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Box" To: david.e.box@linux.intel.com, rajvi.jingar@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, sathyanarayanan.kuppuswamy@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com Subject: [PATCH V2 1/3] platform/x86/intel/vsec: Remove nuisance message Date: Tue, 27 Feb 2024 11:01:32 -0800 Message-Id: <20240227190134.1592072-1-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792088959879086579 X-GMAIL-MSGID: 1792088959879086579 intel_vsec_walk_header() is used to configure features from devices that don't provide a PCI VSEC or DVSEC structure. Some of these features may be unsupported and fail to load. Ignore them silently as we do for unsupported features described by VSEC/DVSEC. Signed-off-by: David E. Box Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Ilpo Järvinen --- V2 - no changes drivers/platform/x86/intel/vsec.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) base-commit: 841c35169323cd833294798e58b9bf63fa4fa1de diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 778eb0aa3479..0fdfaf3a4f5c 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -236,10 +236,7 @@ static bool intel_vsec_walk_header(struct pci_dev *pdev, for ( ; *header; header++) { ret = intel_vsec_add_dev(pdev, *header, info); - if (ret) - dev_info(&pdev->dev, "Could not add device for VSEC id %d\n", - (*header)->id); - else + if (!ret) have_devices = true; } From patchwork Tue Feb 27 19:01:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. 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Box" To: david.e.box@linux.intel.com, rajvi.jingar@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, sathyanarayanan.kuppuswamy@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com Subject: [PATCH V2 2/3] platform/x86/intel/pmc/lnl: Remove SSRAM support Date: Tue, 27 Feb 2024 11:01:33 -0800 Message-Id: <20240227190134.1592072-2-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227190134.1592072-1-david.e.box@linux.intel.com> References: <20240227190134.1592072-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792079872643598181 X-GMAIL-MSGID: 1792079872643598181 A recent PMC firmware change in Lunar Lake caused the pmc_core driver to fail to probe. This is due to a change in the GUID for PMC telemetry coming from the SSRAM device. Until a final release is ready this value may change again. In the meantime, disable the SSRAM support for Lunar Lake so the driver can load and provide some basic functionality. Fixes: 3748dfdae2a6 ("platform/x86/intel/pmc: Add Lunar Lake M support to intel_pmc_core driver") Signed-off-by: David E. Box Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Ilpo Järvinen --- V2 - Removed non-imperative language in changelog. drivers/platform/x86/intel/pmc/lnl.c | 38 +++------------------------- 1 file changed, 4 insertions(+), 34 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c index abad17cdd3d7..068d72504683 100644 --- a/drivers/platform/x86/intel/pmc/lnl.c +++ b/drivers/platform/x86/intel/pmc/lnl.c @@ -13,21 +13,6 @@ #include "core.h" -#define SOCM_LPM_REQ_GUID 0x11594920 - -#define PMC_DEVID_SOCM 0xa87f - -static const u8 LNL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; - -static struct pmc_info lnl_pmc_info_list[] = { - { - .guid = SOCM_LPM_REQ_GUID, - .devid = PMC_DEVID_SOCM, - .map = &lnl_socm_reg_map, - }, - {} -}; - const struct pmc_bit_map lnl_ltr_show_map[] = { {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, @@ -490,7 +475,6 @@ const struct pmc_reg_map lnl_socm_reg_map = { .lpm_sts = lnl_lpm_maps, .lpm_status_offset = MTL_LPM_STATUS_OFFSET, .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, - .lpm_reg_index = LNL_LPM_REG_INDEX, }; #define LNL_NPU_PCI_DEV 0x643e @@ -517,33 +501,19 @@ static int lnl_resume(struct pmc_dev *pmcdev) int lnl_core_init(struct pmc_dev *pmcdev) { int ret; - int func = 2; - bool ssram_init = true; struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC]; lnl_d3_fixup(); pmcdev->suspend = cnl_suspend; pmcdev->resume = lnl_resume; - pmcdev->regmap_list = lnl_pmc_info_list; - ret = pmc_core_ssram_init(pmcdev, func); - /* If regbase not assigned, set map and discover using legacy method */ - if (ret) { - ssram_init = false; - pmc->map = &lnl_socm_reg_map; - ret = get_primary_reg_base(pmc); - if (ret) - return ret; - } + pmc->map = &lnl_socm_reg_map; + ret = get_primary_reg_base(pmc); + if (ret) + return ret; pmc_core_get_low_power_modes(pmcdev); - if (ssram_init) { - ret = pmc_core_ssram_get_lpm_reqs(pmcdev); - if (ret) - return ret; - } - return 0; } From patchwork Tue Feb 27 19:01:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. 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Box" To: david.e.box@linux.intel.com, rajvi.jingar@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, sathyanarayanan.kuppuswamy@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com Subject: [PATCH V2 3/3] platform/x86/intel/pmc/arl: Put GNA device in D3 Date: Tue, 27 Feb 2024 11:01:34 -0800 Message-Id: <20240227190134.1592072-3-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227190134.1592072-1-david.e.box@linux.intel.com> References: <20240227190134.1592072-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792085468299084491 X-GMAIL-MSGID: 1792085468299084491 As is the case on Meteor Lake, the Gaussian & Neural Accelerator (GNA) device is powered by BIOS to D0 by default. If no driver is loaded, this will cause the Package C state to be limited to PC2, leading to significant power consumption and decrease in batter life. Put the GNA device in D3 by default if no driver is loaded for it. Fixes: 83f168a1a437 ("platform/x86/intel/pmc: Add Arrow Lake S support to intel_pmc_core driver") Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen Reviewed-by: Kuppuswamy Sathyanarayanan --- V2 - Better explain the issue in the changelog and spell out GNA. drivers/platform/x86/intel/pmc/arl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/intel/pmc/arl.c index 683ae828276b..34b4cd23bfe5 100644 --- a/drivers/platform/x86/intel/pmc/arl.c +++ b/drivers/platform/x86/intel/pmc/arl.c @@ -673,6 +673,7 @@ static struct pmc_info arl_pmc_info_list[] = { }; #define ARL_NPU_PCI_DEV 0xad1d +#define ARL_GNA_PCI_DEV 0xae4c /* * Set power state of select devices that do not have drivers to D3 * so that they do not block Package C entry. @@ -680,6 +681,7 @@ static struct pmc_info arl_pmc_info_list[] = { static void arl_d3_fixup(void) { pmc_core_set_device_d3(ARL_NPU_PCI_DEV); + pmc_core_set_device_d3(ARL_GNA_PCI_DEV); } static int arl_resume(struct pmc_dev *pmcdev)