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Tue, 27 Feb 2024 18:38:43 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 00D762AD12A; Tue, 27 Feb 2024 18:38:17 +0100 (CET) Received: from localhost (10.252.26.109) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 27 Feb 2024 18:38:16 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v4 01/11] counter: Introduce the COUNTER_COMP_FREQUENCY() macro Date: Tue, 27 Feb 2024 18:37:53 +0100 Message-ID: <20240227173803.53906-2-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> References: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_03,2024-02-27_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792074733348643325 X-GMAIL-MSGID: 1792074733348643325 Now that there are two users for the "frequency" extension, introduce a new COUNTER_COMP_FREQUENCY() macro. Suggested-by: William Breathitt Gray Signed-off-by: Fabrice Gasnier --- include/linux/counter.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/counter.h b/include/linux/counter.h index 702e9108bbb4..03472d7407de 100644 --- a/include/linux/counter.h +++ b/include/linux/counter.h @@ -602,6 +602,9 @@ struct counter_array { #define COUNTER_COMP_FLOOR(_read, _write) \ COUNTER_COMP_COUNT_U64("floor", _read, _write) +#define COUNTER_COMP_FREQUENCY(_read, _write) \ + COUNTER_COMP_SIGNAL_U64("frequency", _read, _write) + #define COUNTER_COMP_POLARITY(_read, _write, _available) \ { \ .type = COUNTER_COMP_SIGNAL_POLARITY, \ From patchwork Tue Feb 27 17:37:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 207369 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2873591dyb; Tue, 27 Feb 2024 10:09:51 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUgvxsOUzb0nJtsu+OOSfz2GAnciLdTtU6vWv6Fbx+p3gVz/k9J6OcUyRTAT8PDD4+cM8CZoRnxKw63ICzCnzsu2vV4bA== X-Google-Smtp-Source: AGHT+IGlGHP+FtZpS9SPzvtnEnW3ppiGZkn0zJfZ8y9U26htrMHlNjo8oG9GGo5BCEoICzBpLCFH X-Received: by 2002:a17:90a:e018:b0:29a:ce5f:4da1 with SMTP id u24-20020a17090ae01800b0029ace5f4da1mr4764723pjy.8.1709057391172; Tue, 27 Feb 2024 10:09:51 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709057391; cv=pass; d=google.com; s=arc-20160816; b=vQjrN6718g62Z3V8NPpyX2d0iJWUWxlsW8vtbVXSlWho2iWK9gixAKgRH+mpCF5tAr Lv5UJUenb6rjCvsw1cKLQTX8oYr9A/Zsv1aNlrJ44EHafl4jcgu706jStVSfG7yMZpwG ROzvqay0IP/ngUXL0H5Y8QHRXzbfilwFh9XiZZXi7PdmdIYBPVTJgdzeXmAtrbkNbuFc i3rhb4kTHhJM2tXIoBFNC+jBu2dfY6Z3b/SJYsdNnELMtrPPJhr9DP8v1J6rYn6/QKRk ecc6qo4jxl6WtrofklXKcijWR9Ol7XvRRx2zFfzKhvGQl8ggPlIZ6bdfQpwRFcB5+Zut SvfQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=kzQQUvSZIpaXW+rkulQUdc2Tl/8nBTPY9MRFsPPGhAc=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=XjWlMqN3eFxgONY40QSIquwUN+cGtNjVPBoCk0IBhQFkn8anXzqtVZuCWCUEW4W2u3 i0TK5LFPaX7hlgSzlhKaJFY5S33efH6XSvzD5d+Us+PhlbG52C+REle7x4uMqgafmlKp WzGBEFoEZevLdlhvrFFNcl+YnDahCNe/hhNU93fhJcCHAn8hCfIjyvq6oFqWlQqVswMK sLIChqrbM5/IspNs58y0vXDy/RkRTc5IUmztog4zH3EEavOsBPry8Kn9mNxmFCMB69Eb gMT52CS7Abmqi3ZKpcYgcKI01Dz94w4MMDEq9X54qG7k/U/BTWI0fK2OJOlLN0cz4t6W n8SQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=CHTjcR9H; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-83747-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83747-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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On stm32-timer: - Quadrature A signal corresponds to timer input ch1, hence "Channel 1" - Quadrature B signal corresponds to timer input ch2, hence "Channel 2". So name these signals after their channel. I suspect it referred to the (unique) quadrature counter support earlier, but the physical input really is CH1/CH2. This will be easier to support other counter modes. Reviewed-by: William Breathitt Gray Signed-off-by: Fabrice Gasnier --- Changes in v4: - Add William's Reviewed-by tag Changes in v2: - Drop the "Quadrature" convention from the signal name, as suggested by William --- drivers/counter/stm32-timer-cnt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 6206d2dc3d47..36d812ddf162 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -279,11 +279,11 @@ static const struct counter_ops stm32_timer_cnt_ops = { static struct counter_signal stm32_signals[] = { { .id = 0, - .name = "Channel 1 Quadrature A" + .name = "Channel 1" }, { .id = 1, - .name = "Channel 1 Quadrature B" + .name = "Channel 2" } }; From patchwork Tue Feb 27 17:37:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 207352 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2855023dyb; Tue, 27 Feb 2024 09:40:15 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWWx1B97pOA7fVG7Ik+oaDAScWLAJY6wDE39f+jcyGGSAvS5nVm3LIYTWaJtC1+shDjo5xXXi+Ki838aP+Ab+aQRpjkJA== X-Google-Smtp-Source: AGHT+IFaiYRRWt+iMecbVvK44RdbZML2j1Jcz7StTUy5FkQjDX9e8kCaPNBDo5ta5zoFg7GEsuL2 X-Received: by 2002:a05:6a20:8f99:b0:1a0:61e4:a940 with SMTP id k25-20020a056a208f9900b001a061e4a940mr1971715pzj.45.1709055614824; Tue, 27 Feb 2024 09:40:14 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709055614; cv=pass; d=google.com; s=arc-20160816; b=HKw8xA2PonmOdlsKa/axhyHE+KPlCo6sYWTy/EnQQRZ/SgF4wUVLIniE1Qf4zKSRK8 LaCSIsvv6A0gblL5uZmUX/aHRfmO357RMc7p43bOfAJ8bLtHg+yV3FYxTYcj7/PMF2Ve 9ep2u+7NwYfoWl88TtDOBtuoptDtEVj5OdXYg5uYuqW+QSdORKygU1TBam6Prdk8KsU4 y69Th8dWJG5euIws4M2Me6wxGD7x72C0E1/U5r7fZf8oIww3PV0py592XGJTKMROnRIt 2nAouvxOM+rcv96cxTaObRl/JJjX3+ig2di3gRiRGZwLIi2uPHRSP5uOtP530nhEy3Rl A/vw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=KVmmLD7PqCyPnZ/PZVStmvG794iivG5lxhLDKuQv7fY=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=p9gc5t6rbXCAnHIvo8LoEyDvMqG7Gh7V7JQDbD8XmebPXtjqzhUidIqRMWp87uK2O5 bjDZndWx04D4AG6k6XkrmCtP2Dvx/vOa7V3bx7QcaNlbaGsPt1folcWoHu+ifwzUc8xI jnLOI8ISIDORcXkheN+IIrs8ufaXWf8X4mOvFUeSI+FvCgsE3RquRMUcyb3RDRPoe4G5 /pj7q/2tyUtXvRmLq5ShDypRhhmF03uwsdfntglkClPJJIuplBeKugGEvQdJiBUSeLnH 4sdoeP+u0HyhB80dlt/a4CgyJjSobPvKVruS9T4Ui2lPg/OxYzRCRTT2tf0nYj6M+wfS s8Jg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=FeXVongi; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-83744-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83744-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Tue, 27 Feb 2024 18:38:43 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 140312AD12E; Tue, 27 Feb 2024 18:38:18 +0100 (CET) Received: from localhost (10.252.26.109) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 27 Feb 2024 18:38:17 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v4 03/11] counter: stm32-timer-cnt: rename counter Date: Tue, 27 Feb 2024 18:37:55 +0100 Message-ID: <20240227173803.53906-4-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> References: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_05,2024-02-27_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792074700079679933 X-GMAIL-MSGID: 1792074700079679933 The STM32 timer may count on various sources or channels. The counter isn't specifically counting on channe1 1. So rename it to avoid a confusion. Reviewed-by: William Breathitt Gray Signed-off-by: Fabrice Gasnier --- Changes in v4: - Add William's Reviewed-by tag --- drivers/counter/stm32-timer-cnt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 36d812ddf162..668e9d1061d3 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -302,7 +302,7 @@ static struct counter_synapse stm32_count_synapses[] = { static struct counter_count stm32_counts = { .id = 0, - .name = "Channel 1 Count", + .name = "STM32 Timer Counter", .functions_list = stm32_count_functions, .num_functions = ARRAY_SIZE(stm32_count_functions), .synapses = stm32_count_synapses, From patchwork Tue Feb 27 17:37:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 207353 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2855244dyb; Tue, 27 Feb 2024 09:40:43 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXDaF3zP8heX4MtI4newmFc3P3zeZ5HqB38TtoQGpGgxB8EvZMDO7+UK+Bd5MYSF7Vct93cUcro5ggporPloDe+HgpcWg== X-Google-Smtp-Source: AGHT+IGJgd6d5+3ZXiiqpvlxcIQNUxe8SJaXTuuxb05tdKEMyJXX0xvI6fM4aummAJn+n1CopHnw X-Received: by 2002:a05:6512:1054:b0:512:bb33:2eab with SMTP id c20-20020a056512105400b00512bb332eabmr8635526lfb.58.1709055643260; Tue, 27 Feb 2024 09:40:43 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709055643; cv=pass; d=google.com; s=arc-20160816; b=cTNbkAat8tA7ME5vd1S+BQnfmOyn0fu40/obFivRao0gaVfYZ1MgvGaAe3eo3X2ff2 2zwq0rgCsMMR4UHbTzyzUNxYr2zsQN1USclobO+BCJrG1ScGOaO2LKMoQD1OoJBWbRex aVP+sdoMGuhUMahrQkXP8euvYXOSbWLkWs9IRo0p34xxHqbHNOfiZu6h5e2kZlhzyr3e cOWQf844zZBnTdXI9i6QgLw53dDBUs4NIG61+aqN3uR51DkgdGqYjNINK5UJjaKr26sO SH5G4msMx09OgKI4cZudVnVBya41ygL7luzTJzCk7QKS7jG7tU3rygGVzK1d0i5xJ5UT THOA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+7nWDb9ZWuayfFkASgiJUL4avZyU6WuY7zpZjhvk6Uc=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=iYAz1oAiyo3n9m9EFGyUBI4ErjkTwED9SqgTvjB7yUEpubSCHj5zsmnUkV4iF5YoJS CQ+TkQe0yz/IqdxWwwQ4uwU8NP6OjLSge0ODS7XN9dAyNme5MWvemvhtYCnWLm4cXlXF hMVOS2GYsBoBTCaHsbeV8rzAGjD45PK2YkKWVUoSgg5CFxQedc+2VI2g8rfX1EK/4x20 pHuy9t3e+7RaHdmzkaekTZROeG89a2p1QmtJhbXH1djAe56t/GbeH0YNXT0jYuvf6rGS 2hmZoXaslflGrpilmz69pQVzZYDr0LOrrYygdKYXuk+BVN7xKD7s1i3u29LthgJV60Cr xebQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=wVWdnsZ3; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-83746-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83746-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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There are no intended functional changes here. Reviewed-by: William Breathitt Gray Signed-off-by: Fabrice Gasnier --- Changes in v4: - Add William's Reviewed-by tag Changes in v3: New patch split from "counter: stm32-timer-cnt: introduce clock signal" --- drivers/counter/stm32-timer-cnt.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 668e9d1061d3..c34747d7857e 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -21,6 +21,9 @@ #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \ TIM_CCER_CC2P | TIM_CCER_CC2NP) +#define STM32_CH1_SIG 0 +#define STM32_CH2_SIG 1 + struct stm32_timer_regs { u32 cr1; u32 cnt; @@ -247,14 +250,14 @@ static int stm32_action_read(struct counter_device *counter, return 0; case COUNTER_FUNCTION_QUADRATURE_X2_A: /* counts up/down on TI1FP1 edge depending on TI2FP2 level */ - if (synapse->signal->id == count->synapses[0].signal->id) + if (synapse->signal->id == STM32_CH1_SIG) *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; else *action = COUNTER_SYNAPSE_ACTION_NONE; return 0; case COUNTER_FUNCTION_QUADRATURE_X2_B: /* counts up/down on TI2FP2 edge depending on TI1FP1 level */ - if (synapse->signal->id == count->synapses[1].signal->id) + if (synapse->signal->id == STM32_CH2_SIG) *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; else *action = COUNTER_SYNAPSE_ACTION_NONE; @@ -278,11 +281,11 @@ static const struct counter_ops stm32_timer_cnt_ops = { static struct counter_signal stm32_signals[] = { { - .id = 0, + .id = STM32_CH1_SIG, .name = "Channel 1" }, { - .id = 1, + .id = STM32_CH2_SIG, .name = "Channel 2" } }; @@ -291,12 +294,12 @@ static struct counter_synapse stm32_count_synapses[] = { { .actions_list = stm32_synapse_actions, .num_actions = ARRAY_SIZE(stm32_synapse_actions), - .signal = &stm32_signals[0] + .signal = &stm32_signals[STM32_CH1_SIG] }, { .actions_list = stm32_synapse_actions, .num_actions = ARRAY_SIZE(stm32_synapse_actions), - .signal = &stm32_signals[1] + .signal = &stm32_signals[STM32_CH2_SIG] } }; From patchwork Tue Feb 27 17:37:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 207355 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2855876dyb; Tue, 27 Feb 2024 09:42:00 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU1CIaczVlVQnbInHJEYkmT0o8+T4kY7LaDz9D1GPE0vKOyVF/90VZYVvl5o5HaV/5tgsVHsOtJ2no9bhaClWVYWMIFKw== X-Google-Smtp-Source: AGHT+IEm5523NUUzl4YyL9nOywlOts1ek6ghx12P+1gWMI63LzYxbaInAY0Y1S6LJITXuh/RJcGC X-Received: by 2002:aa7:db55:0:b0:566:1725:1c86 with SMTP id n21-20020aa7db55000000b0056617251c86mr3657736edt.12.1709055720671; Tue, 27 Feb 2024 09:42:00 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709055720; cv=pass; d=google.com; s=arc-20160816; b=v79QxLRDKLa7l2XFSdDx7PzGMuCJcYjOtRFcAXScC/+XmrYlqGFL4m/wl9AgbrfYeE nEnLcX+3RLN6Nc4n7QZw0j6jLK7uUhkUk0JtPD3wFUqZm3baEOd5ag94uVCqLijygusl njjNf/lmRFvrE8pPRCgQDAevcaJzgXLVtdo/kuo0Li+DUDiCDyjybRqHPhDCM+hamhNK g1uVgoLXsq7P4VknVyFUzHevMZlCC0XxkilKw22z3MNo/UKJEda8NydLWDawf3qPguw1 ASbdF9hrHT8SVRX33dpfdl2tSCp/XrhNc9/mMei5UnsyBVNtObayOuztIuJw6YgUwjHc G/ug== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=gV6cLaC3QIdWwPldH7ryzYKtFzveQ4F+ZEi3MqaDLGQ=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=sZxAHyRXRFhlD/XT1nYAEDCnV6q4BB6Ov9nk8CsRIu/CCfMjJoXrVeSgngiij5O7Q2 pe2921x0dkZQ/AKQ3Km/fOLFtkrOqZkGz7aIjiTqGMCOgMLc0jXnboPYbL4DdTqkxvQn DdqzBYdff0jl1JbUdDMGjtQuvnbvkLo2fK7hKhO3KEiWfGsFT5sIqnDfJ/scICFCn9Jz Q9StxzGTg/ZlMkDA+UvDrna6GTWG3Pm/aZ13cEiJ0NnS7Cak/IZHAGCI/FJXpR3v7nqI GCYOvYz1+7zyLGIvt+HtHqUlCkzfjMKVqTQRBQGZHFOOHeEHhYZAsHf10O9j4Yc9sXNE KnJw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=A2Q+wTCW; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-83752-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83752-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Tue, 27 Feb 2024 18:39:53 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 28F832AD127; Tue, 27 Feb 2024 18:39:29 +0100 (CET) Received: from localhost (10.252.26.109) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 27 Feb 2024 18:39:28 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v4 05/11] counter: stm32-timer-cnt: introduce clock signal Date: Tue, 27 Feb 2024 18:37:57 +0100 Message-ID: <20240227173803.53906-6-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> References: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_05,2024-02-27_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792074811385235071 X-GMAIL-MSGID: 1792074811385235071 Introduce the internal clock signal, used to count when in simple rising function. Also add the "frequency" extension to the clock signal. With this patch, signal action reports a consistent state when "increase" function is used, and the counting frequency: $ echo increase > function $ grep -H "" signal*_action signal0_action:none signal1_action:none signal2_action:rising edge $ echo 1 > enable $ cat count 25425 $ cat count 44439 $ cat ../signal2/frequency 208877930 Signed-off-by: Fabrice Gasnier --- Changes in v4: - Introduce COUNTER_COMP_FREQUENCY() macro as suggested by William in [1] [1] https://lore.kernel.org/lkml/ZZwm7ZyrL7vFn0Xd@ubuntu-server-vm-macos/ - Remove "Signal" from "Clock Signal" name which is redundant with sysfs path that already has signal as a name. Changes in v3: - split the patch in 3 parts: signal definition becomes a pre-cursor patch, add the "prescaler" extension in its own patch. - Move the clock signal at the end of the signals array, so existing userspace programs that may rely on signal0 being "Channel 1" for example will remain compatible. --- drivers/counter/stm32-timer-cnt.c | 53 ++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index c34747d7857e..b914c87b6f10 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -23,6 +23,7 @@ #define STM32_CH1_SIG 0 #define STM32_CH2_SIG 1 +#define STM32_CLOCK_SIG 2 struct stm32_timer_regs { u32 cr1; @@ -226,6 +227,10 @@ static struct counter_comp stm32_count_ext[] = { stm32_count_ceiling_write), }; +static const enum counter_synapse_action stm32_clock_synapse_actions[] = { + COUNTER_SYNAPSE_ACTION_RISING_EDGE, +}; + static const enum counter_synapse_action stm32_synapse_actions[] = { COUNTER_SYNAPSE_ACTION_NONE, COUNTER_SYNAPSE_ACTION_BOTH_EDGES @@ -246,7 +251,10 @@ static int stm32_action_read(struct counter_device *counter, switch (function) { case COUNTER_FUNCTION_INCREASE: /* counts on internal clock when CEN=1 */ - *action = COUNTER_SYNAPSE_ACTION_NONE; + if (synapse->signal->id == STM32_CLOCK_SIG) + *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; + else + *action = COUNTER_SYNAPSE_ACTION_NONE; return 0; case COUNTER_FUNCTION_QUADRATURE_X2_A: /* counts up/down on TI1FP1 edge depending on TI2FP2 level */ @@ -264,7 +272,10 @@ static int stm32_action_read(struct counter_device *counter, return 0; case COUNTER_FUNCTION_QUADRATURE_X4: /* counts up/down on both TI1FP1 and TI2FP2 edges */ - *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; + if (synapse->signal->id == STM32_CH1_SIG || synapse->signal->id == STM32_CH2_SIG) + *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; + else + *action = COUNTER_SYNAPSE_ACTION_NONE; return 0; default: return -EINVAL; @@ -279,7 +290,30 @@ static const struct counter_ops stm32_timer_cnt_ops = { .action_read = stm32_action_read, }; +static int stm32_count_clk_get_freq(struct counter_device *counter, + struct counter_signal *signal, u64 *freq) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + + *freq = clk_get_rate(priv->clk); + + return 0; +} + +static struct counter_comp stm32_count_clock_ext[] = { + COUNTER_COMP_FREQUENCY(stm32_count_clk_get_freq, NULL), +}; + static struct counter_signal stm32_signals[] = { + /* + * Need to declare all the signals as a static array, and keep the signals order here, + * even if they're unused or unexisting on some timer instances. It's an abstraction, + * e.g. high level view of the counter features. + * + * Userspace programs may rely on signal0 to be "Channel 1", signal1 to be "Channel 2", + * and so on. When a signal is unexisting, the COUNTER_SYNAPSE_ACTION_NONE can be used, + * to indicate that a signal doesn't affect the counter. + */ { .id = STM32_CH1_SIG, .name = "Channel 1" @@ -287,7 +321,13 @@ static struct counter_signal stm32_signals[] = { { .id = STM32_CH2_SIG, .name = "Channel 2" - } + }, + { + .id = STM32_CLOCK_SIG, + .name = "Clock", + .ext = stm32_count_clock_ext, + .num_ext = ARRAY_SIZE(stm32_count_clock_ext), + }, }; static struct counter_synapse stm32_count_synapses[] = { @@ -300,7 +340,12 @@ static struct counter_synapse stm32_count_synapses[] = { .actions_list = stm32_synapse_actions, .num_actions = ARRAY_SIZE(stm32_synapse_actions), .signal = &stm32_signals[STM32_CH2_SIG] - } + }, + { + .actions_list = stm32_clock_synapse_actions, + .num_actions = ARRAY_SIZE(stm32_clock_synapse_actions), + .signal = &stm32_signals[STM32_CLOCK_SIG] + }, }; static struct counter_count stm32_counts = { From patchwork Tue Feb 27 17:37:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 207356 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2856117dyb; Tue, 27 Feb 2024 09:42:31 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWqqxXtnOFA2mI1KLb4LDnziYEZu9KlXABuWNqkPBAtef3PJi6WLcCg2hKpL8EyrDiOobY3wb/xDDJCAVEwGDKRxb8Wcw== X-Google-Smtp-Source: AGHT+IHBFnghZ4j1La6HEwK/Q4G86s9yAgvOa1Gu1TACwcYCyT/DAh08nrWtnL9TIYJGlnQOZGMX X-Received: by 2002:a05:622a:347:b0:42e:32d5:dd17 with SMTP id r7-20020a05622a034700b0042e32d5dd17mr13724028qtw.24.1709055750843; Tue, 27 Feb 2024 09:42:30 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709055750; cv=pass; d=google.com; s=arc-20160816; b=azHjweVRpCdYkbdWZNpMAbATdN6WHMBUhSpAZv3WtqPjbTOBZQdt4cEqQZmmZjGJNT /nDa2p7v4K2GdMGMJIwV583x+9/hPlTQUTO5x4ET25Y8KL6/3gWlA46VR+eCFL9c80wJ QnV9Dfv81jxL8PDv+vKUXEiAqFKJ4KqYOu8VHkFViGvAR8QKlGCz0swnFVVALlVZ9Ece 1aG2bAWhQyeLa3M+81rEp/uHef8pW6ROVE3RisDq7+ZesZkTiZh4utJLQvtYSbDK3pBH dDIqFDaqmc/LuioDhcdwumJrnOZoNoV0A3X/z7fakl9b9PZv6M9U0PexfaUIFgIh9Wjr myaA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=23cef0f6RemlkBcr/fQtp0mL/3K1zOCA/BsyeJEat+c=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=db/HtGAGvB1w9AhOCanp5AyoCiy3mE/n+kxWypK8N41pFnQusPm3kfxMcEJgOFOBc2 8Ot6EGjO9IaGSarPnPZH0UCvv1dUTDUwsSB0wDqNoMkyizOOUc7YEHXpQrbCYX752KPi lh+DO6dbmnCipB3NhQZnNBmEocyrU96Sw9SEQIgBCXXEvkHnkLHyXFUjKaEJSX9T1Acn NVIkNhTlzuSiY6BYT5R5Yf4Di6AVsrkklvaMrmTdGkKst5XTATd61MRxFeDHasXB31kU nltXA/bqMe4rEZsJPhPpf/wynvd8m1CCWUfJsj54GjwHoS5pFK1aKjt26jDD2RSKX6aw K6JQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=VApBCMRA; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-83753-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83753-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Tue, 27 Feb 2024 18:39:59 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 13A452AD128; Tue, 27 Feb 2024 18:39:31 +0100 (CET) Received: from localhost (10.252.26.109) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 27 Feb 2024 18:39:28 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v4 06/11] counter: stm32-timer-cnt: add counter prescaler extension Date: Tue, 27 Feb 2024 18:37:58 +0100 Message-ID: <20240227173803.53906-7-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> References: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_05,2024-02-27_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792074842975315568 X-GMAIL-MSGID: 1792074842975315568 There's a prescaler in between the selected input signal used for counting (CK_PSC), and the counter input (CK_CNT). So add the "prescaler" extension to the counter. Reviewed-by: William Breathitt Gray Signed-off-by: Fabrice Gasnier --- Changes in v4: - Add William's Reviewed-by tag Changes in v3: - New patch split from "counter: stm32-timer-cnt: introduce clock signal" --- drivers/counter/stm32-timer-cnt.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index b914c87b6f10..e0709dd7dcfd 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -220,11 +220,40 @@ static int stm32_count_enable_write(struct counter_device *counter, return 0; } +static int stm32_count_prescaler_read(struct counter_device *counter, + struct counter_count *count, u64 *prescaler) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 psc; + + regmap_read(priv->regmap, TIM_PSC, &psc); + + *prescaler = psc + 1; + + return 0; +} + +static int stm32_count_prescaler_write(struct counter_device *counter, + struct counter_count *count, u64 prescaler) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 psc; + + if (!prescaler || prescaler > MAX_TIM_PSC + 1) + return -ERANGE; + + psc = prescaler - 1; + + return regmap_write(priv->regmap, TIM_PSC, psc); +} + static struct counter_comp stm32_count_ext[] = { COUNTER_COMP_DIRECTION(stm32_count_direction_read), COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), COUNTER_COMP_CEILING(stm32_count_ceiling_read, stm32_count_ceiling_write), + COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read, + stm32_count_prescaler_write), }; static const enum counter_synapse_action stm32_clock_synapse_actions[] = { From patchwork Tue Feb 27 17:37:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 207360 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2861017dyb; Tue, 27 Feb 2024 09:52:19 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCW/KxuKRa+MbNC8/zXBx2xaWYbPgq9216hEVBrFMMDEbAvDjWgYEkH9iyuyl+Pla/KIpMHv2qsSYmxI/Gy2Dv0ZOaeWBA== X-Google-Smtp-Source: AGHT+IGj7PjY0JVevD3H1NpiH9WGwunMWQLWcL6HT1nw/Vetcwvv+7l6/ZYSZEbqQ1W4hIpb795g X-Received: by 2002:a05:6a00:4ba4:b0:6e4:148e:2946 with SMTP id kt4-20020a056a004ba400b006e4148e2946mr10051257pfb.25.1709056338875; Tue, 27 Feb 2024 09:52:18 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709056338; cv=pass; d=google.com; s=arc-20160816; b=ZRG3iToD9a7JfjusYmp17M2a/Xjao4+nQ1qe3kC1LRLjevJX+wEWmqQ+aJGMttykdl g7SgPLn4j8P8+JR7wsimgLY8HES3PmOJV5BoV/wqoFdiDEjtt/+yPxK+aj1KccFjH43a gGfZJMGYdwgJlGPQE+N8jInkz2q61b8qgeYuVhWDOapV2JhEniwmlj+8MobbdjJHEZ7k IXH81eITuJDPbcpV4qBbu+biAhuHwEWp0S4iHAGTV5iZm22PqjNR+PDlUOffOZfFVLu3 oR2Y0xrdZ58v0PetChjjSFNcHHL62hCEVASefTGbYiv/plBuUmLeMvWUVmAVnij7eK8t lzYw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=0rgZzVeIciD13wzGBJT0MITILPsQC7SVf3hIqPrhzFs=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=0kfnYrRuiNAsx4QDg7r0MxWq9aPuW0Ms/Ad1J+fJot9+oGQKnuwv9jQMAuXQYHQl/B 9Aq/CxzC91F3ZIEgCG42fvW/HLGLUo7LDj0u/LoVIVUQZri74t679J2udKTkvsuwFg9J RgMG7KPBUDmevXte491hAesPHRW/ZDEk5plhmYhgxZ2M9LCtrOtiZsCGkYYd2nOEmnWo YKuuiBUZMfbG+DAXzRvN89GQjBUPq8p8gYzuq1+EWqCzfGAX+diT6SRnuKD/4ipPFM5I QrHdybyPllGpjQQlFA7GDnd2oEYe6LVTmLVynZgc5QG973R+abumf2EMbdSo3+B4xBLO sXaA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=SbOZ33wP; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-83754-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83754-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Tue, 27 Feb 2024 18:39:59 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 28A832AD132; Tue, 27 Feb 2024 18:39:30 +0100 (CET) Received: from localhost (10.252.26.109) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 27 Feb 2024 18:39:29 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v4 07/11] counter: stm32-timer-cnt: add checks on quadrature encoder capability Date: Tue, 27 Feb 2024 18:37:59 +0100 Message-ID: <20240227173803.53906-8-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> References: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_05,2024-02-27_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792075459191590980 X-GMAIL-MSGID: 1792075459191590980 This is a precursor patch to support capture channels on all possible channels and stm32 timer types. Original driver was intended to be used only as quadrature encoder and simple counter on internal clock. So, add a check on encoder capability, so the driver may be probed for timer instances without encoder feature. This way, all timers may be used as simple counter on internal clock, starting from here. Encoder capability is retrieved by using the timer index (originally in stm32-timer-trigger driver and dt-bindings). The need to keep backward compatibility with existing device tree lead to parse aside trigger node. Signed-off-by: Fabrice Gasnier --- Changes in v4: - drop idx from struct stm32_timer_cnt as unused after probing - directly use dev struct in stm32_timer_cnt_probe_encoder routine. Changes in v3: - New patch split from: "counter: stm32-timer-cnt: populate capture channels and check encoder" - return -EOPNOTSUPP when encoder function isn't supported by the timer instance. --- drivers/counter/stm32-timer-cnt.c | 55 +++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index e0709dd7dcfd..144e040fa457 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,7 @@ struct stm32_timer_cnt { u32 max_arr; bool enabled; struct stm32_timer_regs bak; + bool has_encoder; }; static const enum counter_function stm32_count_functions[] = { @@ -111,12 +113,18 @@ static int stm32_count_function_write(struct counter_device *counter, sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED; break; case COUNTER_FUNCTION_QUADRATURE_X2_A: + if (!priv->has_encoder) + return -EOPNOTSUPP; sms = TIM_SMCR_SMS_ENCODER_MODE_1; break; case COUNTER_FUNCTION_QUADRATURE_X2_B: + if (!priv->has_encoder) + return -EOPNOTSUPP; sms = TIM_SMCR_SMS_ENCODER_MODE_2; break; case COUNTER_FUNCTION_QUADRATURE_X4: + if (!priv->has_encoder) + return -EOPNOTSUPP; sms = TIM_SMCR_SMS_ENCODER_MODE_3; break; default: @@ -388,6 +396,49 @@ static struct counter_count stm32_counts = { .num_ext = ARRAY_SIZE(stm32_count_ext) }; +/* encoder supported on TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 */ +#define STM32_TIM_ENCODER_SUPPORTED (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(7)) + +static const char * const stm32_timer_trigger_compat[] = { + "st,stm32-timer-trigger", + "st,stm32h7-timer-trigger", +}; + +static int stm32_timer_cnt_probe_encoder(struct device *dev, + struct stm32_timer_cnt *priv) +{ + struct device *parent = dev->parent; + struct device_node *tnode = NULL, *pnode = parent->of_node; + int i, ret; + u32 idx; + + /* + * Need to retrieve the trigger node index from DT, to be able + * to determine if the counter supports encoder mode. It also + * enforce backward compatibility, and allow to support other + * counter modes in this driver (when the timer doesn't support + * encoder). + */ + for (i = 0; i < ARRAY_SIZE(stm32_timer_trigger_compat) && !tnode; i++) + tnode = of_get_compatible_child(pnode, stm32_timer_trigger_compat[i]); + if (!tnode) { + dev_err(dev, "Can't find trigger node\n"); + return -ENODATA; + } + + ret = of_property_read_u32(tnode, "reg", &idx); + if (ret) { + dev_err(dev, "Can't get index (%d)\n", ret); + return ret; + } + + priv->has_encoder = !!(STM32_TIM_ENCODER_SUPPORTED & BIT(idx)); + + dev_dbg(dev, "encoder support: %s\n", priv->has_encoder ? "yes" : "no"); + + return 0; +} + static int stm32_timer_cnt_probe(struct platform_device *pdev) { struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); @@ -409,6 +460,10 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) priv->clk = ddata->clk; priv->max_arr = ddata->max_arr; + ret = stm32_timer_cnt_probe_encoder(dev, priv); + if (ret) + return ret; + counter->name = dev_name(dev); counter->parent = dev; counter->ops = &stm32_timer_cnt_ops; From patchwork Tue Feb 27 17:38:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 207375 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2884054dyb; Tue, 27 Feb 2024 10:23:58 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXLCj3avZkS35XrmIVJE5LZhoQgOdg1K//LbhFCg6jU8shH7der0Z1YpUwem54vmkVgvDTLFMB8fAdhsyV+jX0SpBsfrg== X-Google-Smtp-Source: AGHT+IFaOWWUNGiF9OnwDJgKwqxKhpTeFau1YBZG2l3ITWtBnmjQm/YNHSHnBI5McoTP9RZf90zV X-Received: by 2002:a17:903:41cb:b0:1dc:38c7:ba1a with SMTP id u11-20020a17090341cb00b001dc38c7ba1amr13890447ple.25.1709058238598; Tue, 27 Feb 2024 10:23:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709058238; cv=pass; d=google.com; s=arc-20160816; b=z3aQY4AGn/QA5dKzWMxAT/8fvsWkfkHTm8SVSzVh6u2o6Crw0JABJfCJEFwc9pmz7h lka64LO+QKQ70uj2yX/AP/Qf0l3XTr+vcmbhD1PD6617ZOWXC2HiLsP6Rc5Z7rKaKalB lPGbSrJyOb6V38ZBsi+EBa7E5ku23uQXQICTgEbmmNgWfgH3NMHWpcTgVubKl4XvS1bv hRdFFXp9taGwvZM4NF+pNW5B+mBvn9GK7hV11FgMKSE7irnhjSgPe7oUB8MHNg8T1Qv9 BJ91YxmCnn6/Ol2K35UTu4UJ5KXDWGGh7xKsa1Zrr4IYun5DARoGSAnBHl9t8KGAktNS WgHA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=5kAJdzvKyNBF4DCTisnMcXkF/FxsQlkKDl8EbRW2k+4=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=RrA8hJ2mVk2r6KLIREQglchGCV1lhOVgCpWt6wqwjikF167a7G7q3cvbIWqY64F3Cu ATN4NvQCu6FH1cQcBOmzEWTNAo0GoAanpS0qdjIjNmaym83XWBtpz0FsB1X73O13q4pA q2qwtyXGs217l0i5DjIGAXMAxuVv0ZO/D7CXKo40V8qsM8w2JYHe1E0mQvIIH4pTldad gFWATredeACK/xFp1SjMYT08iUgn2PKRIiK0RWx9VFnD9kyZhXdsrose14su/NfmhJTh cSSV3G25JuyClslxksDM1OPx1xy7DjJ8Scmu7LQt+c/NUg+jDB6coIwcz/F9hZPPmgoK Ermw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=bS+u84A6; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-83751-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83751-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Tue, 27 Feb 2024 18:39:53 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0F61C2AD131; Tue, 27 Feb 2024 18:39:30 +0100 (CET) Received: from localhost (10.252.26.109) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 27 Feb 2024 18:39:29 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v4 08/11] counter: stm32-timer-cnt: introduce channels Date: Tue, 27 Feb 2024 18:38:00 +0100 Message-ID: <20240227173803.53906-9-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> References: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_05,2024-02-27_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792077451764388504 X-GMAIL-MSGID: 1792077451764388504 Simply add channels 3 and 4 that can be used for capture. Statically add them, despite some timers doesn't have them. Rather rely on stm32_action_read that will report "none" action for these currently. Reviewed-by: William Breathitt Gray Signed-off-by: Fabrice Gasnier --- Changes in v4: - Add William's Reviewed-by tag Changes in v3: - New patch split from: "counter: stm32-timer-cnt: populate capture channels and check encoder" --- drivers/counter/stm32-timer-cnt.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 144e040fa457..66039d1b3642 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -25,6 +25,8 @@ #define STM32_CH1_SIG 0 #define STM32_CH2_SIG 1 #define STM32_CLOCK_SIG 2 +#define STM32_CH3_SIG 3 +#define STM32_CH4_SIG 4 struct stm32_timer_regs { u32 cr1; @@ -365,6 +367,14 @@ static struct counter_signal stm32_signals[] = { .ext = stm32_count_clock_ext, .num_ext = ARRAY_SIZE(stm32_count_clock_ext), }, + { + .id = STM32_CH3_SIG, + .name = "Channel 3" + }, + { + .id = STM32_CH4_SIG, + .name = "Channel 4" + }, }; static struct counter_synapse stm32_count_synapses[] = { @@ -383,6 +393,16 @@ static struct counter_synapse stm32_count_synapses[] = { .num_actions = ARRAY_SIZE(stm32_clock_synapse_actions), .signal = &stm32_signals[STM32_CLOCK_SIG] }, + { + .actions_list = stm32_synapse_actions, + .num_actions = ARRAY_SIZE(stm32_synapse_actions), + .signal = &stm32_signals[STM32_CH3_SIG] + }, + { + .actions_list = stm32_synapse_actions, + .num_actions = ARRAY_SIZE(stm32_synapse_actions), + .signal = &stm32_signals[STM32_CH4_SIG] + }, }; static struct counter_count stm32_counts = { From patchwork Tue Feb 27 17:38:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 207359 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2860975dyb; Tue, 27 Feb 2024 09:52:12 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWxBguZCCXjXb+SsJ46bt/XVGtKHASUjPWg160zaSqz1ZPfYngRgRNMyFpLspvkbSPUernPrtjp59N0rAKC88nVX0p8Gg== X-Google-Smtp-Source: AGHT+IFNvPb2/oB0x/j7glhcj2Q7knPPvaavbB3RXkEjrUu4jDe29Vr4z+inHVLilKPPvifW/O05 X-Received: by 2002:a05:6a00:26c1:b0:6e5:44f1:1183 with SMTP id p1-20020a056a0026c100b006e544f11183mr3083398pfw.14.1709056332720; Tue, 27 Feb 2024 09:52:12 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709056332; cv=pass; d=google.com; s=arc-20160816; b=bF0yZQX11sPu2cxy/UwTiX5rYuW9zUb6k4pF5S5MzHy6eM3wk1Oi9+tOC4LVL7TVYZ C2VHsQhCSB5f8GLfT84k/xFyQuV+mkBlA3qUcrRTV3HocBaSuW/oRiBvwZhbe7R5fsZ/ 68jKdY0cejRfXQRY+UWY7NEQYFq9lIOId7T4PkSAbpFKljXnT8N23DuE7kNik+Dk4OnY E9cBMqR5Lb5Y2AXo61iECO+Gls+k2NVUInQ0Lg+DyW9j57870LCn4LQOoAS+RNBL+sHP 19asoyQRdbOaI9WDS7YfEv4709hbr0XOwCtYiw6sC5og+LfZAX/ivwV0ljyOi63l0zKO xJjA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=oK3u5VA04nVMBTkalarhGWM8df4YU9kjhwAaKc3RoBs=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=WeG7TsjBsg2oAsGEOy9DSWKriwOUERLI0OR8b/dv3aoncnMhgmwzq0PxAvU6LdBZOY RKfa+7woWzxK/ykFPRqnrEITmDp3DuHRaTIN7fnZVJACrFU/9pU8im69b6Hek59IpNq9 x1QOcc/rIY2gMSXE9/g1KeSye8i2Woxn0ZnRSKwoVqOtJ6T5sOGzczhABJVHfTxE5beH zmOoBupNqTHMObJ/VfQxa6qXfVOspNX6UCBUh2dg8CdT8isSbzXRK8NdzG4yUcwGiUOt 2Clu7RkjAx4QRVyWJ3CmbFh3eHaHlLXBl0IZLCnHfGlEYV+/RE7Gqi+bh+BZOYBWBQ0V CanQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=eD9ZphYg; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-83755-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83755-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Take care to restore the register original value. This is a precursor patch to support capture channels. Signed-off-by: Fabrice Gasnier --- Changes in v4: - directly use dev struct in stm32_timer_cnt_detect_channels routine. Changes in v3: - New patch split from: "counter: stm32-timer-cnt: populate capture channels and check encoder" --- drivers/counter/stm32-timer-cnt.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 66039d1b3642..710437d3b33f 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -42,6 +42,7 @@ struct stm32_timer_cnt { bool enabled; struct stm32_timer_regs bak; bool has_encoder; + unsigned int nchannels; }; static const enum counter_function stm32_count_functions[] = { @@ -416,6 +417,20 @@ static struct counter_count stm32_counts = { .num_ext = ARRAY_SIZE(stm32_count_ext) }; +static void stm32_timer_cnt_detect_channels(struct device *dev, + struct stm32_timer_cnt *priv) +{ + u32 ccer, ccer_backup; + + regmap_read(priv->regmap, TIM_CCER, &ccer_backup); + regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE); + regmap_read(priv->regmap, TIM_CCER, &ccer); + regmap_write(priv->regmap, TIM_CCER, ccer_backup); + priv->nchannels = hweight32(ccer & TIM_CCER_CCXE); + + dev_dbg(dev, "has %d cc channels\n", priv->nchannels); +} + /* encoder supported on TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 */ #define STM32_TIM_ENCODER_SUPPORTED (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(7)) @@ -484,6 +499,8 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) if (ret) return ret; + stm32_timer_cnt_detect_channels(dev, priv); + counter->name = dev_name(dev); counter->parent = dev; counter->ops = &stm32_timer_cnt_ops; From patchwork Tue Feb 27 17:38:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 207372 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2878490dyb; Tue, 27 Feb 2024 10:16:18 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU0nCpZp1gMs2SQrjoEnngNuy65pzu9yxk04dLMdFk3J8dVk9KTzUqAkFTSIQCjQMtTWI8iho4P1XEoCUH5SmJ5RRN5Rw== X-Google-Smtp-Source: AGHT+IGTORoEHAedDm9ibr5CdDB2lEYgIgu/FA/nuTYoCZ31Ify+NqMIs+nwejOubRUFK4rEU/KW X-Received: by 2002:a05:6a00:2310:b0:6e4:cf7c:6c28 with SMTP id h16-20020a056a00231000b006e4cf7c6c28mr11504070pfh.22.1709057778489; Tue, 27 Feb 2024 10:16:18 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709057778; cv=pass; d=google.com; s=arc-20160816; b=duZASTdyQapext6rnnTHWBmQ02dC/38CwxZCqaWGV8bpu9X/HZy0M+6qUxGeXYlfvc rOJp8TDL2PtdfkZr6pftoLJfrLUCqDVsTxCquzk3fjecgZTo2aZ0PjxfrtC2JsK6LcnT XZEi74ZncrWWFUR5YrCbnApunKTqf8sZAgL3TwRPqtWLuHRWLPvi0QtP3zfy/799pFjA aCiaYbd5etFjGN6frBT4SEq6otcsI5zZov75OcIa/navJnIaGDqfHczewaI8XZeeQ60s IxxRcqqtZTdWMGVQES7FsSLsoBeFeMVYG53jDLCdovUEl3aCwtIz87tY4NWQbcIVOuES Nr6w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=/Q/TfEHS7ktUk+Ck1mLVERqp7dICZ7Ag0Jf4kVHfD1E=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=XyDKlev5apv2C/OGpF2yZHgxkj7hKwnOToLTPsM3jH88iHcjgBgWDD4WzLiIaTlNRg LBSf1ZS726qUylLcSeG1OQhCzO7OGRKheYyiw/6ytoWAnrG5IM09c1gK/dnY2VaUVqM+ c414Awgwp9b7LcFYqXKX4rkYMNth+3uv2YrABwbdxu5NxddNZhweKactemhoVD2QcV9B HTucPhkfVHdnnUob5NcFQQTNgfczuToQOvlYDu2O/aPsDhmtrCfZxA7KBl03RvjIQ03P 38WPEPcFNReyQ/J5LDgHVzNzzFikf9tvPIHrqlmtaIlOeTtl5Dv4hoKdvfvyc0evtgQD vfpA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=Ls+hIJEs; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-83756-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83756-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Tue, 27 Feb 2024 18:41:06 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1270E2AD154; Tue, 27 Feb 2024 18:40:41 +0100 (CET) Received: from localhost (10.252.26.109) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 27 Feb 2024 18:40:40 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v4 10/11] counter: stm32-timer-cnt: add support for overflow events Date: Tue, 27 Feb 2024 18:38:02 +0100 Message-ID: <20240227173803.53906-11-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> References: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_05,2024-02-27_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792076969324793180 X-GMAIL-MSGID: 1792076969324793180 Add support overflow events. Also add the related validation and configuration routine. Register and enable interrupts to push events. STM32 Timers can have either 1 global interrupt, or 4 dedicated interrupt lines. Request only the necessary interrupt, e.g. either global interrupt that can report all event types, or update interrupt only for overflow event. Signed-off-by: Fabrice Gasnier --- Changes in v4: - drop *irq from stm32_timer_cnt, as only used at probe time. - Declare nb_ovf as u64 instead of atomic_t, to fit the API, and avoid unsuitable range check. This also avoid checking for negative value. Use a spin_lock to protect it, as it is updated in interrupt context. - use regmap_test_bits() to avoid intermediate variable. - fix error message in probe (ddata->irq[0] instead of ddata->irq[i]) - move mfd header to subsequent patch, where the defines are actually used. Changes in v3: - patch split from: "counter: stm32-timer-cnt: add support for events", to focus on the overflow events only here. Move the capture event support to a separate patch. - simplify the patch, by removing diversity introduced by the number of possible channels. All channels are now exposed instead. Report an error when trying to access a channel that doesn't exist. Changes in v2: - fix warnings (kernel test robot) - fix a typo - add collected ack from Lee --- drivers/counter/stm32-timer-cnt.c | 138 +++++++++++++++++++++++++++++- 1 file changed, 137 insertions(+), 1 deletion(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 710437d3b33f..9ec6e18f4d43 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -8,6 +8,7 @@ * */ #include +#include #include #include #include @@ -43,6 +44,9 @@ struct stm32_timer_cnt { struct stm32_timer_regs bak; bool has_encoder; unsigned int nchannels; + unsigned int nr_irqs; + spinlock_t lock; /* protects nb_ovf */ + u64 nb_ovf; }; static const enum counter_function stm32_count_functions[] = { @@ -258,6 +262,32 @@ static int stm32_count_prescaler_write(struct counter_device *counter, return regmap_write(priv->regmap, TIM_PSC, psc); } +static int stm32_count_nb_ovf_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + unsigned long irqflags; + + spin_lock_irqsave(&priv->lock, irqflags); + *val = priv->nb_ovf; + spin_unlock_irqrestore(&priv->lock, irqflags); + + return 0; +} + +static int stm32_count_nb_ovf_write(struct counter_device *counter, + struct counter_count *count, u64 val) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + unsigned long irqflags; + + spin_lock_irqsave(&priv->lock, irqflags); + priv->nb_ovf = val; + spin_unlock_irqrestore(&priv->lock, irqflags); + + return 0; +} + static struct counter_comp stm32_count_ext[] = { COUNTER_COMP_DIRECTION(stm32_count_direction_read), COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), @@ -265,6 +295,7 @@ static struct counter_comp stm32_count_ext[] = { stm32_count_ceiling_write), COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read, stm32_count_prescaler_write), + COUNTER_COMP_COUNT_U64("num_overflows", stm32_count_nb_ovf_read, stm32_count_nb_ovf_write), }; static const enum counter_synapse_action stm32_clock_synapse_actions[] = { @@ -322,12 +353,57 @@ static int stm32_action_read(struct counter_device *counter, } } +static int stm32_count_events_configure(struct counter_device *counter) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + struct counter_event_node *event_node; + u32 dier = 0; + + list_for_each_entry(event_node, &counter->events_list, l) { + switch (event_node->event) { + case COUNTER_EVENT_OVERFLOW_UNDERFLOW: + /* first clear possibly latched UIF before enabling */ + if (!regmap_test_bits(priv->regmap, TIM_DIER, TIM_DIER_UIE)) + regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF); + dier |= TIM_DIER_UIE; + break; + default: + /* should never reach this path */ + return -EINVAL; + } + } + + /* Enable / disable all events at once, from events_list, so write all DIER bits */ + regmap_write(priv->regmap, TIM_DIER, dier); + + return 0; +} + +static int stm32_count_watch_validate(struct counter_device *counter, + const struct counter_watch *watch) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + + /* Interrupts are optional */ + if (!priv->nr_irqs) + return -EOPNOTSUPP; + + switch (watch->event) { + case COUNTER_EVENT_OVERFLOW_UNDERFLOW: + return 0; + default: + return -EINVAL; + } +} + static const struct counter_ops stm32_timer_cnt_ops = { .count_read = stm32_count_read, .count_write = stm32_count_write, .function_read = stm32_count_function_read, .function_write = stm32_count_function_write, .action_read = stm32_action_read, + .events_configure = stm32_count_events_configure, + .watch_validate = stm32_count_watch_validate, }; static int stm32_count_clk_get_freq(struct counter_device *counter, @@ -417,6 +493,37 @@ static struct counter_count stm32_counts = { .num_ext = ARRAY_SIZE(stm32_count_ext) }; +static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) +{ + struct counter_device *counter = ptr; + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */ + u32 sr, dier; + + regmap_read(priv->regmap, TIM_SR, &sr); + regmap_read(priv->regmap, TIM_DIER, &dier); + /* + * Some status bits in SR don't match with the enable bits in DIER. Only take care of + * the possibly enabled bits in DIER (that matches in between SR and DIER). + */ + dier &= TIM_DIER_UIE; + sr &= dier; + + if (sr & TIM_SR_UIF) { + spin_lock(&priv->lock); + priv->nb_ovf++; + spin_unlock(&priv->lock); + counter_push_event(counter, COUNTER_EVENT_OVERFLOW_UNDERFLOW, 0); + dev_dbg(counter->parent, "COUNTER_EVENT_OVERFLOW_UNDERFLOW\n"); + /* SR flags can be cleared by writing 0, only clear relevant flag */ + clr &= ~TIM_SR_UIF; + } + + regmap_write(priv->regmap, TIM_SR, clr); + + return IRQ_HANDLED; +}; + static void stm32_timer_cnt_detect_channels(struct device *dev, struct stm32_timer_cnt *priv) { @@ -480,7 +587,7 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct stm32_timer_cnt *priv; struct counter_device *counter; - int ret; + int i, ret; if (IS_ERR_OR_NULL(ddata)) return -EINVAL; @@ -494,6 +601,7 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) priv->regmap = ddata->regmap; priv->clk = ddata->clk; priv->max_arr = ddata->max_arr; + priv->nr_irqs = ddata->nr_irqs; ret = stm32_timer_cnt_probe_encoder(dev, priv); if (ret) @@ -509,8 +617,36 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) counter->signals = stm32_signals; counter->num_signals = ARRAY_SIZE(stm32_signals); + spin_lock_init(&priv->lock); + platform_set_drvdata(pdev, priv); + /* STM32 Timers can have either 1 global, or 4 dedicated interrupts (optional) */ + if (priv->nr_irqs == 1) { + /* All events reported through the global interrupt */ + ret = devm_request_irq(&pdev->dev, ddata->irq[0], stm32_timer_cnt_isr, + 0, dev_name(dev), counter); + if (ret) { + dev_err(dev, "Failed to request irq %d (err %d)\n", + ddata->irq[0], ret); + return ret; + } + } else { + for (i = 0; i < priv->nr_irqs; i++) { + /* Only take care of update IRQ for overflow events */ + if (i != STM32_TIMERS_IRQ_UP) + continue; + + ret = devm_request_irq(&pdev->dev, ddata->irq[i], stm32_timer_cnt_isr, + 0, dev_name(dev), counter); + if (ret) { + dev_err(dev, "Failed to request irq %d (err %d)\n", + ddata->irq[i], ret); + return ret; + } + } + } + /* Reset input selector to its default input */ regmap_write(priv->regmap, TIM_TISEL, 0x0); From patchwork Tue Feb 27 17:38:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 207357 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2856510dyb; Tue, 27 Feb 2024 09:43:23 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUUXYQmxMrH9S6LiiYak/rDZU1RhQ/joFiV6ytOn1tnQuF8pLfZkdENkXNjna/5M+wA5Fbeh4sxb2ZESnujGTpibaqHjw== X-Google-Smtp-Source: AGHT+IGYeNv2Epx/eWa/OtGvazsTj+TkFa80qPxDrHHvPRsufifTTAbN4JpItUtpa6OP+Pnb0GvY X-Received: by 2002:a37:db11:0:b0:787:b85c:f83e with SMTP id e17-20020a37db11000000b00787b85cf83emr2727513qki.75.1709055803699; Tue, 27 Feb 2024 09:43:23 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709055803; cv=pass; d=google.com; s=arc-20160816; b=gAH3W9m6I8hYBIz9iWEKzcMQGrjSm8pCCM/CsGl0xKA/vdOlTDxt7u1XNqKJhNiUzo ExDWPZ8lLEt4u6crb3xsPWgqTJCFl337Ye6KSEtuM7QZNwLwOgIM3vEbm/JMjcLTy/6i RKViMk6KhAsh3WThQsD3gPcIp3iZuNeItntiy1i4PqL2DldhS3QKJVoe5z35hhw8B81T /ep7edj1iWHobtKcrRumafEVZj/Gr49t7oMW+euu0jh+bXlYnJg3OMtWXd0fXyQTkteD yVfup3/iY1bdvHOZc3eTkmYbNaf2AlSXOb4oIZHHzfun8vbvEl9iwn052LPRzRbmolPf 332Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=45JJWKc7Z05d/UNRZjlQGN1CH09iiNsdefrvNgsenrM=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=dM8oQB0wLxeMxOH+QwfYpwBe8IhPZ1wd/3rIHDTQ5sPOBjlKOTmW5tzofpmf0rRkEf cqs+ij+UN1GeOqnKy47JAh0orWqTah0A8q/HOwFx13XZ6es4TS2AuMMksvJUE/aV/rSE nxb/LacQ4C1NWiu7zD12sXAt1AGj5jGOylF5pbxF9Ukg8uMj7yDAHF3vv7eIXL+GiT1G LY3M+SKzlg9tjxT1CEQBPAzgk9wAnusnmU6owN82dC0nJtO9WmPCuLhifOAk2Te5wU9t +SuRmDw3E2y1xhi595TpXiAijLvmt56qUjY1u1vSZl9HwPLCchD4TlAsuOVfkWiWjCRO ecQQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b="7lIV/hYi"; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-83757-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83757-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Tue, 27 Feb 2024 18:41:09 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 30DA02AD157; Tue, 27 Feb 2024 18:40:44 +0100 (CET) Received: from localhost (10.252.26.109) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 27 Feb 2024 18:40:41 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v4 11/11] counter: stm32-timer-cnt: add support for capture events Date: Tue, 27 Feb 2024 18:38:03 +0100 Message-ID: <20240227173803.53906-12-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> References: <20240227173803.53906-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_05,2024-02-27_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792074898265300555 X-GMAIL-MSGID: 1792074898265300555 Add support for capture events. Captured counter value for each channel can be retrieved through CCRx register. STM32 timers can have up to 4 capture channels (on input channel 1 to channel 4), hence need to check the number of channels before reading the capture data. The capture configuration is hard-coded to capture signals on both edges (non-inverted). Interrupts are used to report events independently for each channel. Acked-by: Lee Jones Signed-off-by: Fabrice Gasnier --- Changes in v4: - move registers definition from previous patch to here. That's where the defines are actually used. So move the collected Acked-by: Lee for the mfd header here. - drop *irq from stm32_timer_cnt, as only used at probe time. - adopt some of the suggestions from William: introduce cc local variable, use regmap_test_bits(). Changes in v3: - patch split from: "counter: stm32-timer-cnt: add support for events", to focus on the capture events only here. - only get relevant interrupt line --- drivers/counter/stm32-timer-cnt.c | 134 +++++++++++++++++++++++++++++- include/linux/mfd/stm32-timers.h | 13 +++ 2 files changed, 144 insertions(+), 3 deletions(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 9ec6e18f4d43..787ebfb893b0 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -262,6 +262,40 @@ static int stm32_count_prescaler_write(struct counter_device *counter, return regmap_write(priv->regmap, TIM_PSC, psc); } +static int stm32_count_cap_read(struct counter_device *counter, + struct counter_count *count, + size_t ch, u64 *cap) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 ccrx; + + if (ch >= priv->nchannels) + return -EOPNOTSUPP; + + switch (ch) { + case 0: + regmap_read(priv->regmap, TIM_CCR1, &ccrx); + break; + case 1: + regmap_read(priv->regmap, TIM_CCR2, &ccrx); + break; + case 2: + regmap_read(priv->regmap, TIM_CCR3, &ccrx); + break; + case 3: + regmap_read(priv->regmap, TIM_CCR4, &ccrx); + break; + default: + return -EINVAL; + } + + dev_dbg(counter->parent, "CCR%zu: 0x%08x\n", ch + 1, ccrx); + + *cap = ccrx; + + return 0; +} + static int stm32_count_nb_ovf_read(struct counter_device *counter, struct counter_count *count, u64 *val) { @@ -288,6 +322,8 @@ static int stm32_count_nb_ovf_write(struct counter_device *counter, return 0; } +static DEFINE_COUNTER_ARRAY_CAPTURE(stm32_count_cap_array, 4); + static struct counter_comp stm32_count_ext[] = { COUNTER_COMP_DIRECTION(stm32_count_direction_read), COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), @@ -295,6 +331,7 @@ static struct counter_comp stm32_count_ext[] = { stm32_count_ceiling_write), COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read, stm32_count_prescaler_write), + COUNTER_COMP_ARRAY_CAPTURE(stm32_count_cap_read, NULL, stm32_count_cap_array), COUNTER_COMP_COUNT_U64("num_overflows", stm32_count_nb_ovf_read, stm32_count_nb_ovf_write), }; @@ -353,11 +390,68 @@ static int stm32_action_read(struct counter_device *counter, } } +struct stm32_count_cc_regs { + u32 ccmr_reg; + u32 ccmr_mask; + u32 ccmr_bits; + u32 ccer_bits; +}; + +static const struct stm32_count_cc_regs stm32_cc[] = { + { TIM_CCMR1, TIM_CCMR_CC1S, TIM_CCMR_CC1S_TI1, + TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC1NP }, + { TIM_CCMR1, TIM_CCMR_CC2S, TIM_CCMR_CC2S_TI2, + TIM_CCER_CC2E | TIM_CCER_CC2P | TIM_CCER_CC2NP }, + { TIM_CCMR2, TIM_CCMR_CC3S, TIM_CCMR_CC3S_TI3, + TIM_CCER_CC3E | TIM_CCER_CC3P | TIM_CCER_CC3NP }, + { TIM_CCMR2, TIM_CCMR_CC4S, TIM_CCMR_CC4S_TI4, + TIM_CCER_CC4E | TIM_CCER_CC4P | TIM_CCER_CC4NP }, +}; + +static int stm32_count_capture_configure(struct counter_device *counter, unsigned int ch, + bool enable) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + const struct stm32_count_cc_regs *cc; + u32 ccmr, ccer; + + if (ch >= ARRAY_SIZE(stm32_cc) || ch >= priv->nchannels) { + dev_err(counter->parent, "invalid ch: %d\n", ch); + return -EINVAL; + } + + cc = &stm32_cc[ch]; + + /* + * configure channel in input capture mode, map channel 1 on TI1, channel2 on TI2... + * Select both edges / non-inverted to trigger a capture. + */ + if (enable) { + /* first clear possibly latched capture flag upon enabling */ + if (!regmap_test_bits(priv->regmap, TIM_CCER, cc->ccer_bits)) + regmap_write(priv->regmap, TIM_SR, ~TIM_SR_CC_IF(ch)); + regmap_update_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask, + cc->ccmr_bits); + regmap_set_bits(priv->regmap, TIM_CCER, cc->ccer_bits); + } else { + regmap_clear_bits(priv->regmap, TIM_CCER, cc->ccer_bits); + regmap_clear_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask); + } + + regmap_read(priv->regmap, cc->ccmr_reg, &ccmr); + regmap_read(priv->regmap, TIM_CCER, &ccer); + dev_dbg(counter->parent, "%s(%s) ch%d 0x%08x 0x%08x\n", __func__, enable ? "ena" : "dis", + ch, ccmr, ccer); + + return 0; +} + static int stm32_count_events_configure(struct counter_device *counter) { struct stm32_timer_cnt *const priv = counter_priv(counter); struct counter_event_node *event_node; u32 dier = 0; + int i, ret; list_for_each_entry(event_node, &counter->events_list, l) { switch (event_node->event) { @@ -367,6 +461,12 @@ static int stm32_count_events_configure(struct counter_device *counter) regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF); dier |= TIM_DIER_UIE; break; + case COUNTER_EVENT_CAPTURE: + ret = stm32_count_capture_configure(counter, event_node->channel, true); + if (ret) + return ret; + dier |= TIM_DIER_CC_IE(event_node->channel); + break; default: /* should never reach this path */ return -EINVAL; @@ -376,6 +476,15 @@ static int stm32_count_events_configure(struct counter_device *counter) /* Enable / disable all events at once, from events_list, so write all DIER bits */ regmap_write(priv->regmap, TIM_DIER, dier); + /* check for disabled capture events */ + for (i = 0 ; i < priv->nchannels; i++) { + if (!(dier & TIM_DIER_CC_IE(i))) { + ret = stm32_count_capture_configure(counter, i, false); + if (ret) + return ret; + } + } + return 0; } @@ -389,6 +498,12 @@ static int stm32_count_watch_validate(struct counter_device *counter, return -EOPNOTSUPP; switch (watch->event) { + case COUNTER_EVENT_CAPTURE: + if (watch->channel >= priv->nchannels) { + dev_err(counter->parent, "Invalid channel %d\n", watch->channel); + return -EINVAL; + } + return 0; case COUNTER_EVENT_OVERFLOW_UNDERFLOW: return 0; default: @@ -499,6 +614,7 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) struct stm32_timer_cnt *const priv = counter_priv(counter); u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */ u32 sr, dier; + int i; regmap_read(priv->regmap, TIM_SR, &sr); regmap_read(priv->regmap, TIM_DIER, &dier); @@ -506,7 +622,7 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) * Some status bits in SR don't match with the enable bits in DIER. Only take care of * the possibly enabled bits in DIER (that matches in between SR and DIER). */ - dier &= TIM_DIER_UIE; + dier &= (TIM_DIER_UIE | TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_CC3IE | TIM_DIER_CC4IE); sr &= dier; if (sr & TIM_SR_UIF) { @@ -519,6 +635,15 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) clr &= ~TIM_SR_UIF; } + /* Check capture events */ + for (i = 0 ; i < priv->nchannels; i++) { + if (sr & TIM_SR_CC_IF(i)) { + counter_push_event(counter, COUNTER_EVENT_CAPTURE, i); + clr &= ~TIM_SR_CC_IF(i); + dev_dbg(counter->parent, "COUNTER_EVENT_CAPTURE, %d\n", i); + } + } + regmap_write(priv->regmap, TIM_SR, clr); return IRQ_HANDLED; @@ -633,8 +758,11 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) } } else { for (i = 0; i < priv->nr_irqs; i++) { - /* Only take care of update IRQ for overflow events */ - if (i != STM32_TIMERS_IRQ_UP) + /* + * Only take care of update IRQ for overflow events, and cc for + * capture events. + */ + if (i != STM32_TIMERS_IRQ_UP && i != STM32_TIMERS_IRQ_CC) continue; ret = devm_request_irq(&pdev->dev, ddata->irq[i], stm32_timer_cnt_isr, diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index ca35af30745f..9eb17481b07f 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -41,6 +41,11 @@ #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ #define TIM_DIER_UIE BIT(0) /* Update interrupt */ +#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */ +#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */ +#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */ +#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */ +#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */ #define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ #define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ #define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ @@ -49,6 +54,7 @@ #define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ #define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ +#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */ #define TIM_EGR_UG BIT(0) /* Update Generation */ #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ @@ -60,16 +66,23 @@ #define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ #define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ #define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ +#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */ +#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */ +#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */ +#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */ #define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ #define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ #define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ +#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */ #define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ #define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ +#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */ #define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ #define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ +#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */ #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) #define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */ #define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */