From patchwork Tue Feb 27 10:59:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthieu Longo X-Patchwork-Id: 207135 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2619944dyb; Tue, 27 Feb 2024 03:01:20 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUt6+vQmIwHO7rU2in0kUPmpjuqGKTjJKrzuInQGqGE1r2p2WJkCS4nW1JxXStl5hnR1JQ3k1qLhSMipCoIOnd4ELuYVg== X-Google-Smtp-Source: AGHT+IFRaVo5CUccSRhZthz1+4K64zYOE05au5U6aRnuAExzzrm8LBEvGwrEjhFZM7CbmbQKotdE X-Received: by 2002:a9d:7552:0:b0:6e4:87c9:8364 with SMTP id b18-20020a9d7552000000b006e487c98364mr10351679otl.16.1709031680382; Tue, 27 Feb 2024 03:01:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709031680; cv=pass; d=google.com; s=arc-20160816; b=wJwCZUWE+hVmt5zcYgidT+XQYOIBH+3pNnQ9gZdM4hNhN8qVui5T/kO6ro9UXZ8Z4i O9y1ljCx4tiRp7s3yGyrgy2XTV774/NFXUiUYUux8+iXUeytW9eCUjvKuUZaHeEQ/1zI Goax7iHXJQqd11UIPLfcbJsZtney919NmrdDGjPT30EuY0CDr+8mB7l4EViCt5drmwSw 5SLEqZ+cAVUNa3nF55jEr9CFtGgwD+lxqZ8b1hWw02rKChjzZ0CI7UWc1VZBHtEFvDTJ uV1W1bxvBQJMR+mmF+lSF80dCdbwmUrUYnW+gzLdwLPOaiPTin09M08LL9phV5QRJ0c/ CLIg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=l7reayvE1suKlLS13vDrh+s17pbAy28XnDlndhjaZ4A=; fh=bcbSBk6kL0yCjqxjmEWwFzJxBMxjhnM2jUxTrAFje1Y=; b=IHy0fIUUO/TNSvYrfLj/jtzYklxHXGIWIWwdmugzdZV1MCapqRrh/iMbAUDvAScjuU ocUH4IM5RBzRWXnLi0v/XL+qKCvTmKcfTWim7YBHwKD8tyCz0j69ZYa6Amjk/IZ8WJuv X2gb9ojGio8wIQNAuXZNDiR0dAhz4WiRH4TC90HuRTB4U89LwsRHYlrxiFxUJ3cSv1g6 YZbDts41pLO9nktXCwiC3yUXeghAxpnoww/PfDJ86CknVu1ADEIzjR6TJOXQA3uDMbnb 8xbKwyLa93ZTDfywT3wzV/CWN0vprXcEiKsScqZUN71SlRg4tbwUrXHtJPAolAd8WuKv PKmg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id u16-20020a05620a023000b007872a6a51b4si7267955qkm.132.2024.02.27.03.01.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 03:01:20 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CBA813858414 for ; Tue, 27 Feb 2024 11:01:19 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat-cam5.arm.com [217.140.106.53]) by sourceware.org (Postfix) with ESMTPS id 8DD283858420 for ; Tue, 27 Feb 2024 11:00:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8DD283858420 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8DD283858420 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.106.53 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709031602; cv=none; b=udldMyGvfrp8+F/M1vAw+V4A6DPTt8BzV1ZXPmvxiov17NzCvyXLrwhEacPAdps3sxkdpIpLikzWGfLnBHrMlQJn2zCfOus1et+YCM3+rl7/J6vFkLgZGC0fPiAmDCDDsusqTs8Y06ShMnFvg0Gp/gt5VVjgCDKOOHdblTRypjI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709031602; c=relaxed/simple; bh=yc1L6w4PqONnM1sJp4vdo5KNVq5eaG/ZL1Z78KnTHiM=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=VdDIlkNndB5RdmHMepEg4yeYDP+jkt/qPEeBKuUqiFOnS0FN9+75EFvcGAFWwdPdnzOeCDDHsHM2E8vXgX3k854CjgupIZOwTGq0IpbH14TLMektF6k6zaqa14S+wvaWMlY76/gYh49YimYPQaRZ12MmXr6VjgTdEqG4zCTn+B4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from e129756.cambridge.arm.com (e129756.arm.com [10.2.78.55]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id 41RAxnZP030743; Tue, 27 Feb 2024 10:59:58 GMT From: Matthieu Longo To: binutils@sourceware.org Cc: Richard Earnshaw , Nick Clifton , Matthieu Longo Subject: [PATCH v1 1/4] aarch64: testsuite: replace instruction addresses by regex Date: Tue, 27 Feb 2024 10:59:14 +0000 Message-Id: <20240227105917.295899-2-matthieu.longo@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227105917.295899-1-matthieu.longo@arm.com> References: <20240227105917.295899-1-matthieu.longo@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KHOP_HELO_FCRDNS, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792049603227664360 X-GMAIL-MSGID: 1792049603227664360 This patch removes the instruction addresses from the objdump's expected output (.d files). The intended benefit from this clean-up is to allow to swap lines around more easilly, and removes the noise of patches that add, remove or reorder instructions. --- gas/testsuite/gas/aarch64/sysreg/sysreg.d | 56 +++++++++++------------ 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sysreg.d index d10175837f2..90b5be3cabf 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.d @@ -5,31 +5,31 @@ Disassembly of section \.text: 0+ <.*>: - 0: d51b9c67 msr pmovsclr_el0, x7 - 4: d53b9c60 mrs x0, pmovsclr_el0 - 8: d51b9e67 msr pmovsset_el0, x7 - c: d53b9e60 mrs x0, pmovsset_el0 - 10: d5380140 mrs x0, id_dfr0_el1 - 14: d5380100 mrs x0, id_pfr0_el1 - 18: d5380120 mrs x0, id_pfr1_el1 - 1c: d5380160 mrs x0, id_afr0_el1 - 20: d5380180 mrs x0, id_mmfr0_el1 - 24: d53801a0 mrs x0, id_mmfr1_el1 - 28: d53801c0 mrs x0, id_mmfr2_el1 - 2c: d53801e0 mrs x0, id_mmfr3_el1 - 30: d53802c0 mrs x0, id_mmfr4_el1 - 34: d5380200 mrs x0, id_isar0_el1 - 38: d5380220 mrs x0, id_isar1_el1 - 3c: d5380240 mrs x0, id_isar2_el1 - 40: d5380260 mrs x0, id_isar3_el1 - 44: d5380280 mrs x0, id_isar4_el1 - 48: d53802a0 mrs x0, id_isar5_el1 - 4c: d538cf00 mrs x0, s3_0_c12_c15_0 - 50: d5384b00 mrs x0, s3_0_c4_c11_0 - 54: d5184b00 msr s3_0_c4_c11_0, x0 - 58: d5310300 mrs x0, trcstatr - 5c: d5110300 msr trcstatr, x0 - 60: d5380640 mrs x0, id_aa64isar2_el1 - 64: d538065e mrs x30, id_aa64isar2_el1 - 68: d5380660 mrs x0, id_aa64isar3_el1 - 6c: d538067e mrs x30, id_aa64isar3_el1 +.*: d51b9c67 msr pmovsclr_el0, x7 +.*: d53b9c60 mrs x0, pmovsclr_el0 +.*: d51b9e67 msr pmovsset_el0, x7 +.*: d53b9e60 mrs x0, pmovsset_el0 +.*: d5380140 mrs x0, id_dfr0_el1 +.*: d5380100 mrs x0, id_pfr0_el1 +.*: d5380120 mrs x0, id_pfr1_el1 +.*: d5380160 mrs x0, id_afr0_el1 +.*: d5380180 mrs x0, id_mmfr0_el1 +.*: d53801a0 mrs x0, id_mmfr1_el1 +.*: d53801c0 mrs x0, id_mmfr2_el1 +.*: d53801e0 mrs x0, id_mmfr3_el1 +.*: d53802c0 mrs x0, id_mmfr4_el1 +.*: d5380200 mrs x0, id_isar0_el1 +.*: d5380220 mrs x0, id_isar1_el1 +.*: d5380240 mrs x0, id_isar2_el1 +.*: d5380260 mrs x0, id_isar3_el1 +.*: d5380280 mrs x0, id_isar4_el1 +.*: d53802a0 mrs x0, id_isar5_el1 +.*: d538cf00 mrs x0, s3_0_c12_c15_0 +.*: d5384b00 mrs x0, s3_0_c4_c11_0 +.*: d5184b00 msr s3_0_c4_c11_0, x0 +.*: d5310300 mrs x0, trcstatr +.*: d5110300 msr trcstatr, x0 +.*: d5380640 mrs x0, id_aa64isar2_el1 +.*: d538065e mrs x30, id_aa64isar2_el1 +.*: d5380660 mrs x0, id_aa64isar3_el1 +.*: d538067e mrs x30, id_aa64isar3_el1 From patchwork Tue Feb 27 10:59:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthieu Longo X-Patchwork-Id: 207133 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2619207dyb; Tue, 27 Feb 2024 03:00:17 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVeDeI09qdPiMHHbzG7/LgjLrlm4kIC2kivYTURRx64HFHOekNI3MJdPsf+4F+UU2uAjasMhlNqDnfjS4U/3tE62CGlAg== X-Google-Smtp-Source: AGHT+IFYVFCQkmKaK6USYVA0zUtu0CeyxaTNZiMz6OeE37EZLR6KjSVjbot94aulbxF0qHrydNbP X-Received: by 2002:a05:6102:370f:b0:470:575a:f4bd with SMTP id s15-20020a056102370f00b00470575af4bdmr8173171vst.28.1709031617420; Tue, 27 Feb 2024 03:00:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709031617; cv=pass; d=google.com; s=arc-20160816; b=ajmAUAVyKQDLfDmK21H0wLtNNAUBMoNX3jxZwBiFaMSyG3gAEzU8lMCxu2VNktq+XS X1Qs324uk348V30gV3YjKaz0zGqyKWCbUiYtjGjf7mk6QeLn2dVRjJpexl7GxkZOT6h9 xisqxYLiPe7uqXhlVSYABqFVt9eamKFnNC52HWpR6gFmJjQjgWpGdd/uQs+V/6BvfOA2 E+zcqVU8ZmLNcDKN0K+NeP8TYCe4IcrJ9l5cSkR4r/fOcwXuyHVXrMrjq2ygUxFsPm4Z nFbQBFntHfautjOQ3aK/2th526+OyEZslIu87cstpKKKdIgd+Tq2Q9yhsS+X6rmdEQX6 vM/Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=Z2geVT30ziknoI842bf/i3UhHyVPEy/OHKKsB3DRg9g=; fh=bcbSBk6kL0yCjqxjmEWwFzJxBMxjhnM2jUxTrAFje1Y=; b=ZBfHXb0lUwS6ViVK/dMTwiXzyBrXhLJsg3JZeY7wuS40EsLpV7gWn5BHTC5OUdPq4r WuJGIFKuvFPwD6HAlEvDhCYGW/gZD4qO/KzOI1kta+oItBkPKwdAG5zNvPqRdGfmdnjr wDIQs8CjBcBlle/OjO/ANNZICPd5EE1Y5vQb8CUwpnVPg3stFhw/WwxmRA9WfegANUyp edvh3GRZq0ThXjXBO5Fg5bX4Oru+frjVdsOuXkoPCZtqTQtbOSmDmpkb//yPoGhsqX0O b4ss1A2fYkwz6We9yYa6Mm+yLBBeEs2Calpo/KEWmEgMVHSm0ra2cq0KUlSmrM+JacOG AYBw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d20-20020ac847d4000000b0042e66cbc8f7si6787412qtr.319.2024.02.27.03.00.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 03:00:17 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7BF9B385829B for ; Tue, 27 Feb 2024 11:00:16 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat-cam5.arm.com [217.140.106.53]) by sourceware.org (Postfix) with ESMTPS id DD48F385843B for ; Tue, 27 Feb 2024 11:00:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DD48F385843B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DD48F385843B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.106.53 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709031606; cv=none; b=hIBGIa2fh+n3kATaBUOQL/qIebQ2kx76JOZSEIzn1/yfYL0iBDUXtXhbiRnmyKhQtAj7CBww83zQAVRD2EwORTg5rYfQBYtGamG/bs7wvavzjY08WfFP6hVOUQ4AV6iWK9GRyWayVF0gcNUlBczkPBoejX7EzYTC0sfOjf2UaRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709031606; c=relaxed/simple; bh=jLu1kdvkD/5bpyuIaeBJHCMUS/BgaU+LWYT7Xt3T7Hw=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=gPUWMDcPgEGZfWOmJ3bL9B7J63WFKJnYi1wZHtASKvHzqCfdxspKBzVUAXHzbTTXRyVl+PUMq6MMYEYIkoZ9Sq6ThRONiLgcvnDqtKyPBElEYiW1sU63lJDn8Hpbn4FxOA7i/uWNk9CeEBRWNeus3DPfo/Mo7U0ogmO4bHxuJ6k= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from e129756.cambridge.arm.com (e129756.arm.com [10.2.78.55]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id 41RAxnZQ030743; Tue, 27 Feb 2024 10:59:58 GMT From: Matthieu Longo To: binutils@sourceware.org Cc: Richard Earnshaw , Nick Clifton , Matthieu Longo Subject: [PATCH v1 2/4] aarch64: testsuite: use same regs for read and write tests Date: Tue, 27 Feb 2024 10:59:15 +0000 Message-Id: <20240227105917.295899-3-matthieu.longo@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227105917.295899-1-matthieu.longo@arm.com> References: <20240227105917.295899-1-matthieu.longo@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KHOP_HELO_FCRDNS, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792049537038304454 X-GMAIL-MSGID: 1792049537038304454 This patch aims at making easier to replacement of read and write instructions to system registers by a macro that will use the same registers for read and write. --- gas/testsuite/gas/aarch64/sysreg/sysreg-2.d | 102 ++-- gas/testsuite/gas/aarch64/sysreg/sysreg-2.s | 38 +- gas/testsuite/gas/aarch64/sysreg/sysreg-3.d | 40 +- gas/testsuite/gas/aarch64/sysreg/sysreg-3.s | 18 +- gas/testsuite/gas/aarch64/sysreg/sysreg-8.d | 528 +++++++++---------- gas/testsuite/gas/aarch64/sysreg/sysreg-8.s | 6 +- gas/testsuite/gas/aarch64/sysreg/sysreg128.d | 20 +- gas/testsuite/gas/aarch64/sysreg/sysreg128.s | 2 +- 8 files changed, 377 insertions(+), 377 deletions(-) diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d index ac0a8621bfa..0a3a0c7d6b4 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d @@ -7,54 +7,54 @@ Disassembly of section .text: 0+ <.*>: -.*: d5380725 mrs x5, id_aa64mmfr1_el1 -.*: d5380747 mrs x7, id_aa64mmfr2_el1 -.*: d5380769 mrs x9, id_aa64mmfr3_el1 -.*: d538078b mrs x11, id_aa64mmfr4_el1 - [0-9a-f]+: d5385305 mrs x5, erridr_el1 - [0-9a-f]+: d5185327 msr errselr_el1, x7 - [0-9a-f]+: d5385327 mrs x7, errselr_el1 - [0-9a-f]+: d5385405 mrs x5, erxfr_el1 - [0-9a-f]+: d5185425 msr erxctlr_el1, x5 - [0-9a-f]+: d5385425 mrs x5, erxctlr_el1 - [0-9a-f]+: d5185445 msr erxstatus_el1, x5 - [0-9a-f]+: d5385445 mrs x5, erxstatus_el1 - [0-9a-f]+: d5185465 msr erxaddr_el1, x5 - [0-9a-f]+: d5385465 mrs x5, erxaddr_el1 - [0-9a-f]+: d5185505 msr erxmisc0_el1, x5 - [0-9a-f]+: d5385505 mrs x5, erxmisc0_el1 - [0-9a-f]+: d5185525 msr erxmisc1_el1, x5 - [0-9a-f]+: d5385525 mrs x5, erxmisc1_el1 - [0-9a-f]+: d53c5265 mrs x5, vsesr_el2 - [0-9a-f]+: d518c125 msr disr_el1, x5 - [0-9a-f]+: d538c125 mrs x5, disr_el1 - [0-9a-f]+: d53cc125 mrs x5, vdisr_el2 - [0-9a-f]+: d50b7a20 dc cvac, x0 - [0-9a-f]+: d50b7b21 dc cvau, x1 - [0-9a-f]+: d50b7c22 dc cvap, x2 - [0-9a-f]+: d5087900 at s1e1rp, x0 - [0-9a-f]+: d5087921 at s1e1wp, x1 - [0-9a-f]+: d5189a07 msr pmblimitr_el1, x7 - [0-9a-f]+: d5389a07 mrs x7, pmblimitr_el1 - [0-9a-f]+: d5189a27 msr pmbptr_el1, x7 - [0-9a-f]+: d5389a27 mrs x7, pmbptr_el1 - [0-9a-f]+: d5189a67 msr pmbsr_el1, x7 - [0-9a-f]+: d5389a67 mrs x7, pmbsr_el1 - [0-9a-f]+: d5189907 msr pmscr_el1, x7 - [0-9a-f]+: d5389907 mrs x7, pmscr_el1 - [0-9a-f]+: d5189947 msr pmsicr_el1, x7 - [0-9a-f]+: d5389947 mrs x7, pmsicr_el1 - [0-9a-f]+: d5189967 msr pmsirr_el1, x7 - [0-9a-f]+: d5389967 mrs x7, pmsirr_el1 - [0-9a-f]+: d5189987 msr pmsfcr_el1, x7 - [0-9a-f]+: d5389987 mrs x7, pmsfcr_el1 - [0-9a-f]+: d51899a7 msr pmsevfr_el1, x7 - [0-9a-f]+: d53899a7 mrs x7, pmsevfr_el1 - [0-9a-f]+: d51899c7 msr pmslatfr_el1, x7 - [0-9a-f]+: d53899c7 mrs x7, pmslatfr_el1 - [0-9a-f]+: d51c9907 msr pmscr_el2, x7 - [0-9a-f]+: d53c9907 mrs x7, pmscr_el2 - [0-9a-f]+: d51d9907 msr pmscr_el12, x7 - [0-9a-f]+: d53d9907 mrs x7, pmscr_el12 - [0-9a-f]+: d5389ae7 mrs x7, pmbidr_el1 - [0-9a-f]+: d53899e7 mrs x7, pmsidr_el1 +.*: d5380720 mrs x0, id_aa64mmfr1_el1 +.*: d5380740 mrs x0, id_aa64mmfr2_el1 +.*: d5380760 mrs x0, id_aa64mmfr3_el1 +.*: d5380780 mrs x0, id_aa64mmfr4_el1 +.*: d5385300 mrs x0, erridr_el1 +.*: d5185320 msr errselr_el1, x0 +.*: d5385320 mrs x0, errselr_el1 +.*: d5385400 mrs x0, erxfr_el1 +.*: d5185420 msr erxctlr_el1, x0 +.*: d5385420 mrs x0, erxctlr_el1 +.*: d5185440 msr erxstatus_el1, x0 +.*: d5385440 mrs x0, erxstatus_el1 +.*: d5185460 msr erxaddr_el1, x0 +.*: d5385460 mrs x0, erxaddr_el1 +.*: d5185500 msr erxmisc0_el1, x0 +.*: d5385500 mrs x0, erxmisc0_el1 +.*: d5185520 msr erxmisc1_el1, x0 +.*: d5385520 mrs x0, erxmisc1_el1 +.*: d53c5260 mrs x0, vsesr_el2 +.*: d518c120 msr disr_el1, x0 +.*: d538c120 mrs x0, disr_el1 +.*: d53cc120 mrs x0, vdisr_el2 +.*: d50b7a20 dc cvac, x0 +.*: d50b7b21 dc cvau, x1 +.*: d50b7c22 dc cvap, x2 +.*: d5087900 at s1e1rp, x0 +.*: d5087921 at s1e1wp, x1 +.*: d5189a00 msr pmblimitr_el1, x0 +.*: d5389a00 mrs x0, pmblimitr_el1 +.*: d5189a20 msr pmbptr_el1, x0 +.*: d5389a20 mrs x0, pmbptr_el1 +.*: d5189a60 msr pmbsr_el1, x0 +.*: d5389a60 mrs x0, pmbsr_el1 +.*: d5189900 msr pmscr_el1, x0 +.*: d5389900 mrs x0, pmscr_el1 +.*: d5189940 msr pmsicr_el1, x0 +.*: d5389940 mrs x0, pmsicr_el1 +.*: d5189960 msr pmsirr_el1, x0 +.*: d5389960 mrs x0, pmsirr_el1 +.*: d5189980 msr pmsfcr_el1, x0 +.*: d5389980 mrs x0, pmsfcr_el1 +.*: d51899a0 msr pmsevfr_el1, x0 +.*: d53899a0 mrs x0, pmsevfr_el1 +.*: d51899c0 msr pmslatfr_el1, x0 +.*: d53899c0 mrs x0, pmslatfr_el1 +.*: d51c9900 msr pmscr_el2, x0 +.*: d53c9900 mrs x0, pmscr_el2 +.*: d51d9900 msr pmscr_el12, x0 +.*: d53d9900 mrs x0, pmscr_el12 +.*: d5389ae0 mrs x0, pmbidr_el1 +.*: d53899e0 mrs x0, pmsidr_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-2.s index ae2bb145e72..315e6411849 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-2.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-2.s @@ -11,27 +11,27 @@ .text - rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x5 r=1 w=0 - rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x7 r=1 w=0 - rw_sys_reg sys_reg=id_aa64mmfr3_el1 xreg=x9 r=1 w=0 - rw_sys_reg sys_reg=id_aa64mmfr4_el1 xreg=x11 r=1 w=0 + rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x0 r=1 w=0 + rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x0 r=1 w=0 + rw_sys_reg sys_reg=id_aa64mmfr3_el1 xreg=x0 r=1 w=0 + rw_sys_reg sys_reg=id_aa64mmfr4_el1 xreg=x0 r=1 w=0 /* RAS extension. */ - rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0 - rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1 + rw_sys_reg sys_reg=erridr_el1 xreg=x0 r=1 w=0 + rw_sys_reg sys_reg=errselr_el1 xreg=x0 r=1 w=1 - rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0 - rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1 - rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1 - rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxfr_el1 xreg=x0 r=1 w=0 + rw_sys_reg sys_reg=erxctlr_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=erxstatus_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=erxaddr_el1 xreg=x0 r=1 w=1 - rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1 - rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxmisc0_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=erxmisc1_el1 xreg=x0 r=1 w=1 - rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0 - rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1 - rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=vsesr_el2 xreg=x0 r=1 w=0 + rw_sys_reg sys_reg=disr_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=vdisr_el2 xreg=x0 r=1 w=0 /* DC CVAP. */ @@ -47,17 +47,17 @@ /* Statistical profiling. */ .irp reg, pmblimitr_el1, pmbptr_el1, pmbsr_el1 - rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1 + rw_sys_reg sys_reg=\reg xreg=x0 r=1 w=1 .endr .irp reg, pmscr_el1, pmsicr_el1, pmsirr_el1, pmsfcr_el1 - rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1 + rw_sys_reg sys_reg=\reg xreg=x0 r=1 w=1 .endr .irp reg, pmsevfr_el1, pmslatfr_el1, pmscr_el2, pmscr_el12 - rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1 + rw_sys_reg sys_reg=\reg xreg=x0 r=1 w=1 .endr .irp reg, pmbidr_el1, pmsidr_el1 - rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=0 + rw_sys_reg sys_reg=\reg xreg=x0 r=1 w=0 .endr diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d index e1c1ead73e7..5ed05d6916c 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d @@ -6,23 +6,23 @@ Disassembly of section \.text: 0+ <.*>: - 0: d5182100 msr apiakeylo_el1, x0 - 4: d5382100 mrs x0, apiakeylo_el1 - 8: d5182121 msr apiakeyhi_el1, x1 - c: d5382121 mrs x1, apiakeyhi_el1 - 10: d5182142 msr apibkeylo_el1, x2 - 14: d5382142 mrs x2, apibkeylo_el1 - 18: d5182163 msr apibkeyhi_el1, x3 - 1c: d5382163 mrs x3, apibkeyhi_el1 - 20: d5182204 msr apdakeylo_el1, x4 - 24: d5382204 mrs x4, apdakeylo_el1 - 28: d5182225 msr apdakeyhi_el1, x5 - 2c: d5382225 mrs x5, apdakeyhi_el1 - 30: d5182246 msr apdbkeylo_el1, x6 - 34: d5382246 mrs x6, apdbkeylo_el1 - 38: d5182267 msr apdbkeyhi_el1, x7 - 3c: d5382267 mrs x7, apdbkeyhi_el1 - 40: d5182308 msr apgakeylo_el1, x8 - 44: d5382308 mrs x8, apgakeylo_el1 - 48: d5182329 msr apgakeyhi_el1, x9 - 4c: d5382329 mrs x9, apgakeyhi_el1 +.*: d5182100 msr apiakeylo_el1, x0 +.*: d5382100 mrs x0, apiakeylo_el1 +.*: d5182120 msr apiakeyhi_el1, x0 +.*: d5382120 mrs x0, apiakeyhi_el1 +.*: d5182140 msr apibkeylo_el1, x0 +.*: d5382140 mrs x0, apibkeylo_el1 +.*: d5182160 msr apibkeyhi_el1, x0 +.*: d5382160 mrs x0, apibkeyhi_el1 +.*: d5182200 msr apdakeylo_el1, x0 +.*: d5382200 mrs x0, apdakeylo_el1 +.*: d5182220 msr apdakeyhi_el1, x0 +.*: d5382220 mrs x0, apdakeyhi_el1 +.*: d5182240 msr apdbkeylo_el1, x0 +.*: d5382240 mrs x0, apdbkeylo_el1 +.*: d5182260 msr apdbkeyhi_el1, x0 +.*: d5382260 mrs x0, apdbkeyhi_el1 +.*: d5182300 msr apgakeylo_el1, x0 +.*: d5382300 mrs x0, apgakeylo_el1 +.*: d5182320 msr apgakeyhi_el1, x0 +.*: d5382320 mrs x0, apgakeyhi_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-3.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-3.s index e2ffc81c2b2..b45f89fcf27 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-3.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-3.s @@ -8,14 +8,14 @@ .text test sys_reg=apiakeylo_el1 xreg=x0 - test sys_reg=apiakeyhi_el1 xreg=x1 - test sys_reg=apibkeylo_el1 xreg=x2 - test sys_reg=apibkeyhi_el1 xreg=x3 + test sys_reg=apiakeyhi_el1 xreg=x0 + test sys_reg=apibkeylo_el1 xreg=x0 + test sys_reg=apibkeyhi_el1 xreg=x0 - test sys_reg=apdakeylo_el1 xreg=x4 - test sys_reg=apdakeyhi_el1 xreg=x5 - test sys_reg=apdbkeylo_el1 xreg=x6 - test sys_reg=apdbkeyhi_el1 xreg=x7 + test sys_reg=apdakeylo_el1 xreg=x0 + test sys_reg=apdakeyhi_el1 xreg=x0 + test sys_reg=apdbkeylo_el1 xreg=x0 + test sys_reg=apdbkeyhi_el1 xreg=x0 - test sys_reg=apgakeylo_el1 xreg=x8 - test sys_reg=apgakeyhi_el1 xreg=x9 + test sys_reg=apgakeylo_el1 xreg=x0 + test sys_reg=apgakeyhi_el1 xreg=x0 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d index 09b67245781..3f048849836 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d @@ -9,287 +9,287 @@ Disassembly of section \.text: [^:]*: d53803a0 mrs x0, id_dfr1_el1 [^:]*: d53803c0 mrs x0, id_mmfr5_el1 [^:]*: d53802e0 mrs x0, id_isar6_el1 -[^:]*: d5384602 mrs x2, icc_pmr_el1 -[^:]*: d5184603 msr icc_pmr_el1, x3 +[^:]*: d5384600 mrs x0, icc_pmr_el1 +[^:]*: d5184600 msr icc_pmr_el1, x0 [^:]*: d538c800 mrs x0, icc_iar0_el1 -[^:]*: d518c821 msr icc_eoir0_el1, x1 +[^:]*: d518c820 msr icc_eoir0_el1, x0 [^:]*: d538c840 mrs x0, icc_hppir0_el1 -[^:]*: d538c862 mrs x2, icc_bpr0_el1 -[^:]*: d518c863 msr icc_bpr0_el1, x3 -[^:]*: d538c882 mrs x2, icc_ap0r0_el1 -[^:]*: d518c883 msr icc_ap0r0_el1, x3 -[^:]*: d538c8a2 mrs x2, icc_ap0r1_el1 -[^:]*: d518c8a3 msr icc_ap0r1_el1, x3 -[^:]*: d538c8c2 mrs x2, icc_ap0r2_el1 -[^:]*: d518c8c3 msr icc_ap0r2_el1, x3 -[^:]*: d538c8e2 mrs x2, icc_ap0r3_el1 -[^:]*: d518c8e3 msr icc_ap0r3_el1, x3 -[^:]*: d538c902 mrs x2, icc_ap1r0_el1 -[^:]*: d518c903 msr icc_ap1r0_el1, x3 -[^:]*: d538c922 mrs x2, icc_ap1r1_el1 -[^:]*: d518c923 msr icc_ap1r1_el1, x3 -[^:]*: d538c942 mrs x2, icc_ap1r2_el1 -[^:]*: d518c943 msr icc_ap1r2_el1, x3 -[^:]*: d538c962 mrs x2, icc_ap1r3_el1 -[^:]*: d518c963 msr icc_ap1r3_el1, x3 -[^:]*: d518cb21 msr icc_dir_el1, x1 +[^:]*: d538c860 mrs x0, icc_bpr0_el1 +[^:]*: d518c860 msr icc_bpr0_el1, x0 +[^:]*: d538c880 mrs x0, icc_ap0r0_el1 +[^:]*: d518c880 msr icc_ap0r0_el1, x0 +[^:]*: d538c8a0 mrs x0, icc_ap0r1_el1 +[^:]*: d518c8a0 msr icc_ap0r1_el1, x0 +[^:]*: d538c8c0 mrs x0, icc_ap0r2_el1 +[^:]*: d518c8c0 msr icc_ap0r2_el1, x0 +[^:]*: d538c8e0 mrs x0, icc_ap0r3_el1 +[^:]*: d518c8e0 msr icc_ap0r3_el1, x0 +[^:]*: d538c900 mrs x0, icc_ap1r0_el1 +[^:]*: d518c900 msr icc_ap1r0_el1, x0 +[^:]*: d538c920 mrs x0, icc_ap1r1_el1 +[^:]*: d518c920 msr icc_ap1r1_el1, x0 +[^:]*: d538c940 mrs x0, icc_ap1r2_el1 +[^:]*: d518c940 msr icc_ap1r2_el1, x0 +[^:]*: d538c960 mrs x0, icc_ap1r3_el1 +[^:]*: d518c960 msr icc_ap1r3_el1, x0 +[^:]*: d518cb20 msr icc_dir_el1, x0 [^:]*: d538cb60 mrs x0, icc_rpr_el1 -[^:]*: d518cba1 msr icc_sgi1r_el1, x1 -[^:]*: d518cbc1 msr icc_asgi1r_el1, x1 -[^:]*: d518cbe1 msr icc_sgi0r_el1, x1 +[^:]*: d518cba0 msr icc_sgi1r_el1, x0 +[^:]*: d518cbc0 msr icc_asgi1r_el1, x0 +[^:]*: d518cbe0 msr icc_sgi0r_el1, x0 [^:]*: d538cc00 mrs x0, icc_iar1_el1 -[^:]*: d518cc21 msr icc_eoir1_el1, x1 +[^:]*: d518cc20 msr icc_eoir1_el1, x0 [^:]*: d538cc40 mrs x0, icc_hppir1_el1 -[^:]*: d538cc62 mrs x2, icc_bpr1_el1 -[^:]*: d518cc63 msr icc_bpr1_el1, x3 -[^:]*: d538cc82 mrs x2, icc_ctlr_el1 -[^:]*: d518cc83 msr icc_ctlr_el1, x3 -[^:]*: d538ccc2 mrs x2, icc_igrpen0_el1 -[^:]*: d518ccc3 msr icc_igrpen0_el1, x3 -[^:]*: d538cce2 mrs x2, icc_igrpen1_el1 -[^:]*: d518cce3 msr icc_igrpen1_el1, x3 -[^:]*: d53cc802 mrs x2, ich_ap0r0_el2 -[^:]*: d51cc803 msr ich_ap0r0_el2, x3 -[^:]*: d53cc822 mrs x2, ich_ap0r1_el2 -[^:]*: d51cc823 msr ich_ap0r1_el2, x3 -[^:]*: d53cc842 mrs x2, ich_ap0r2_el2 -[^:]*: d51cc843 msr ich_ap0r2_el2, x3 -[^:]*: d53cc862 mrs x2, ich_ap0r3_el2 -[^:]*: d51cc863 msr ich_ap0r3_el2, x3 -[^:]*: d53cc902 mrs x2, ich_ap1r0_el2 -[^:]*: d51cc903 msr ich_ap1r0_el2, x3 -[^:]*: d53cc922 mrs x2, ich_ap1r1_el2 -[^:]*: d51cc923 msr ich_ap1r1_el2, x3 -[^:]*: d53cc942 mrs x2, ich_ap1r2_el2 -[^:]*: d51cc943 msr ich_ap1r2_el2, x3 -[^:]*: d53cc962 mrs x2, ich_ap1r3_el2 -[^:]*: d51cc963 msr ich_ap1r3_el2, x3 -[^:]*: d53ccb02 mrs x2, ich_hcr_el2 -[^:]*: d51ccb03 msr ich_hcr_el2, x3 +[^:]*: d538cc60 mrs x0, icc_bpr1_el1 +[^:]*: d518cc60 msr icc_bpr1_el1, x0 +[^:]*: d538cc80 mrs x0, icc_ctlr_el1 +[^:]*: d518cc80 msr icc_ctlr_el1, x0 +[^:]*: d538ccc0 mrs x0, icc_igrpen0_el1 +[^:]*: d518ccc0 msr icc_igrpen0_el1, x0 +[^:]*: d538cce0 mrs x0, icc_igrpen1_el1 +[^:]*: d518cce0 msr icc_igrpen1_el1, x0 +[^:]*: d53cc800 mrs x0, ich_ap0r0_el2 +[^:]*: d51cc800 msr ich_ap0r0_el2, x0 +[^:]*: d53cc820 mrs x0, ich_ap0r1_el2 +[^:]*: d51cc820 msr ich_ap0r1_el2, x0 +[^:]*: d53cc840 mrs x0, ich_ap0r2_el2 +[^:]*: d51cc840 msr ich_ap0r2_el2, x0 +[^:]*: d53cc860 mrs x0, ich_ap0r3_el2 +[^:]*: d51cc860 msr ich_ap0r3_el2, x0 +[^:]*: d53cc900 mrs x0, ich_ap1r0_el2 +[^:]*: d51cc900 msr ich_ap1r0_el2, x0 +[^:]*: d53cc920 mrs x0, ich_ap1r1_el2 +[^:]*: d51cc920 msr ich_ap1r1_el2, x0 +[^:]*: d53cc940 mrs x0, ich_ap1r2_el2 +[^:]*: d51cc940 msr ich_ap1r2_el2, x0 +[^:]*: d53cc960 mrs x0, ich_ap1r3_el2 +[^:]*: d51cc960 msr ich_ap1r3_el2, x0 +[^:]*: d53ccb00 mrs x0, ich_hcr_el2 +[^:]*: d51ccb00 msr ich_hcr_el2, x0 [^:]*: d53ccb40 mrs x0, ich_misr_el2 [^:]*: d53ccb60 mrs x0, ich_eisr_el2 [^:]*: d53ccba0 mrs x0, ich_elrsr_el2 -[^:]*: d53ccbe2 mrs x2, ich_vmcr_el2 -[^:]*: d51ccbe3 msr ich_vmcr_el2, x3 -[^:]*: d53ccc02 mrs x2, ich_lr0_el2 -[^:]*: d51ccc03 msr ich_lr0_el2, x3 -[^:]*: d53ccc22 mrs x2, ich_lr1_el2 -[^:]*: d51ccc23 msr ich_lr1_el2, x3 -[^:]*: d53ccc42 mrs x2, ich_lr2_el2 -[^:]*: d51ccc43 msr ich_lr2_el2, x3 -[^:]*: d53ccc62 mrs x2, ich_lr3_el2 -[^:]*: d51ccc63 msr ich_lr3_el2, x3 -[^:]*: d53ccc82 mrs x2, ich_lr4_el2 -[^:]*: d51ccc83 msr ich_lr4_el2, x3 -[^:]*: d53ccca2 mrs x2, ich_lr5_el2 -[^:]*: d51ccca3 msr ich_lr5_el2, x3 -[^:]*: d53cccc2 mrs x2, ich_lr6_el2 -[^:]*: d51cccc3 msr ich_lr6_el2, x3 -[^:]*: d53ccce2 mrs x2, ich_lr7_el2 -[^:]*: d51ccce3 msr ich_lr7_el2, x3 -[^:]*: d53ccd02 mrs x2, ich_lr8_el2 -[^:]*: d51ccd03 msr ich_lr8_el2, x3 -[^:]*: d53ccd22 mrs x2, ich_lr9_el2 -[^:]*: d51ccd23 msr ich_lr9_el2, x3 -[^:]*: d53ccd42 mrs x2, ich_lr10_el2 -[^:]*: d51ccd43 msr ich_lr10_el2, x3 -[^:]*: d53ccd62 mrs x2, ich_lr11_el2 -[^:]*: d51ccd63 msr ich_lr11_el2, x3 -[^:]*: d53ccd82 mrs x2, ich_lr12_el2 -[^:]*: d51ccd83 msr ich_lr12_el2, x3 -[^:]*: d53ccda2 mrs x2, ich_lr13_el2 -[^:]*: d51ccda3 msr ich_lr13_el2, x3 -[^:]*: d53ccdc2 mrs x2, ich_lr14_el2 -[^:]*: d51ccdc3 msr ich_lr14_el2, x3 -[^:]*: d53ccde2 mrs x2, ich_lr15_el2 -[^:]*: d51ccde3 msr ich_lr15_el2, x3 -[^:]*: d53ecce2 mrs x2, icc_igrpen1_el3 -[^:]*: d51ecce3 msr icc_igrpen1_el3, x3 +[^:]*: d53ccbe0 mrs x0, ich_vmcr_el2 +[^:]*: d51ccbe0 msr ich_vmcr_el2, x0 +[^:]*: d53ccc00 mrs x0, ich_lr0_el2 +[^:]*: d51ccc00 msr ich_lr0_el2, x0 +[^:]*: d53ccc20 mrs x0, ich_lr1_el2 +[^:]*: d51ccc20 msr ich_lr1_el2, x0 +[^:]*: d53ccc40 mrs x0, ich_lr2_el2 +[^:]*: d51ccc40 msr ich_lr2_el2, x0 +[^:]*: d53ccc60 mrs x0, ich_lr3_el2 +[^:]*: d51ccc60 msr ich_lr3_el2, x0 +[^:]*: d53ccc80 mrs x0, ich_lr4_el2 +[^:]*: d51ccc80 msr ich_lr4_el2, x0 +[^:]*: d53ccca0 mrs x0, ich_lr5_el2 +[^:]*: d51ccca0 msr ich_lr5_el2, x0 +[^:]*: d53cccc0 mrs x0, ich_lr6_el2 +[^:]*: d51cccc0 msr ich_lr6_el2, x0 +[^:]*: d53ccce0 mrs x0, ich_lr7_el2 +[^:]*: d51ccce0 msr ich_lr7_el2, x0 +[^:]*: d53ccd00 mrs x0, ich_lr8_el2 +[^:]*: d51ccd00 msr ich_lr8_el2, x0 +[^:]*: d53ccd20 mrs x0, ich_lr9_el2 +[^:]*: d51ccd20 msr ich_lr9_el2, x0 +[^:]*: d53ccd40 mrs x0, ich_lr10_el2 +[^:]*: d51ccd40 msr ich_lr10_el2, x0 +[^:]*: d53ccd60 mrs x0, ich_lr11_el2 +[^:]*: d51ccd60 msr ich_lr11_el2, x0 +[^:]*: d53ccd80 mrs x0, ich_lr12_el2 +[^:]*: d51ccd80 msr ich_lr12_el2, x0 +[^:]*: d53ccda0 mrs x0, ich_lr13_el2 +[^:]*: d51ccda0 msr ich_lr13_el2, x0 +[^:]*: d53ccdc0 mrs x0, ich_lr14_el2 +[^:]*: d51ccdc0 msr ich_lr14_el2, x0 +[^:]*: d53ccde0 mrs x0, ich_lr15_el2 +[^:]*: d51ccde0 msr ich_lr15_el2, x0 +[^:]*: d53ecce0 mrs x0, icc_igrpen1_el3 +[^:]*: d51ecce0 msr icc_igrpen1_el3, x0 [^:]*: d538a4e0 mrs x0, lorid_el1 [^:]*: d5390040 mrs x0, ccsidr2_el1 -[^:]*: d5381222 mrs x2, trfcr_el1 -[^:]*: d5181223 msr trfcr_el1, x3 +[^:]*: d5381220 mrs x0, trfcr_el1 +[^:]*: d5181220 msr trfcr_el1, x0 [^:]*: d5389ec0 mrs x0, pmmir_el1 -[^:]*: d53c1222 mrs x2, trfcr_el2 -[^:]*: d51c1223 msr trfcr_el2, x3 -[^:]*: d53d1222 mrs x2, trfcr_el12 -[^:]*: d51d1223 msr trfcr_el12, x3 -[^:]*: d53bd202 mrs x2, amcr_el0 -[^:]*: d51bd203 msr amcr_el0, x3 +[^:]*: d53c1220 mrs x0, trfcr_el2 +[^:]*: d51c1220 msr trfcr_el2, x0 +[^:]*: d53d1220 mrs x0, trfcr_el12 +[^:]*: d51d1220 msr trfcr_el12, x0 +[^:]*: d53bd200 mrs x0, amcr_el0 +[^:]*: d51bd200 msr amcr_el0, x0 [^:]*: d53bd220 mrs x0, amcfgr_el0 [^:]*: d53bd240 mrs x0, amcgcr_el0 -[^:]*: d53bd262 mrs x2, amuserenr_el0 -[^:]*: d51bd263 msr amuserenr_el0, x3 -[^:]*: d53bd282 mrs x2, amcntenclr0_el0 -[^:]*: d51bd283 msr amcntenclr0_el0, x3 -[^:]*: d53bd2a2 mrs x2, amcntenset0_el0 -[^:]*: d51bd2a3 msr amcntenset0_el0, x3 -[^:]*: d53bd302 mrs x2, amcntenclr1_el0 -[^:]*: d51bd303 msr amcntenclr1_el0, x3 -[^:]*: d53bd322 mrs x2, amcntenset1_el0 -[^:]*: d51bd323 msr amcntenset1_el0, x3 -[^:]*: d53bd402 mrs x2, amevcntr00_el0 -[^:]*: d51bd403 msr amevcntr00_el0, x3 -[^:]*: d53bd422 mrs x2, amevcntr01_el0 -[^:]*: d51bd423 msr amevcntr01_el0, x3 -[^:]*: d53bd442 mrs x2, amevcntr02_el0 -[^:]*: d51bd443 msr amevcntr02_el0, x3 -[^:]*: d53bd462 mrs x2, amevcntr03_el0 -[^:]*: d51bd463 msr amevcntr03_el0, x3 +[^:]*: d53bd260 mrs x0, amuserenr_el0 +[^:]*: d51bd260 msr amuserenr_el0, x0 +[^:]*: d53bd280 mrs x0, amcntenclr0_el0 +[^:]*: d51bd280 msr amcntenclr0_el0, x0 +[^:]*: d53bd2a0 mrs x0, amcntenset0_el0 +[^:]*: d51bd2a0 msr amcntenset0_el0, x0 +[^:]*: d53bd300 mrs x0, amcntenclr1_el0 +[^:]*: d51bd300 msr amcntenclr1_el0, x0 +[^:]*: d53bd320 mrs x0, amcntenset1_el0 +[^:]*: d51bd320 msr amcntenset1_el0, x0 +[^:]*: d53bd400 mrs x0, amevcntr00_el0 +[^:]*: d51bd400 msr amevcntr00_el0, x0 +[^:]*: d53bd420 mrs x0, amevcntr01_el0 +[^:]*: d51bd420 msr amevcntr01_el0, x0 +[^:]*: d53bd440 mrs x0, amevcntr02_el0 +[^:]*: d51bd440 msr amevcntr02_el0, x0 +[^:]*: d53bd460 mrs x0, amevcntr03_el0 +[^:]*: d51bd460 msr amevcntr03_el0, x0 [^:]*: d53bd600 mrs x0, amevtyper00_el0 [^:]*: d53bd620 mrs x0, amevtyper01_el0 [^:]*: d53bd640 mrs x0, amevtyper02_el0 [^:]*: d53bd660 mrs x0, amevtyper03_el0 -[^:]*: d53bdc02 mrs x2, amevcntr10_el0 -[^:]*: d51bdc03 msr amevcntr10_el0, x3 -[^:]*: d53bdc22 mrs x2, amevcntr11_el0 -[^:]*: d51bdc23 msr amevcntr11_el0, x3 -[^:]*: d53bdc42 mrs x2, amevcntr12_el0 -[^:]*: d51bdc43 msr amevcntr12_el0, x3 -[^:]*: d53bdc62 mrs x2, amevcntr13_el0 -[^:]*: d51bdc63 msr amevcntr13_el0, x3 -[^:]*: d53bdc82 mrs x2, amevcntr14_el0 -[^:]*: d51bdc83 msr amevcntr14_el0, x3 -[^:]*: d53bdca2 mrs x2, amevcntr15_el0 -[^:]*: d51bdca3 msr amevcntr15_el0, x3 -[^:]*: d53bdcc2 mrs x2, amevcntr16_el0 -[^:]*: d51bdcc3 msr amevcntr16_el0, x3 -[^:]*: d53bdce2 mrs x2, amevcntr17_el0 -[^:]*: d51bdce3 msr amevcntr17_el0, x3 -[^:]*: d53bdd02 mrs x2, amevcntr18_el0 -[^:]*: d51bdd03 msr amevcntr18_el0, x3 -[^:]*: d53bdd22 mrs x2, amevcntr19_el0 -[^:]*: d51bdd23 msr amevcntr19_el0, x3 -[^:]*: d53bdd42 mrs x2, amevcntr110_el0 -[^:]*: d51bdd43 msr amevcntr110_el0, x3 -[^:]*: d53bdd62 mrs x2, amevcntr111_el0 -[^:]*: d51bdd63 msr amevcntr111_el0, x3 -[^:]*: d53bdd82 mrs x2, amevcntr112_el0 -[^:]*: d51bdd83 msr amevcntr112_el0, x3 -[^:]*: d53bdda2 mrs x2, amevcntr113_el0 -[^:]*: d51bdda3 msr amevcntr113_el0, x3 -[^:]*: d53bddc2 mrs x2, amevcntr114_el0 -[^:]*: d51bddc3 msr amevcntr114_el0, x3 -[^:]*: d53bdde2 mrs x2, amevcntr115_el0 -[^:]*: d51bdde3 msr amevcntr115_el0, x3 -[^:]*: d53bde02 mrs x2, amevtyper10_el0 -[^:]*: d51bde03 msr amevtyper10_el0, x3 -[^:]*: d53bde22 mrs x2, amevtyper11_el0 -[^:]*: d51bde23 msr amevtyper11_el0, x3 -[^:]*: d53bde42 mrs x2, amevtyper12_el0 -[^:]*: d51bde43 msr amevtyper12_el0, x3 -[^:]*: d53bde62 mrs x2, amevtyper13_el0 -[^:]*: d51bde63 msr amevtyper13_el0, x3 -[^:]*: d53bde82 mrs x2, amevtyper14_el0 -[^:]*: d51bde83 msr amevtyper14_el0, x3 -[^:]*: d53bdea2 mrs x2, amevtyper15_el0 -[^:]*: d51bdea3 msr amevtyper15_el0, x3 -[^:]*: d53bdec2 mrs x2, amevtyper16_el0 -[^:]*: d51bdec3 msr amevtyper16_el0, x3 -[^:]*: d53bdee2 mrs x2, amevtyper17_el0 -[^:]*: d51bdee3 msr amevtyper17_el0, x3 -[^:]*: d53bdf02 mrs x2, amevtyper18_el0 -[^:]*: d51bdf03 msr amevtyper18_el0, x3 -[^:]*: d53bdf22 mrs x2, amevtyper19_el0 -[^:]*: d51bdf23 msr amevtyper19_el0, x3 -[^:]*: d53bdf42 mrs x2, amevtyper110_el0 -[^:]*: d51bdf43 msr amevtyper110_el0, x3 -[^:]*: d53bdf62 mrs x2, amevtyper111_el0 -[^:]*: d51bdf63 msr amevtyper111_el0, x3 -[^:]*: d53bdf82 mrs x2, amevtyper112_el0 -[^:]*: d51bdf83 msr amevtyper112_el0, x3 -[^:]*: d53bdfa2 mrs x2, amevtyper113_el0 -[^:]*: d51bdfa3 msr amevtyper113_el0, x3 -[^:]*: d53bdfc2 mrs x2, amevtyper114_el0 -[^:]*: d51bdfc3 msr amevtyper114_el0, x3 -[^:]*: d53bdfe2 mrs x2, amevtyper115_el0 -[^:]*: d51bdfe3 msr amevtyper115_el0, x3 +[^:]*: d53bdc00 mrs x0, amevcntr10_el0 +[^:]*: d51bdc00 msr amevcntr10_el0, x0 +[^:]*: d53bdc20 mrs x0, amevcntr11_el0 +[^:]*: d51bdc20 msr amevcntr11_el0, x0 +[^:]*: d53bdc40 mrs x0, amevcntr12_el0 +[^:]*: d51bdc40 msr amevcntr12_el0, x0 +[^:]*: d53bdc60 mrs x0, amevcntr13_el0 +[^:]*: d51bdc60 msr amevcntr13_el0, x0 +[^:]*: d53bdc80 mrs x0, amevcntr14_el0 +[^:]*: d51bdc80 msr amevcntr14_el0, x0 +[^:]*: d53bdca0 mrs x0, amevcntr15_el0 +[^:]*: d51bdca0 msr amevcntr15_el0, x0 +[^:]*: d53bdcc0 mrs x0, amevcntr16_el0 +[^:]*: d51bdcc0 msr amevcntr16_el0, x0 +[^:]*: d53bdce0 mrs x0, amevcntr17_el0 +[^:]*: d51bdce0 msr amevcntr17_el0, x0 +[^:]*: d53bdd00 mrs x0, amevcntr18_el0 +[^:]*: d51bdd00 msr amevcntr18_el0, x0 +[^:]*: d53bdd20 mrs x0, amevcntr19_el0 +[^:]*: d51bdd20 msr amevcntr19_el0, x0 +[^:]*: d53bdd40 mrs x0, amevcntr110_el0 +[^:]*: d51bdd40 msr amevcntr110_el0, x0 +[^:]*: d53bdd60 mrs x0, amevcntr111_el0 +[^:]*: d51bdd60 msr amevcntr111_el0, x0 +[^:]*: d53bdd80 mrs x0, amevcntr112_el0 +[^:]*: d51bdd80 msr amevcntr112_el0, x0 +[^:]*: d53bdda0 mrs x0, amevcntr113_el0 +[^:]*: d51bdda0 msr amevcntr113_el0, x0 +[^:]*: d53bddc0 mrs x0, amevcntr114_el0 +[^:]*: d51bddc0 msr amevcntr114_el0, x0 +[^:]*: d53bdde0 mrs x0, amevcntr115_el0 +[^:]*: d51bdde0 msr amevcntr115_el0, x0 +[^:]*: d53bde00 mrs x0, amevtyper10_el0 +[^:]*: d51bde00 msr amevtyper10_el0, x0 +[^:]*: d53bde20 mrs x0, amevtyper11_el0 +[^:]*: d51bde20 msr amevtyper11_el0, x0 +[^:]*: d53bde40 mrs x0, amevtyper12_el0 +[^:]*: d51bde40 msr amevtyper12_el0, x0 +[^:]*: d53bde60 mrs x0, amevtyper13_el0 +[^:]*: d51bde60 msr amevtyper13_el0, x0 +[^:]*: d53bde80 mrs x0, amevtyper14_el0 +[^:]*: d51bde80 msr amevtyper14_el0, x0 +[^:]*: d53bdea0 mrs x0, amevtyper15_el0 +[^:]*: d51bdea0 msr amevtyper15_el0, x0 +[^:]*: d53bdec0 mrs x0, amevtyper16_el0 +[^:]*: d51bdec0 msr amevtyper16_el0, x0 +[^:]*: d53bdee0 mrs x0, amevtyper17_el0 +[^:]*: d51bdee0 msr amevtyper17_el0, x0 +[^:]*: d53bdf00 mrs x0, amevtyper18_el0 +[^:]*: d51bdf00 msr amevtyper18_el0, x0 +[^:]*: d53bdf20 mrs x0, amevtyper19_el0 +[^:]*: d51bdf20 msr amevtyper19_el0, x0 +[^:]*: d53bdf40 mrs x0, amevtyper110_el0 +[^:]*: d51bdf40 msr amevtyper110_el0, x0 +[^:]*: d53bdf60 mrs x0, amevtyper111_el0 +[^:]*: d51bdf60 msr amevtyper111_el0, x0 +[^:]*: d53bdf80 mrs x0, amevtyper112_el0 +[^:]*: d51bdf80 msr amevtyper112_el0, x0 +[^:]*: d53bdfa0 mrs x0, amevtyper113_el0 +[^:]*: d51bdfa0 msr amevtyper113_el0, x0 +[^:]*: d53bdfc0 mrs x0, amevtyper114_el0 +[^:]*: d51bdfc0 msr amevtyper114_el0, x0 +[^:]*: d53bdfe0 mrs x0, amevtyper115_el0 +[^:]*: d51bdfe0 msr amevtyper115_el0, x0 [^:]*: d53bd2c0 mrs x0, amcg1idr_el0 [^:]*: d53be0a0 mrs x0, cntpctss_el0 [^:]*: d53be0c0 mrs x0, cntvctss_el0 -[^:]*: d53c1182 mrs x2, hfgrtr_el2 -[^:]*: d51c1183 msr hfgrtr_el2, x3 -[^:]*: d53c11a2 mrs x2, hfgwtr_el2 -[^:]*: d51c11a3 msr hfgwtr_el2, x3 -[^:]*: d53c11c2 mrs x2, hfgitr_el2 -[^:]*: d51c11c3 msr hfgitr_el2, x3 -[^:]*: d53c3182 mrs x2, hdfgrtr_el2 -[^:]*: d51c3183 msr hdfgrtr_el2, x3 -[^:]*: d53c31a2 mrs x2, hdfgwtr_el2 -[^:]*: d51c31a3 msr hdfgwtr_el2, x3 -[^:]*: d53c31c2 mrs x2, hafgrtr_el2 -[^:]*: d51c31c3 msr hafgrtr_el2, x3 -[^:]*: d53cd802 mrs x2, amevcntvoff00_el2 -[^:]*: d51cd803 msr amevcntvoff00_el2, x3 -[^:]*: d53cd822 mrs x2, amevcntvoff01_el2 -[^:]*: d51cd823 msr amevcntvoff01_el2, x3 -[^:]*: d53cd842 mrs x2, amevcntvoff02_el2 -[^:]*: d51cd843 msr amevcntvoff02_el2, x3 -[^:]*: d53cd862 mrs x2, amevcntvoff03_el2 -[^:]*: d51cd863 msr amevcntvoff03_el2, x3 -[^:]*: d53cd882 mrs x2, amevcntvoff04_el2 -[^:]*: d51cd883 msr amevcntvoff04_el2, x3 -[^:]*: d53cd8a2 mrs x2, amevcntvoff05_el2 -[^:]*: d51cd8a3 msr amevcntvoff05_el2, x3 -[^:]*: d53cd8c2 mrs x2, amevcntvoff06_el2 -[^:]*: d51cd8c3 msr amevcntvoff06_el2, x3 -[^:]*: d53cd8e2 mrs x2, amevcntvoff07_el2 -[^:]*: d51cd8e3 msr amevcntvoff07_el2, x3 -[^:]*: d53cd902 mrs x2, amevcntvoff08_el2 -[^:]*: d51cd903 msr amevcntvoff08_el2, x3 -[^:]*: d53cd922 mrs x2, amevcntvoff09_el2 -[^:]*: d51cd923 msr amevcntvoff09_el2, x3 -[^:]*: d53cd942 mrs x2, amevcntvoff010_el2 -[^:]*: d51cd943 msr amevcntvoff010_el2, x3 -[^:]*: d53cd962 mrs x2, amevcntvoff011_el2 -[^:]*: d51cd963 msr amevcntvoff011_el2, x3 -[^:]*: d53cd982 mrs x2, amevcntvoff012_el2 -[^:]*: d51cd983 msr amevcntvoff012_el2, x3 -[^:]*: d53cd9a2 mrs x2, amevcntvoff013_el2 -[^:]*: d51cd9a3 msr amevcntvoff013_el2, x3 -[^:]*: d53cd9c2 mrs x2, amevcntvoff014_el2 -[^:]*: d51cd9c3 msr amevcntvoff014_el2, x3 -[^:]*: d53cd9e2 mrs x2, amevcntvoff015_el2 -[^:]*: d51cd9e3 msr amevcntvoff015_el2, x3 -[^:]*: d53cda02 mrs x2, amevcntvoff10_el2 -[^:]*: d51cda03 msr amevcntvoff10_el2, x3 -[^:]*: d53cda22 mrs x2, amevcntvoff11_el2 -[^:]*: d51cda23 msr amevcntvoff11_el2, x3 -[^:]*: d53cda42 mrs x2, amevcntvoff12_el2 -[^:]*: d51cda43 msr amevcntvoff12_el2, x3 -[^:]*: d53cda62 mrs x2, amevcntvoff13_el2 -[^:]*: d51cda63 msr amevcntvoff13_el2, x3 -[^:]*: d53cda82 mrs x2, amevcntvoff14_el2 -[^:]*: d51cda83 msr amevcntvoff14_el2, x3 -[^:]*: d53cdaa2 mrs x2, amevcntvoff15_el2 -[^:]*: d51cdaa3 msr amevcntvoff15_el2, x3 -[^:]*: d53cdac2 mrs x2, amevcntvoff16_el2 -[^:]*: d51cdac3 msr amevcntvoff16_el2, x3 -[^:]*: d53cdae2 mrs x2, amevcntvoff17_el2 -[^:]*: d51cdae3 msr amevcntvoff17_el2, x3 -[^:]*: d53cdb02 mrs x2, amevcntvoff18_el2 -[^:]*: d51cdb03 msr amevcntvoff18_el2, x3 -[^:]*: d53cdb22 mrs x2, amevcntvoff19_el2 -[^:]*: d51cdb23 msr amevcntvoff19_el2, x3 -[^:]*: d53cdb42 mrs x2, amevcntvoff110_el2 -[^:]*: d51cdb43 msr amevcntvoff110_el2, x3 -[^:]*: d53cdb62 mrs x2, amevcntvoff111_el2 -[^:]*: d51cdb63 msr amevcntvoff111_el2, x3 -[^:]*: d53cdb82 mrs x2, amevcntvoff112_el2 -[^:]*: d51cdb83 msr amevcntvoff112_el2, x3 -[^:]*: d53cdba2 mrs x2, amevcntvoff113_el2 -[^:]*: d51cdba3 msr amevcntvoff113_el2, x3 -[^:]*: d53cdbc2 mrs x2, amevcntvoff114_el2 -[^:]*: d51cdbc3 msr amevcntvoff114_el2, x3 -[^:]*: d53cdbe2 mrs x2, amevcntvoff115_el2 -[^:]*: d51cdbe3 msr amevcntvoff115_el2, x3 -[^:]*: d53ce0c2 mrs x2, cntpoff_el2 -[^:]*: d51ce0c3 msr cntpoff_el2, x3 -[^:]*: d5389922 mrs x2, pmsnevfr_el1 -[^:]*: d5189923 msr pmsnevfr_el1, x3 -[^:]*: d53c1242 mrs x2, hcrx_el2 -[^:]*: d51c1243 msr hcrx_el2, x3 -[^:]*: d538d0c2 mrs x2, rcwmask_el1 -[^:]*: d518d0c3 msr rcwmask_el1, x3 -[^:]*: d538d062 mrs x2, rcwsmask_el1 -[^:]*: d518d063 msr rcwsmask_el1, x3 +[^:]*: d53c1180 mrs x0, hfgrtr_el2 +[^:]*: d51c1180 msr hfgrtr_el2, x0 +[^:]*: d53c11a0 mrs x0, hfgwtr_el2 +[^:]*: d51c11a0 msr hfgwtr_el2, x0 +[^:]*: d53c11c0 mrs x0, hfgitr_el2 +[^:]*: d51c11c0 msr hfgitr_el2, x0 +[^:]*: d53c3180 mrs x0, hdfgrtr_el2 +[^:]*: d51c3180 msr hdfgrtr_el2, x0 +[^:]*: d53c31a0 mrs x0, hdfgwtr_el2 +[^:]*: d51c31a0 msr hdfgwtr_el2, x0 +[^:]*: d53c31c0 mrs x0, hafgrtr_el2 +[^:]*: d51c31c0 msr hafgrtr_el2, x0 +[^:]*: d53cd800 mrs x0, amevcntvoff00_el2 +[^:]*: d51cd800 msr amevcntvoff00_el2, x0 +[^:]*: d53cd820 mrs x0, amevcntvoff01_el2 +[^:]*: d51cd820 msr amevcntvoff01_el2, x0 +[^:]*: d53cd840 mrs x0, amevcntvoff02_el2 +[^:]*: d51cd840 msr amevcntvoff02_el2, x0 +[^:]*: d53cd860 mrs x0, amevcntvoff03_el2 +[^:]*: d51cd860 msr amevcntvoff03_el2, x0 +[^:]*: d53cd880 mrs x0, amevcntvoff04_el2 +[^:]*: d51cd880 msr amevcntvoff04_el2, x0 +[^:]*: d53cd8a0 mrs x0, amevcntvoff05_el2 +[^:]*: d51cd8a0 msr amevcntvoff05_el2, x0 +[^:]*: d53cd8c0 mrs x0, amevcntvoff06_el2 +[^:]*: d51cd8c0 msr amevcntvoff06_el2, x0 +[^:]*: d53cd8e0 mrs x0, amevcntvoff07_el2 +[^:]*: d51cd8e0 msr amevcntvoff07_el2, x0 +[^:]*: d53cd900 mrs x0, amevcntvoff08_el2 +[^:]*: d51cd900 msr amevcntvoff08_el2, x0 +[^:]*: d53cd920 mrs x0, amevcntvoff09_el2 +[^:]*: d51cd920 msr amevcntvoff09_el2, x0 +[^:]*: d53cd940 mrs x0, amevcntvoff010_el2 +[^:]*: d51cd940 msr amevcntvoff010_el2, x0 +[^:]*: d53cd960 mrs x0, amevcntvoff011_el2 +[^:]*: d51cd960 msr amevcntvoff011_el2, x0 +[^:]*: d53cd980 mrs x0, amevcntvoff012_el2 +[^:]*: d51cd980 msr amevcntvoff012_el2, x0 +[^:]*: d53cd9a0 mrs x0, amevcntvoff013_el2 +[^:]*: d51cd9a0 msr amevcntvoff013_el2, x0 +[^:]*: d53cd9c0 mrs x0, amevcntvoff014_el2 +[^:]*: d51cd9c0 msr amevcntvoff014_el2, x0 +[^:]*: d53cd9e0 mrs x0, amevcntvoff015_el2 +[^:]*: d51cd9e0 msr amevcntvoff015_el2, x0 +[^:]*: d53cda00 mrs x0, amevcntvoff10_el2 +[^:]*: d51cda00 msr amevcntvoff10_el2, x0 +[^:]*: d53cda20 mrs x0, amevcntvoff11_el2 +[^:]*: d51cda20 msr amevcntvoff11_el2, x0 +[^:]*: d53cda40 mrs x0, amevcntvoff12_el2 +[^:]*: d51cda40 msr amevcntvoff12_el2, x0 +[^:]*: d53cda60 mrs x0, amevcntvoff13_el2 +[^:]*: d51cda60 msr amevcntvoff13_el2, x0 +[^:]*: d53cda80 mrs x0, amevcntvoff14_el2 +[^:]*: d51cda80 msr amevcntvoff14_el2, x0 +[^:]*: d53cdaa0 mrs x0, amevcntvoff15_el2 +[^:]*: d51cdaa0 msr amevcntvoff15_el2, x0 +[^:]*: d53cdac0 mrs x0, amevcntvoff16_el2 +[^:]*: d51cdac0 msr amevcntvoff16_el2, x0 +[^:]*: d53cdae0 mrs x0, amevcntvoff17_el2 +[^:]*: d51cdae0 msr amevcntvoff17_el2, x0 +[^:]*: d53cdb00 mrs x0, amevcntvoff18_el2 +[^:]*: d51cdb00 msr amevcntvoff18_el2, x0 +[^:]*: d53cdb20 mrs x0, amevcntvoff19_el2 +[^:]*: d51cdb20 msr amevcntvoff19_el2, x0 +[^:]*: d53cdb40 mrs x0, amevcntvoff110_el2 +[^:]*: d51cdb40 msr amevcntvoff110_el2, x0 +[^:]*: d53cdb60 mrs x0, amevcntvoff111_el2 +[^:]*: d51cdb60 msr amevcntvoff111_el2, x0 +[^:]*: d53cdb80 mrs x0, amevcntvoff112_el2 +[^:]*: d51cdb80 msr amevcntvoff112_el2, x0 +[^:]*: d53cdba0 mrs x0, amevcntvoff113_el2 +[^:]*: d51cdba0 msr amevcntvoff113_el2, x0 +[^:]*: d53cdbc0 mrs x0, amevcntvoff114_el2 +[^:]*: d51cdbc0 msr amevcntvoff114_el2, x0 +[^:]*: d53cdbe0 mrs x0, amevcntvoff115_el2 +[^:]*: d51cdbe0 msr amevcntvoff115_el2, x0 +[^:]*: d53ce0c0 mrs x0, cntpoff_el2 +[^:]*: d51ce0c0 msr cntpoff_el2, x0 +[^:]*: d5389920 mrs x0, pmsnevfr_el1 +[^:]*: d5189920 msr pmsnevfr_el1, x0 +[^:]*: d53c1240 mrs x0, hcrx_el2 +[^:]*: d51c1240 msr hcrx_el2, x0 +[^:]*: d538d0c0 mrs x0, rcwmask_el1 +[^:]*: d518d0c0 msr rcwmask_el1, x0 +[^:]*: d538d060 mrs x0, rcwsmask_el1 +[^:]*: d518d060 msr rcwsmask_el1, x0 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s index 21daa8c8c65..bf555d23b82 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s @@ -3,12 +3,12 @@ .endm .macro woreg, name - msr \name, x1 + msr \name, x0 .endm .macro rwreg, name - mrs x2, \name - msr \name, x3 + mrs x0, \name + msr \name, x0 .endm roreg id_dfr1_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg128.d b/gas/testsuite/gas/aarch64/sysreg/sysreg128.d index 8c9f7ca14d1..cb895c64503 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg128.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg128.d @@ -7,22 +7,22 @@ Disassembly of section \.text: 0+ <\.text>: [^:]*: d5787402 mrrs x2, x3, par_el1 -[^:]*: d5587404 msrr par_el1, x4, x5 +[^:]*: d5587402 msrr par_el1, x2, x3 [^:]*: d578d0c2 mrrs x2, x3, rcwmask_el1 -[^:]*: d558d0c4 msrr rcwmask_el1, x4, x5 +[^:]*: d558d0c2 msrr rcwmask_el1, x2, x3 [^:]*: d578d062 mrrs x2, x3, rcwsmask_el1 -[^:]*: d558d064 msrr rcwsmask_el1, x4, x5 +[^:]*: d558d062 msrr rcwsmask_el1, x2, x3 [^:]*: d5782002 mrrs x2, x3, ttbr0_el1 -[^:]*: d5582004 msrr ttbr0_el1, x4, x5 +[^:]*: d5582002 msrr ttbr0_el1, x2, x3 [^:]*: d57d2002 mrrs x2, x3, ttbr0_el12 -[^:]*: d55d2004 msrr ttbr0_el12, x4, x5 +[^:]*: d55d2002 msrr ttbr0_el12, x2, x3 [^:]*: d57c2002 mrrs x2, x3, ttbr0_el2 -[^:]*: d55c2004 msrr ttbr0_el2, x4, x5 +[^:]*: d55c2002 msrr ttbr0_el2, x2, x3 [^:]*: d5782022 mrrs x2, x3, ttbr1_el1 -[^:]*: d5582024 msrr ttbr1_el1, x4, x5 +[^:]*: d5582022 msrr ttbr1_el1, x2, x3 [^:]*: d57d2022 mrrs x2, x3, ttbr1_el12 -[^:]*: d55d2024 msrr ttbr1_el12, x4, x5 +[^:]*: d55d2022 msrr ttbr1_el12, x2, x3 [^:]*: d57c2022 mrrs x2, x3, ttbr1_el2 -[^:]*: d55c2024 msrr ttbr1_el2, x4, x5 +[^:]*: d55c2022 msrr ttbr1_el2, x2, x3 [^:]*: d57c2102 mrrs x2, x3, vttbr_el2 -[^:]*: d55c2104 msrr vttbr_el2, x4, x5 \ No newline at end of file +[^:]*: d55c2102 msrr vttbr_el2, x2, x3 \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg128.s b/gas/testsuite/gas/aarch64/sysreg/sysreg128.s index 4093315973d..09c9dace9b5 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg128.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg128.s @@ -2,7 +2,7 @@ .macro rwreg128, name mrrs x2, x3, \name - msrr \name, x4, x5 + msrr \name, x2, x3 .endm rwreg128 par_el1 From patchwork Tue Feb 27 10:59:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthieu Longo X-Patchwork-Id: 207136 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2620039dyb; Tue, 27 Feb 2024 03:01:31 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWp2I2MJdAqVfPxWS/Zdne2sF2MruID45QsyXhSjFHUA9FC7XHiNqK4rPI2Nkx+LLfIRWosFRytM7bKwON/AKh1jDWixQ== X-Google-Smtp-Source: AGHT+IFg9PN3b4uWvBH7LKYuH9OKk3JY1I6YwxaoUwjT7tMKByTCCeOktTvwTdWR/5Xpg43hgw5l X-Received: by 2002:a05:620a:2058:b0:787:b0b2:3e27 with SMTP id d24-20020a05620a205800b00787b0b23e27mr1372661qka.17.1709031690986; Tue, 27 Feb 2024 03:01:30 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709031690; cv=pass; d=google.com; s=arc-20160816; b=I7jtwqKXXEO7kvnmMz/koNMAHdbmJi8ywd19cx3CZMQtYsigaGBNmR7MgoNzKSFTif DsaJZv+9JuCydwCBZFWBa+Cno1vraj/nnOg0v04hmUWDp5p3+SZ+vFQtRxri2Ca2yxzu xdhrXOyllJIZPCDgjmEzUr2/WwedMWn83/9I0iQ3YKn/s/Rjw7qPkxp93pPVLugjJUGN 3/r+gORA7/0txD2e1n+nFfRnB0qwjKIi3zTXR2E2InM2T7bUyFXLbrPLhjZ5T5GeWpsD 9bYgMirsDX10objg1Cwwt2lqQKjMnBDIdn4qaDLNG0AlLRIGDQ7CKskdu5xoZMWx0Pz1 iPmg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=KseFxvORReKDR2i3bjI/Gziu2TN6l2saxJ4NXoRiWuo=; fh=bcbSBk6kL0yCjqxjmEWwFzJxBMxjhnM2jUxTrAFje1Y=; b=SzJf2iXDfpIRyxnL2dryiyE278PoTyEoqRcpPcTDtSOaP04kRLg8KlS+VwLjbntMLX AP7GNZOn/QDC87PLvj0plnudupBte+VOb+y2D3iyKwYdKBLDXrCtXLM5qNL0aUCatrg7 8/Izr79EHyUyf3lhg1GAmFTPdRPouzEni/eQjMfiNrTJ17QXvcRbK884VQEyI4qWq/p+ zt499tfa8Sz4eWy2chFjk5qMfiE0YNGJeEqRJbRoyyNcj93TifywRZGgsK7VgJkLQmjX RLciko8zL6QDuZP6ELHWw3AVkyAXic+1JU77sh9TAKMgNh4jBfFz9a4FgvTWp3uq+EmB PgCw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id u4-20020a05620a084400b00785dadcf1fdsi6924430qku.23.2024.02.27.03.01.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 03:01:30 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 98D3F3858420 for ; Tue, 27 Feb 2024 11:01:30 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat-cam5.arm.com [217.140.106.53]) by sourceware.org (Postfix) with ESMTPS id D3E093858436 for ; Tue, 27 Feb 2024 11:00:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D3E093858436 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D3E093858436 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.106.53 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709031607; cv=none; b=APUB3zBFv2FIr4pQkWbnFG3F/Ov/3PJ1sh6O778pyYNsrr3g4mz+Q0X6uHqQ0FpTVqNZP2V/23AOu6REYAZqZA6rTVtFT9LrSMwkL/SmdRViy2VfboYCpKSFybzMA3up4XJPRP9TJZdRPkGDNNArgJ2Ig8YTcYxOWprPMT6gMEg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709031607; c=relaxed/simple; bh=6uhDQYQWxdnSGwGGIZXVg/7VM1E2dshzroJ7mlQZVXM=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=tlmwm2/N7um6Yh3qEK5L5s8WeY5qxVHE8umBrWeB/qAsSMT4ij4UK/0uBYCuAsEQyBAcVdPvJFEdkWqlHsLmT5+RIdSKSPdaGJCJSpVG/zsSjhx7hLLktwb6VX+OxV7RUn1X/s8yWn1UeKLPINgcwKfE2Bv7azLb3mttBcQ+KvY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from e129756.cambridge.arm.com (e129756.arm.com [10.2.78.55]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id 41RAxnZR030743; Tue, 27 Feb 2024 10:59:58 GMT From: Matthieu Longo To: binutils@sourceware.org Cc: Richard Earnshaw , Nick Clifton , Matthieu Longo Subject: [PATCH v1 3/4] aarch64: testsuite: reorder write and read to match macro order Date: Tue, 27 Feb 2024 10:59:16 +0000 Message-Id: <20240227105917.295899-4-matthieu.longo@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227105917.295899-1-matthieu.longo@arm.com> References: <20240227105917.295899-1-matthieu.longo@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KHOP_HELO_FCRDNS, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792049614421683212 X-GMAIL-MSGID: 1792049614421683212 This patch aims at grouping write and read for a same system register one after another so that the diff for the macro replacement does not generate too much noise. --- .../aarch64/sysreg/armv8_9-a-sysregs-bad.l | 56 ++-- .../gas/aarch64/sysreg/armv8_9-a-sysregs.d | 88 +++--- .../gas/aarch64/sysreg/armv8_9-a-sysregs.s | 90 +++--- gas/testsuite/gas/aarch64/sysreg/sysreg-7.d | 16 +- gas/testsuite/gas/aarch64/sysreg/sysreg-7.s | 20 +- gas/testsuite/gas/aarch64/sysreg/sysreg-8.d | 258 +++++++++--------- gas/testsuite/gas/aarch64/sysreg/sysreg-8.s | 2 +- gas/testsuite/gas/aarch64/sysreg/sysreg.d | 10 +- gas/testsuite/gas/aarch64/sysreg/sysreg.s | 14 +- gas/testsuite/gas/aarch64/sysreg/sysreg128.d | 22 +- gas/testsuite/gas/aarch64/sysreg/sysreg128.s | 2 +- 11 files changed, 286 insertions(+), 292 deletions(-) diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l index 02d9cac392c..d98c2ed573a 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l @@ -3,79 +3,79 @@ .*: Error: selected processor does not support system register name 'pmsdsfr_el1' .*: Error: selected processor does not support system register name 'erxgsr_el1' .*: Error: selected processor does not support system register name 'sctlr2_el1' -.*: Error: selected processor does not support system register name 'sctlr2_el12' -.*: Error: selected processor does not support system register name 'sctlr2_el2' -.*: Error: selected processor does not support system register name 'sctlr2_el3' .*: Error: selected processor does not support system register name 'sctlr2_el1' .*: Error: selected processor does not support system register name 'sctlr2_el12' +.*: Error: selected processor does not support system register name 'sctlr2_el12' .*: Error: selected processor does not support system register name 'sctlr2_el2' +.*: Error: selected processor does not support system register name 'sctlr2_el2' +.*: Error: selected processor does not support system register name 'sctlr2_el3' .*: Error: selected processor does not support system register name 'sctlr2_el3' .*: Error: selected processor does not support system register name 'hdfgrtr2_el2' -.*: Error: selected processor does not support system register name 'hdfgwtr2_el2' -.*: Error: selected processor does not support system register name 'hfgrtr2_el2' -.*: Error: selected processor does not support system register name 'hfgwtr2_el2' .*: Error: selected processor does not support system register name 'hdfgrtr2_el2' .*: Error: selected processor does not support system register name 'hdfgwtr2_el2' +.*: Error: selected processor does not support system register name 'hdfgwtr2_el2' +.*: Error: selected processor does not support system register name 'hfgrtr2_el2' .*: Error: selected processor does not support system register name 'hfgrtr2_el2' .*: Error: selected processor does not support system register name 'hfgwtr2_el2' +.*: Error: selected processor does not support system register name 'hfgwtr2_el2' .*: Error: selected processor does not support system register name 'pfar_el1' -.*: Error: selected processor does not support system register name 'pfar_el2' -.*: Error: selected processor does not support system register name 'pfar_el12' .*: Error: selected processor does not support system register name 'pfar_el1' .*: Error: selected processor does not support system register name 'pfar_el2' +.*: Error: selected processor does not support system register name 'pfar_el2' +.*: Error: selected processor does not support system register name 'pfar_el12' .*: Error: selected processor does not support system register name 'pfar_el12' .*: Error: selected processor does not support system register name 's1e1a' .*: Error: selected processor does not support system register name 's1e2a' .*: Error: selected processor does not support system register name 's1e3a' .*: Error: selected processor does not support system register name 'amair2_el1' -.*: Error: selected processor does not support system register name 'amair2_el12' -.*: Error: selected processor does not support system register name 'amair2_el2' -.*: Error: selected processor does not support system register name 'amair2_el3' -.*: Error: selected processor does not support system register name 'mair2_el1' -.*: Error: selected processor does not support system register name 'mair2_el12' -.*: Error: selected processor does not support system register name 'mair2_el2' -.*: Error: selected processor does not support system register name 'mair2_el3' .*: Error: selected processor does not support system register name 'amair2_el1' .*: Error: selected processor does not support system register name 'amair2_el12' +.*: Error: selected processor does not support system register name 'amair2_el12' +.*: Error: selected processor does not support system register name 'amair2_el2' .*: Error: selected processor does not support system register name 'amair2_el2' .*: Error: selected processor does not support system register name 'amair2_el3' +.*: Error: selected processor does not support system register name 'amair2_el3' +.*: Error: selected processor does not support system register name 'mair2_el1' .*: Error: selected processor does not support system register name 'mair2_el1' .*: Error: selected processor does not support system register name 'mair2_el12' +.*: Error: selected processor does not support system register name 'mair2_el12' .*: Error: selected processor does not support system register name 'mair2_el2' +.*: Error: selected processor does not support system register name 'mair2_el2' +.*: Error: selected processor does not support system register name 'mair2_el3' .*: Error: selected processor does not support system register name 'mair2_el3' .*: Error: selected processor does not support system register name 'pir_el1' -.*: Error: selected processor does not support system register name 'pir_el12' -.*: Error: selected processor does not support system register name 'pir_el2' -.*: Error: selected processor does not support system register name 'pir_el3' -.*: Error: selected processor does not support system register name 'pire0_el1' -.*: Error: selected processor does not support system register name 'pire0_el12' -.*: Error: selected processor does not support system register name 'pire0_el2' .*: Error: selected processor does not support system register name 'pir_el1' .*: Error: selected processor does not support system register name 'pir_el12' +.*: Error: selected processor does not support system register name 'pir_el12' .*: Error: selected processor does not support system register name 'pir_el2' +.*: Error: selected processor does not support system register name 'pir_el2' +.*: Error: selected processor does not support system register name 'pir_el3' .*: Error: selected processor does not support system register name 'pir_el3' .*: Error: selected processor does not support system register name 'pire0_el1' +.*: Error: selected processor does not support system register name 'pire0_el1' +.*: Error: selected processor does not support system register name 'pire0_el12' .*: Error: selected processor does not support system register name 'pire0_el12' .*: Error: selected processor does not support system register name 'pire0_el2' +.*: Error: selected processor does not support system register name 'pire0_el2' .*: Error: selected processor does not support system register name 's2pir_el2' .*: Error: selected processor does not support system register name 's2pir_el2' .*: Error: selected processor does not support system register name 'por_el0' -.*: Error: selected processor does not support system register name 'por_el1' -.*: Error: selected processor does not support system register name 'por_el12' -.*: Error: selected processor does not support system register name 'por_el2' -.*: Error: selected processor does not support system register name 'por_el3' .*: Error: selected processor does not support system register name 'por_el0' .*: Error: selected processor does not support system register name 'por_el1' +.*: Error: selected processor does not support system register name 'por_el1' +.*: Error: selected processor does not support system register name 'por_el12' .*: Error: selected processor does not support system register name 'por_el12' .*: Error: selected processor does not support system register name 'por_el2' +.*: Error: selected processor does not support system register name 'por_el2' +.*: Error: selected processor does not support system register name 'por_el3' .*: Error: selected processor does not support system register name 'por_el3' .*: Error: selected processor does not support system register name 's2por_el1' .*: Error: selected processor does not support system register name 's2por_el1' .*: Error: selected processor does not support system register name 'tcr2_el1' -.*: Error: selected processor does not support system register name 'tcr2_el12' -.*: Error: selected processor does not support system register name 'tcr2_el2' .*: Error: selected processor does not support system register name 'tcr2_el1' .*: Error: selected processor does not support system register name 'tcr2_el12' +.*: Error: selected processor does not support system register name 'tcr2_el12' +.*: Error: selected processor does not support system register name 'tcr2_el2' .*: Error: selected processor does not support system register name 'tcr2_el2' .*: Error: selected processor does not support system register name 'mdselr_el1' .*: Error: selected processor does not support system register name 'mdselr_el1' @@ -123,4 +123,4 @@ .*: Error: selected processor does not support system register name 'pmecr_el1' .*: Error: selected processor does not support system register name 'pmecr_el1' .*: Error: selected processor does not support system register name 'pmiar_el1' -.*: Error: selected processor does not support system register name 'pmiar_el1' +.*: Error: selected processor does not support system register name 'pmiar_el1' \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d index dc1e8bc1fa8..ac32b80b40c 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d @@ -6,92 +6,92 @@ Disassembly of section \.text: 0+ <.*>: -.*: d53c9a83 mrs x3, pmsdsfr_el1 .*: d51c9a83 msr pmsdsfr_el1, x3 +.*: d53c9a83 mrs x3, pmsdsfr_el1 .*: d5385340 mrs x0, erxgsr_el1 .*: d5181063 msr sctlr2_el1, x3 -.*: d51d1063 msr sctlr2_el12, x3 -.*: d51c1063 msr sctlr2_el2, x3 -.*: d51e1063 msr sctlr2_el3, x3 .*: d5381063 mrs x3, sctlr2_el1 +.*: d51d1063 msr sctlr2_el12, x3 .*: d53d1063 mrs x3, sctlr2_el12 +.*: d51c1063 msr sctlr2_el2, x3 .*: d53c1063 mrs x3, sctlr2_el2 +.*: d51e1063 msr sctlr2_el3, x3 .*: d53e1063 mrs x3, sctlr2_el3 -.*: d53c3103 mrs x3, hdfgrtr2_el2 -.*: d53c3123 mrs x3, hdfgwtr2_el2 -.*: d53c3143 mrs x3, hfgrtr2_el2 -.*: d53c3163 mrs x3, hfgwtr2_el2 .*: d51c3103 msr hdfgrtr2_el2, x3 +.*: d53c3103 mrs x3, hdfgrtr2_el2 .*: d51c3123 msr hdfgwtr2_el2, x3 +.*: d53c3123 mrs x3, hdfgwtr2_el2 .*: d51c3143 msr hfgrtr2_el2, x3 +.*: d53c3143 mrs x3, hfgrtr2_el2 .*: d51c3163 msr hfgwtr2_el2, x3 -.*: d53860a0 mrs x0, pfar_el1 -.*: d53c60a0 mrs x0, pfar_el2 -.*: d53d60a0 mrs x0, pfar_el12 +.*: d53c3163 mrs x3, hfgwtr2_el2 .*: d51860a0 msr pfar_el1, x0 +.*: d53860a0 mrs x0, pfar_el1 .*: d51c60a0 msr pfar_el2, x0 +.*: d53c60a0 mrs x0, pfar_el2 .*: d51d60a0 msr pfar_el12, x0 +.*: d53d60a0 mrs x0, pfar_el12 .*: d5087941 at s1e1a, x1 .*: d50c7943 at s1e2a, x3 .*: d50e7945 at s1e3a, x5 -.*: d538a320 mrs x0, amair2_el1 -.*: d53da320 mrs x0, amair2_el12 -.*: d53ca320 mrs x0, amair2_el2 -.*: d53ea320 mrs x0, amair2_el3 -.*: d538a220 mrs x0, mair2_el1 -.*: d53da220 mrs x0, mair2_el12 -.*: d53ca120 mrs x0, mair2_el2 -.*: d53ea120 mrs x0, mair2_el3 .*: d518a320 msr amair2_el1, x0 +.*: d538a320 mrs x0, amair2_el1 .*: d51da320 msr amair2_el12, x0 +.*: d53da320 mrs x0, amair2_el12 .*: d51ca320 msr amair2_el2, x0 +.*: d53ca320 mrs x0, amair2_el2 .*: d51ea320 msr amair2_el3, x0 +.*: d53ea320 mrs x0, amair2_el3 .*: d518a220 msr mair2_el1, x0 +.*: d538a220 mrs x0, mair2_el1 .*: d51da220 msr mair2_el12, x0 +.*: d53da220 mrs x0, mair2_el12 .*: d51ca120 msr mair2_el2, x0 +.*: d53ca120 mrs x0, mair2_el2 .*: d51ea120 msr mair2_el3, x0 -.*: d538a260 mrs x0, pir_el1 -.*: d53da260 mrs x0, pir_el12 -.*: d53ca260 mrs x0, pir_el2 -.*: d53ea260 mrs x0, pir_el3 -.*: d538a240 mrs x0, pire0_el1 -.*: d53da240 mrs x0, pire0_el12 -.*: d53ca240 mrs x0, pire0_el2 +.*: d53ea120 mrs x0, mair2_el3 .*: d518a260 msr pir_el1, x0 +.*: d538a260 mrs x0, pir_el1 .*: d51da260 msr pir_el12, x0 +.*: d53da260 mrs x0, pir_el12 .*: d51ca260 msr pir_el2, x0 +.*: d53ca260 mrs x0, pir_el2 .*: d51ea260 msr pir_el3, x0 +.*: d53ea260 mrs x0, pir_el3 .*: d518a240 msr pire0_el1, x0 +.*: d538a240 mrs x0, pire0_el1 .*: d51da240 msr pire0_el12, x0 +.*: d53da240 mrs x0, pire0_el12 .*: d51ca240 msr pire0_el2, x0 -.*: d53ca2a0 mrs x0, s2pir_el2 +.*: d53ca240 mrs x0, pire0_el2 .*: d51ca2a0 msr s2pir_el2, x0 -.*: d53ba280 mrs x0, por_el0 -.*: d538a280 mrs x0, por_el1 -.*: d53da280 mrs x0, por_el12 -.*: d53ca280 mrs x0, por_el2 -.*: d53ea280 mrs x0, por_el3 +.*: d53ca2a0 mrs x0, s2pir_el2 .*: d51ba280 msr por_el0, x0 +.*: d53ba280 mrs x0, por_el0 .*: d518a280 msr por_el1, x0 +.*: d538a280 mrs x0, por_el1 .*: d51da280 msr por_el12, x0 +.*: d53da280 mrs x0, por_el12 .*: d51ca280 msr por_el2, x0 +.*: d53ca280 mrs x0, por_el2 .*: d51ea280 msr por_el3, x0 -.*: d538a2a0 mrs x0, s2por_el1 +.*: d53ea280 mrs x0, por_el3 .*: d518a2a0 msr s2por_el1, x0 -.*: d5382060 mrs x0, tcr2_el1 -.*: d53d2060 mrs x0, tcr2_el12 -.*: d53c2060 mrs x0, tcr2_el2 +.*: d538a2a0 mrs x0, s2por_el1 .*: d5182060 msr tcr2_el1, x0 +.*: d5382060 mrs x0, tcr2_el1 .*: d51d2060 msr tcr2_el12, x0 +.*: d53d2060 mrs x0, tcr2_el12 .*: d51c2060 msr tcr2_el2, x0 -.*: d5300440 mrs x0, mdselr_el1 +.*: d53c2060 mrs x0, tcr2_el2 .*: d5100440 msr mdselr_el1, x0 -.*: d5389e80 mrs x0, pmuacr_el1 +.*: d5300440 mrs x0, mdselr_el1 .*: d5189e80 msr pmuacr_el1, x0 +.*: d5389e80 mrs x0, pmuacr_el1 .*: d530ebe0 mrs x0, pmccntsvr_el1 .*: d530ec00 mrs x0, pmicntsvr_el1 -.*: d5389d60 mrs x0, pmsscr_el1 .*: d5189d60 msr pmsscr_el1, x0 +.*: d5389d60 mrs x0, pmsscr_el1 .*: d530e800 mrs x0, pmevcntsvr0_el1 .*: d530e940 mrs x0, pmevcntsvr10_el1 .*: d530e960 mrs x0, pmevcntsvr11_el1 @@ -122,12 +122,12 @@ Disassembly of section \.text: .*: d530e8e0 mrs x0, pmevcntsvr7_el1 .*: d530e900 mrs x0, pmevcntsvr8_el1 .*: d530e920 mrs x0, pmevcntsvr9_el1 -.*: d53b9400 mrs x0, pmicntr_el0 .*: d51b9400 msr pmicntr_el0, x0 -.*: d53b9600 mrs x0, pmicfiltr_el0 +.*: d53b9400 mrs x0, pmicntr_el0 .*: d51b9600 msr pmicfiltr_el0, x0 +.*: d53b9600 mrs x0, pmicfiltr_el0 .*: d51b9d80 msr pmzr_el0, x0 -.*: d5389ea0 mrs x0, pmecr_el1 .*: d5189ea0 msr pmecr_el1, x0 -.*: d5389ee0 mrs x0, pmiar_el1 -.*: d5189ee0 msr pmiar_el1, x0 \ No newline at end of file +.*: d5389ea0 mrs x0, pmecr_el1 +.*: d5189ee0 msr pmiar_el1, x0 +.*: d5389ee0 mrs x0, pmiar_el1 \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s index 536631823f5..bf9019c9ac8 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s @@ -1,32 +1,32 @@ - mrs x3, PMSDSFR_EL1 msr PMSDSFR_EL1, x3 + mrs x3, PMSDSFR_EL1 mrs x0, ERXGSR_EL1 msr SCTLR2_EL1, x3 - msr SCTLR2_EL12, x3 - msr SCTLR2_EL2, x3 - msr SCTLR2_EL3, x3 mrs x3, SCTLR2_EL1 + msr SCTLR2_EL12, x3 mrs x3, SCTLR2_EL12 + msr SCTLR2_EL2, x3 mrs x3, SCTLR2_EL2 + msr SCTLR2_EL3, x3 mrs x3, SCTLR2_EL3 - mrs x3, HDFGRTR2_EL2 - mrs x3, HDFGWTR2_EL2 - mrs x3, HFGRTR2_EL2 - mrs x3, HFGWTR2_EL2 msr HDFGRTR2_EL2, x3 + mrs x3, HDFGRTR2_EL2 msr HDFGWTR2_EL2, x3 + mrs x3, HDFGWTR2_EL2 msr HFGRTR2_EL2, x3 + mrs x3, HFGRTR2_EL2 msr HFGWTR2_EL2, x3 + mrs x3, HFGWTR2_EL2 - mrs x0, PFAR_EL1 - mrs x0, PFAR_EL2 - mrs x0, PFAR_EL12 msr PFAR_EL1, x0 + mrs x0, PFAR_EL1 msr PFAR_EL2, x0 + mrs x0, PFAR_EL2 msr PFAR_EL12, x0 + mrs x0, PFAR_EL12 /* AT. */ at s1e1a, x1 @@ -34,84 +34,80 @@ at s1e3a, x5 /* FEAT_AIE. */ - mrs x0, amair2_el1 - mrs x0, amair2_el12 - mrs x0, amair2_el2 - mrs x0, amair2_el3 - mrs x0, mair2_el1 - mrs x0, mair2_el12 - mrs x0, mair2_el2 - mrs x0, mair2_el3 - msr amair2_el1, x0 + mrs x0, amair2_el1 msr amair2_el12, x0 + mrs x0, amair2_el12 msr amair2_el2, x0 + mrs x0, amair2_el2 msr amair2_el3, x0 + mrs x0, amair2_el3 msr mair2_el1, x0 + mrs x0, mair2_el1 msr mair2_el12, x0 + mrs x0, mair2_el12 msr mair2_el2, x0 + mrs x0, mair2_el2 msr mair2_el3, x0 + mrs x0, mair2_el3 /* FEAT_S1PIE. */ - mrs x0, pir_el1 - mrs x0, pir_el12 - mrs x0, pir_el2 - mrs x0, pir_el3 - mrs x0, pire0_el1 - mrs x0, pire0_el12 - mrs x0, pire0_el2 - msr pir_el1, x0 + mrs x0, pir_el1 msr pir_el12, x0 + mrs x0, pir_el12 msr pir_el2, x0 + mrs x0, pir_el2 msr pir_el3, x0 + mrs x0, pir_el3 msr pire0_el1, x0 + mrs x0, pire0_el1 msr pire0_el12, x0 + mrs x0, pire0_el12 msr pire0_el2, x0 + mrs x0, pire0_el2 /* FEAT_S2PIE. */ - mrs x0, s2pir_el2 msr s2pir_el2, x0 + mrs x0, s2pir_el2 /* FEAT_S1POE. */ - mrs x0, por_el0 - mrs x0, por_el1 - mrs x0, por_el12 - mrs x0, por_el2 - mrs x0, por_el3 - msr por_el0, x0 + mrs x0, por_el0 msr por_el1, x0 + mrs x0, por_el1 msr por_el12, x0 + mrs x0, por_el12 msr por_el2, x0 + mrs x0, por_el2 msr por_el3, x0 + mrs x0, por_el3 /* FEAT_S21POE. */ - mrs x0, s2por_el1 msr s2por_el1, x0 + mrs x0, s2por_el1 /* FEAT_TCR2. */ - mrs x0, tcr2_el1 - mrs x0, tcr2_el12 - mrs x0, tcr2_el2 - msr tcr2_el1, x0 + mrs x0, tcr2_el1 msr tcr2_el12, x0 + mrs x0, tcr2_el12 msr tcr2_el2, x0 + mrs x0, tcr2_el2 /* FEAT_DEBUGv8p9 Extension. */ - mrs x0, mdselr_el1 msr mdselr_el1, x0 + mrs x0, mdselr_el1 /* FEAT_PMUv3p9 Extension. */ - mrs x0, pmuacr_el1 msr pmuacr_el1, x0 + mrs x0, pmuacr_el1 /* FEAT_PMUv3_SS Extension. */ mrs x0, pmccntsvr_el1 mrs x0, pmicntsvr_el1 - mrs x0, pmsscr_el1 msr pmsscr_el1, x0 + mrs x0, pmsscr_el1 mrs x0, pmevcntsvr0_el1 mrs x0, pmevcntsvr10_el1 mrs x0, pmevcntsvr11_el1 @@ -144,14 +140,14 @@ mrs x0, pmevcntsvr9_el1 /* FEAT_PMUv3_ICNTR Extension. */ - mrs x0, pmicntr_el0 msr pmicntr_el0, x0 - mrs x0, pmicfiltr_el0 + mrs x0, pmicntr_el0 msr pmicfiltr_el0, x0 + mrs x0, pmicfiltr_el0 msr pmzr_el0, x0 /* FEAT_SEBEP Extension. */ - mrs x0, pmecr_el1 msr pmecr_el1, x0 - mrs x0, pmiar_el1 + mrs x0, pmecr_el1 msr pmiar_el1, x0 + mrs x0, pmiar_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d index 1564f530c67..5d74fd7056b 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d @@ -6,20 +6,20 @@ Disassembly of section \.text: 0+ <.*>: +.*: d518a460 msr lorc_el1, x0 .*: d538a460 mrs x0, lorc_el1 +.*: d518a420 msr lorea_el1, x0 .*: d538a420 mrs x0, lorea_el1 +.*: d518a440 msr lorn_el1, x0 .*: d538a440 mrs x0, lorn_el1 +.*: d518a400 msr lorsa_el1, x0 .*: d538a400 mrs x0, lorsa_el1 +.*: d51ecc80 msr icc_ctlr_el3, x0 .*: d53ecc80 mrs x0, icc_ctlr_el3 +.*: d518cca0 msr icc_sre_el1, x0 .*: d538cca0 mrs x0, icc_sre_el1 +.*: d51cc9a0 msr icc_sre_el2, x0 .*: d53cc9a0 mrs x0, icc_sre_el2 +.*: d51ecca0 msr icc_sre_el3, x0 .*: d53ecca0 mrs x0, icc_sre_el3 .*: d53ccb20 mrs x0, ich_vtr_el2 -.*: d518a460 msr lorc_el1, x0 -.*: d518a420 msr lorea_el1, x0 -.*: d518a440 msr lorn_el1, x0 -.*: d518a400 msr lorsa_el1, x0 -.*: d51ecc80 msr icc_ctlr_el3, x0 -.*: d518cca0 msr icc_sre_el1, x0 -.*: d51cc9a0 msr icc_sre_el2, x0 -.*: d51ecca0 msr icc_sre_el3, x0 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s index 94dd85b1a03..8354a44a813 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s @@ -1,22 +1,20 @@ .arch armv8-a+lor -/* Read from system registers. */ +msr lorc_el1, x0 mrs x0, lorc_el1 +msr lorea_el1, x0 mrs x0, lorea_el1 +msr lorn_el1, x0 mrs x0, lorn_el1 +msr lorsa_el1, x0 mrs x0, lorsa_el1 +msr icc_ctlr_el3, x0 mrs x0, icc_ctlr_el3 +msr icc_sre_el1, x0 mrs x0, icc_sre_el1 +msr icc_sre_el2, x0 mrs x0, icc_sre_el2 +msr icc_sre_el3, x0 mrs x0, icc_sre_el3 -mrs x0, ich_vtr_el2 -/* Write to system registers. */ -msr lorc_el1, x0 -msr lorea_el1, x0 -msr lorn_el1, x0 -msr lorsa_el1, x0 -msr icc_ctlr_el3, x0 -msr icc_sre_el1, x0 -msr icc_sre_el2, x0 -msr icc_sre_el3, x0 +mrs x0, ich_vtr_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d index 3f048849836..d93b4c7da40 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d @@ -9,29 +9,29 @@ Disassembly of section \.text: [^:]*: d53803a0 mrs x0, id_dfr1_el1 [^:]*: d53803c0 mrs x0, id_mmfr5_el1 [^:]*: d53802e0 mrs x0, id_isar6_el1 -[^:]*: d5384600 mrs x0, icc_pmr_el1 [^:]*: d5184600 msr icc_pmr_el1, x0 +[^:]*: d5384600 mrs x0, icc_pmr_el1 [^:]*: d538c800 mrs x0, icc_iar0_el1 [^:]*: d518c820 msr icc_eoir0_el1, x0 [^:]*: d538c840 mrs x0, icc_hppir0_el1 -[^:]*: d538c860 mrs x0, icc_bpr0_el1 [^:]*: d518c860 msr icc_bpr0_el1, x0 -[^:]*: d538c880 mrs x0, icc_ap0r0_el1 +[^:]*: d538c860 mrs x0, icc_bpr0_el1 [^:]*: d518c880 msr icc_ap0r0_el1, x0 -[^:]*: d538c8a0 mrs x0, icc_ap0r1_el1 +[^:]*: d538c880 mrs x0, icc_ap0r0_el1 [^:]*: d518c8a0 msr icc_ap0r1_el1, x0 -[^:]*: d538c8c0 mrs x0, icc_ap0r2_el1 +[^:]*: d538c8a0 mrs x0, icc_ap0r1_el1 [^:]*: d518c8c0 msr icc_ap0r2_el1, x0 -[^:]*: d538c8e0 mrs x0, icc_ap0r3_el1 +[^:]*: d538c8c0 mrs x0, icc_ap0r2_el1 [^:]*: d518c8e0 msr icc_ap0r3_el1, x0 -[^:]*: d538c900 mrs x0, icc_ap1r0_el1 +[^:]*: d538c8e0 mrs x0, icc_ap0r3_el1 [^:]*: d518c900 msr icc_ap1r0_el1, x0 -[^:]*: d538c920 mrs x0, icc_ap1r1_el1 +[^:]*: d538c900 mrs x0, icc_ap1r0_el1 [^:]*: d518c920 msr icc_ap1r1_el1, x0 -[^:]*: d538c940 mrs x0, icc_ap1r2_el1 +[^:]*: d538c920 mrs x0, icc_ap1r1_el1 [^:]*: d518c940 msr icc_ap1r2_el1, x0 -[^:]*: d538c960 mrs x0, icc_ap1r3_el1 +[^:]*: d538c940 mrs x0, icc_ap1r2_el1 [^:]*: d518c960 msr icc_ap1r3_el1, x0 +[^:]*: d538c960 mrs x0, icc_ap1r3_el1 [^:]*: d518cb20 msr icc_dir_el1, x0 [^:]*: d538cb60 mrs x0, icc_rpr_el1 [^:]*: d518cba0 msr icc_sgi1r_el1, x0 @@ -40,256 +40,256 @@ Disassembly of section \.text: [^:]*: d538cc00 mrs x0, icc_iar1_el1 [^:]*: d518cc20 msr icc_eoir1_el1, x0 [^:]*: d538cc40 mrs x0, icc_hppir1_el1 -[^:]*: d538cc60 mrs x0, icc_bpr1_el1 [^:]*: d518cc60 msr icc_bpr1_el1, x0 -[^:]*: d538cc80 mrs x0, icc_ctlr_el1 +[^:]*: d538cc60 mrs x0, icc_bpr1_el1 [^:]*: d518cc80 msr icc_ctlr_el1, x0 -[^:]*: d538ccc0 mrs x0, icc_igrpen0_el1 +[^:]*: d538cc80 mrs x0, icc_ctlr_el1 [^:]*: d518ccc0 msr icc_igrpen0_el1, x0 -[^:]*: d538cce0 mrs x0, icc_igrpen1_el1 +[^:]*: d538ccc0 mrs x0, icc_igrpen0_el1 [^:]*: d518cce0 msr icc_igrpen1_el1, x0 -[^:]*: d53cc800 mrs x0, ich_ap0r0_el2 +[^:]*: d538cce0 mrs x0, icc_igrpen1_el1 [^:]*: d51cc800 msr ich_ap0r0_el2, x0 -[^:]*: d53cc820 mrs x0, ich_ap0r1_el2 +[^:]*: d53cc800 mrs x0, ich_ap0r0_el2 [^:]*: d51cc820 msr ich_ap0r1_el2, x0 -[^:]*: d53cc840 mrs x0, ich_ap0r2_el2 +[^:]*: d53cc820 mrs x0, ich_ap0r1_el2 [^:]*: d51cc840 msr ich_ap0r2_el2, x0 -[^:]*: d53cc860 mrs x0, ich_ap0r3_el2 +[^:]*: d53cc840 mrs x0, ich_ap0r2_el2 [^:]*: d51cc860 msr ich_ap0r3_el2, x0 -[^:]*: d53cc900 mrs x0, ich_ap1r0_el2 +[^:]*: d53cc860 mrs x0, ich_ap0r3_el2 [^:]*: d51cc900 msr ich_ap1r0_el2, x0 -[^:]*: d53cc920 mrs x0, ich_ap1r1_el2 +[^:]*: d53cc900 mrs x0, ich_ap1r0_el2 [^:]*: d51cc920 msr ich_ap1r1_el2, x0 -[^:]*: d53cc940 mrs x0, ich_ap1r2_el2 +[^:]*: d53cc920 mrs x0, ich_ap1r1_el2 [^:]*: d51cc940 msr ich_ap1r2_el2, x0 -[^:]*: d53cc960 mrs x0, ich_ap1r3_el2 +[^:]*: d53cc940 mrs x0, ich_ap1r2_el2 [^:]*: d51cc960 msr ich_ap1r3_el2, x0 -[^:]*: d53ccb00 mrs x0, ich_hcr_el2 +[^:]*: d53cc960 mrs x0, ich_ap1r3_el2 [^:]*: d51ccb00 msr ich_hcr_el2, x0 +[^:]*: d53ccb00 mrs x0, ich_hcr_el2 [^:]*: d53ccb40 mrs x0, ich_misr_el2 [^:]*: d53ccb60 mrs x0, ich_eisr_el2 [^:]*: d53ccba0 mrs x0, ich_elrsr_el2 -[^:]*: d53ccbe0 mrs x0, ich_vmcr_el2 [^:]*: d51ccbe0 msr ich_vmcr_el2, x0 -[^:]*: d53ccc00 mrs x0, ich_lr0_el2 +[^:]*: d53ccbe0 mrs x0, ich_vmcr_el2 [^:]*: d51ccc00 msr ich_lr0_el2, x0 -[^:]*: d53ccc20 mrs x0, ich_lr1_el2 +[^:]*: d53ccc00 mrs x0, ich_lr0_el2 [^:]*: d51ccc20 msr ich_lr1_el2, x0 -[^:]*: d53ccc40 mrs x0, ich_lr2_el2 +[^:]*: d53ccc20 mrs x0, ich_lr1_el2 [^:]*: d51ccc40 msr ich_lr2_el2, x0 -[^:]*: d53ccc60 mrs x0, ich_lr3_el2 +[^:]*: d53ccc40 mrs x0, ich_lr2_el2 [^:]*: d51ccc60 msr ich_lr3_el2, x0 -[^:]*: d53ccc80 mrs x0, ich_lr4_el2 +[^:]*: d53ccc60 mrs x0, ich_lr3_el2 [^:]*: d51ccc80 msr ich_lr4_el2, x0 -[^:]*: d53ccca0 mrs x0, ich_lr5_el2 +[^:]*: d53ccc80 mrs x0, ich_lr4_el2 [^:]*: d51ccca0 msr ich_lr5_el2, x0 -[^:]*: d53cccc0 mrs x0, ich_lr6_el2 +[^:]*: d53ccca0 mrs x0, ich_lr5_el2 [^:]*: d51cccc0 msr ich_lr6_el2, x0 -[^:]*: d53ccce0 mrs x0, ich_lr7_el2 +[^:]*: d53cccc0 mrs x0, ich_lr6_el2 [^:]*: d51ccce0 msr ich_lr7_el2, x0 -[^:]*: d53ccd00 mrs x0, ich_lr8_el2 +[^:]*: d53ccce0 mrs x0, ich_lr7_el2 [^:]*: d51ccd00 msr ich_lr8_el2, x0 -[^:]*: d53ccd20 mrs x0, ich_lr9_el2 +[^:]*: d53ccd00 mrs x0, ich_lr8_el2 [^:]*: d51ccd20 msr ich_lr9_el2, x0 -[^:]*: d53ccd40 mrs x0, ich_lr10_el2 +[^:]*: d53ccd20 mrs x0, ich_lr9_el2 [^:]*: d51ccd40 msr ich_lr10_el2, x0 -[^:]*: d53ccd60 mrs x0, ich_lr11_el2 +[^:]*: d53ccd40 mrs x0, ich_lr10_el2 [^:]*: d51ccd60 msr ich_lr11_el2, x0 -[^:]*: d53ccd80 mrs x0, ich_lr12_el2 +[^:]*: d53ccd60 mrs x0, ich_lr11_el2 [^:]*: d51ccd80 msr ich_lr12_el2, x0 -[^:]*: d53ccda0 mrs x0, ich_lr13_el2 +[^:]*: d53ccd80 mrs x0, ich_lr12_el2 [^:]*: d51ccda0 msr ich_lr13_el2, x0 -[^:]*: d53ccdc0 mrs x0, ich_lr14_el2 +[^:]*: d53ccda0 mrs x0, ich_lr13_el2 [^:]*: d51ccdc0 msr ich_lr14_el2, x0 -[^:]*: d53ccde0 mrs x0, ich_lr15_el2 +[^:]*: d53ccdc0 mrs x0, ich_lr14_el2 [^:]*: d51ccde0 msr ich_lr15_el2, x0 -[^:]*: d53ecce0 mrs x0, icc_igrpen1_el3 +[^:]*: d53ccde0 mrs x0, ich_lr15_el2 [^:]*: d51ecce0 msr icc_igrpen1_el3, x0 +[^:]*: d53ecce0 mrs x0, icc_igrpen1_el3 [^:]*: d538a4e0 mrs x0, lorid_el1 [^:]*: d5390040 mrs x0, ccsidr2_el1 -[^:]*: d5381220 mrs x0, trfcr_el1 [^:]*: d5181220 msr trfcr_el1, x0 +[^:]*: d5381220 mrs x0, trfcr_el1 [^:]*: d5389ec0 mrs x0, pmmir_el1 -[^:]*: d53c1220 mrs x0, trfcr_el2 [^:]*: d51c1220 msr trfcr_el2, x0 -[^:]*: d53d1220 mrs x0, trfcr_el12 +[^:]*: d53c1220 mrs x0, trfcr_el2 [^:]*: d51d1220 msr trfcr_el12, x0 -[^:]*: d53bd200 mrs x0, amcr_el0 +[^:]*: d53d1220 mrs x0, trfcr_el12 [^:]*: d51bd200 msr amcr_el0, x0 +[^:]*: d53bd200 mrs x0, amcr_el0 [^:]*: d53bd220 mrs x0, amcfgr_el0 [^:]*: d53bd240 mrs x0, amcgcr_el0 -[^:]*: d53bd260 mrs x0, amuserenr_el0 [^:]*: d51bd260 msr amuserenr_el0, x0 -[^:]*: d53bd280 mrs x0, amcntenclr0_el0 +[^:]*: d53bd260 mrs x0, amuserenr_el0 [^:]*: d51bd280 msr amcntenclr0_el0, x0 -[^:]*: d53bd2a0 mrs x0, amcntenset0_el0 +[^:]*: d53bd280 mrs x0, amcntenclr0_el0 [^:]*: d51bd2a0 msr amcntenset0_el0, x0 -[^:]*: d53bd300 mrs x0, amcntenclr1_el0 +[^:]*: d53bd2a0 mrs x0, amcntenset0_el0 [^:]*: d51bd300 msr amcntenclr1_el0, x0 -[^:]*: d53bd320 mrs x0, amcntenset1_el0 +[^:]*: d53bd300 mrs x0, amcntenclr1_el0 [^:]*: d51bd320 msr amcntenset1_el0, x0 -[^:]*: d53bd400 mrs x0, amevcntr00_el0 +[^:]*: d53bd320 mrs x0, amcntenset1_el0 [^:]*: d51bd400 msr amevcntr00_el0, x0 -[^:]*: d53bd420 mrs x0, amevcntr01_el0 +[^:]*: d53bd400 mrs x0, amevcntr00_el0 [^:]*: d51bd420 msr amevcntr01_el0, x0 -[^:]*: d53bd440 mrs x0, amevcntr02_el0 +[^:]*: d53bd420 mrs x0, amevcntr01_el0 [^:]*: d51bd440 msr amevcntr02_el0, x0 -[^:]*: d53bd460 mrs x0, amevcntr03_el0 +[^:]*: d53bd440 mrs x0, amevcntr02_el0 [^:]*: d51bd460 msr amevcntr03_el0, x0 +[^:]*: d53bd460 mrs x0, amevcntr03_el0 [^:]*: d53bd600 mrs x0, amevtyper00_el0 [^:]*: d53bd620 mrs x0, amevtyper01_el0 [^:]*: d53bd640 mrs x0, amevtyper02_el0 [^:]*: d53bd660 mrs x0, amevtyper03_el0 -[^:]*: d53bdc00 mrs x0, amevcntr10_el0 [^:]*: d51bdc00 msr amevcntr10_el0, x0 -[^:]*: d53bdc20 mrs x0, amevcntr11_el0 +[^:]*: d53bdc00 mrs x0, amevcntr10_el0 [^:]*: d51bdc20 msr amevcntr11_el0, x0 -[^:]*: d53bdc40 mrs x0, amevcntr12_el0 +[^:]*: d53bdc20 mrs x0, amevcntr11_el0 [^:]*: d51bdc40 msr amevcntr12_el0, x0 -[^:]*: d53bdc60 mrs x0, amevcntr13_el0 +[^:]*: d53bdc40 mrs x0, amevcntr12_el0 [^:]*: d51bdc60 msr amevcntr13_el0, x0 -[^:]*: d53bdc80 mrs x0, amevcntr14_el0 +[^:]*: d53bdc60 mrs x0, amevcntr13_el0 [^:]*: d51bdc80 msr amevcntr14_el0, x0 -[^:]*: d53bdca0 mrs x0, amevcntr15_el0 +[^:]*: d53bdc80 mrs x0, amevcntr14_el0 [^:]*: d51bdca0 msr amevcntr15_el0, x0 -[^:]*: d53bdcc0 mrs x0, amevcntr16_el0 +[^:]*: d53bdca0 mrs x0, amevcntr15_el0 [^:]*: d51bdcc0 msr amevcntr16_el0, x0 -[^:]*: d53bdce0 mrs x0, amevcntr17_el0 +[^:]*: d53bdcc0 mrs x0, amevcntr16_el0 [^:]*: d51bdce0 msr amevcntr17_el0, x0 -[^:]*: d53bdd00 mrs x0, amevcntr18_el0 +[^:]*: d53bdce0 mrs x0, amevcntr17_el0 [^:]*: d51bdd00 msr amevcntr18_el0, x0 -[^:]*: d53bdd20 mrs x0, amevcntr19_el0 +[^:]*: d53bdd00 mrs x0, amevcntr18_el0 [^:]*: d51bdd20 msr amevcntr19_el0, x0 -[^:]*: d53bdd40 mrs x0, amevcntr110_el0 +[^:]*: d53bdd20 mrs x0, amevcntr19_el0 [^:]*: d51bdd40 msr amevcntr110_el0, x0 -[^:]*: d53bdd60 mrs x0, amevcntr111_el0 +[^:]*: d53bdd40 mrs x0, amevcntr110_el0 [^:]*: d51bdd60 msr amevcntr111_el0, x0 -[^:]*: d53bdd80 mrs x0, amevcntr112_el0 +[^:]*: d53bdd60 mrs x0, amevcntr111_el0 [^:]*: d51bdd80 msr amevcntr112_el0, x0 -[^:]*: d53bdda0 mrs x0, amevcntr113_el0 +[^:]*: d53bdd80 mrs x0, amevcntr112_el0 [^:]*: d51bdda0 msr amevcntr113_el0, x0 -[^:]*: d53bddc0 mrs x0, amevcntr114_el0 +[^:]*: d53bdda0 mrs x0, amevcntr113_el0 [^:]*: d51bddc0 msr amevcntr114_el0, x0 -[^:]*: d53bdde0 mrs x0, amevcntr115_el0 +[^:]*: d53bddc0 mrs x0, amevcntr114_el0 [^:]*: d51bdde0 msr amevcntr115_el0, x0 -[^:]*: d53bde00 mrs x0, amevtyper10_el0 +[^:]*: d53bdde0 mrs x0, amevcntr115_el0 [^:]*: d51bde00 msr amevtyper10_el0, x0 -[^:]*: d53bde20 mrs x0, amevtyper11_el0 +[^:]*: d53bde00 mrs x0, amevtyper10_el0 [^:]*: d51bde20 msr amevtyper11_el0, x0 -[^:]*: d53bde40 mrs x0, amevtyper12_el0 +[^:]*: d53bde20 mrs x0, amevtyper11_el0 [^:]*: d51bde40 msr amevtyper12_el0, x0 -[^:]*: d53bde60 mrs x0, amevtyper13_el0 +[^:]*: d53bde40 mrs x0, amevtyper12_el0 [^:]*: d51bde60 msr amevtyper13_el0, x0 -[^:]*: d53bde80 mrs x0, amevtyper14_el0 +[^:]*: d53bde60 mrs x0, amevtyper13_el0 [^:]*: d51bde80 msr amevtyper14_el0, x0 -[^:]*: d53bdea0 mrs x0, amevtyper15_el0 +[^:]*: d53bde80 mrs x0, amevtyper14_el0 [^:]*: d51bdea0 msr amevtyper15_el0, x0 -[^:]*: d53bdec0 mrs x0, amevtyper16_el0 +[^:]*: d53bdea0 mrs x0, amevtyper15_el0 [^:]*: d51bdec0 msr amevtyper16_el0, x0 -[^:]*: d53bdee0 mrs x0, amevtyper17_el0 +[^:]*: d53bdec0 mrs x0, amevtyper16_el0 [^:]*: d51bdee0 msr amevtyper17_el0, x0 -[^:]*: d53bdf00 mrs x0, amevtyper18_el0 +[^:]*: d53bdee0 mrs x0, amevtyper17_el0 [^:]*: d51bdf00 msr amevtyper18_el0, x0 -[^:]*: d53bdf20 mrs x0, amevtyper19_el0 +[^:]*: d53bdf00 mrs x0, amevtyper18_el0 [^:]*: d51bdf20 msr amevtyper19_el0, x0 -[^:]*: d53bdf40 mrs x0, amevtyper110_el0 +[^:]*: d53bdf20 mrs x0, amevtyper19_el0 [^:]*: d51bdf40 msr amevtyper110_el0, x0 -[^:]*: d53bdf60 mrs x0, amevtyper111_el0 +[^:]*: d53bdf40 mrs x0, amevtyper110_el0 [^:]*: d51bdf60 msr amevtyper111_el0, x0 -[^:]*: d53bdf80 mrs x0, amevtyper112_el0 +[^:]*: d53bdf60 mrs x0, amevtyper111_el0 [^:]*: d51bdf80 msr amevtyper112_el0, x0 -[^:]*: d53bdfa0 mrs x0, amevtyper113_el0 +[^:]*: d53bdf80 mrs x0, amevtyper112_el0 [^:]*: d51bdfa0 msr amevtyper113_el0, x0 -[^:]*: d53bdfc0 mrs x0, amevtyper114_el0 +[^:]*: d53bdfa0 mrs x0, amevtyper113_el0 [^:]*: d51bdfc0 msr amevtyper114_el0, x0 -[^:]*: d53bdfe0 mrs x0, amevtyper115_el0 +[^:]*: d53bdfc0 mrs x0, amevtyper114_el0 [^:]*: d51bdfe0 msr amevtyper115_el0, x0 +[^:]*: d53bdfe0 mrs x0, amevtyper115_el0 [^:]*: d53bd2c0 mrs x0, amcg1idr_el0 [^:]*: d53be0a0 mrs x0, cntpctss_el0 [^:]*: d53be0c0 mrs x0, cntvctss_el0 -[^:]*: d53c1180 mrs x0, hfgrtr_el2 [^:]*: d51c1180 msr hfgrtr_el2, x0 -[^:]*: d53c11a0 mrs x0, hfgwtr_el2 +[^:]*: d53c1180 mrs x0, hfgrtr_el2 [^:]*: d51c11a0 msr hfgwtr_el2, x0 -[^:]*: d53c11c0 mrs x0, hfgitr_el2 +[^:]*: d53c11a0 mrs x0, hfgwtr_el2 [^:]*: d51c11c0 msr hfgitr_el2, x0 -[^:]*: d53c3180 mrs x0, hdfgrtr_el2 +[^:]*: d53c11c0 mrs x0, hfgitr_el2 [^:]*: d51c3180 msr hdfgrtr_el2, x0 -[^:]*: d53c31a0 mrs x0, hdfgwtr_el2 +[^:]*: d53c3180 mrs x0, hdfgrtr_el2 [^:]*: d51c31a0 msr hdfgwtr_el2, x0 -[^:]*: d53c31c0 mrs x0, hafgrtr_el2 +[^:]*: d53c31a0 mrs x0, hdfgwtr_el2 [^:]*: d51c31c0 msr hafgrtr_el2, x0 -[^:]*: d53cd800 mrs x0, amevcntvoff00_el2 +[^:]*: d53c31c0 mrs x0, hafgrtr_el2 [^:]*: d51cd800 msr amevcntvoff00_el2, x0 -[^:]*: d53cd820 mrs x0, amevcntvoff01_el2 +[^:]*: d53cd800 mrs x0, amevcntvoff00_el2 [^:]*: d51cd820 msr amevcntvoff01_el2, x0 -[^:]*: d53cd840 mrs x0, amevcntvoff02_el2 +[^:]*: d53cd820 mrs x0, amevcntvoff01_el2 [^:]*: d51cd840 msr amevcntvoff02_el2, x0 -[^:]*: d53cd860 mrs x0, amevcntvoff03_el2 +[^:]*: d53cd840 mrs x0, amevcntvoff02_el2 [^:]*: d51cd860 msr amevcntvoff03_el2, x0 -[^:]*: d53cd880 mrs x0, amevcntvoff04_el2 +[^:]*: d53cd860 mrs x0, amevcntvoff03_el2 [^:]*: d51cd880 msr amevcntvoff04_el2, x0 -[^:]*: d53cd8a0 mrs x0, amevcntvoff05_el2 +[^:]*: d53cd880 mrs x0, amevcntvoff04_el2 [^:]*: d51cd8a0 msr amevcntvoff05_el2, x0 -[^:]*: d53cd8c0 mrs x0, amevcntvoff06_el2 +[^:]*: d53cd8a0 mrs x0, amevcntvoff05_el2 [^:]*: d51cd8c0 msr amevcntvoff06_el2, x0 -[^:]*: d53cd8e0 mrs x0, amevcntvoff07_el2 +[^:]*: d53cd8c0 mrs x0, amevcntvoff06_el2 [^:]*: d51cd8e0 msr amevcntvoff07_el2, x0 -[^:]*: d53cd900 mrs x0, amevcntvoff08_el2 +[^:]*: d53cd8e0 mrs x0, amevcntvoff07_el2 [^:]*: d51cd900 msr amevcntvoff08_el2, x0 -[^:]*: d53cd920 mrs x0, amevcntvoff09_el2 +[^:]*: d53cd900 mrs x0, amevcntvoff08_el2 [^:]*: d51cd920 msr amevcntvoff09_el2, x0 -[^:]*: d53cd940 mrs x0, amevcntvoff010_el2 +[^:]*: d53cd920 mrs x0, amevcntvoff09_el2 [^:]*: d51cd940 msr amevcntvoff010_el2, x0 -[^:]*: d53cd960 mrs x0, amevcntvoff011_el2 +[^:]*: d53cd940 mrs x0, amevcntvoff010_el2 [^:]*: d51cd960 msr amevcntvoff011_el2, x0 -[^:]*: d53cd980 mrs x0, amevcntvoff012_el2 +[^:]*: d53cd960 mrs x0, amevcntvoff011_el2 [^:]*: d51cd980 msr amevcntvoff012_el2, x0 -[^:]*: d53cd9a0 mrs x0, amevcntvoff013_el2 +[^:]*: d53cd980 mrs x0, amevcntvoff012_el2 [^:]*: d51cd9a0 msr amevcntvoff013_el2, x0 -[^:]*: d53cd9c0 mrs x0, amevcntvoff014_el2 +[^:]*: d53cd9a0 mrs x0, amevcntvoff013_el2 [^:]*: d51cd9c0 msr amevcntvoff014_el2, x0 -[^:]*: d53cd9e0 mrs x0, amevcntvoff015_el2 +[^:]*: d53cd9c0 mrs x0, amevcntvoff014_el2 [^:]*: d51cd9e0 msr amevcntvoff015_el2, x0 -[^:]*: d53cda00 mrs x0, amevcntvoff10_el2 +[^:]*: d53cd9e0 mrs x0, amevcntvoff015_el2 [^:]*: d51cda00 msr amevcntvoff10_el2, x0 -[^:]*: d53cda20 mrs x0, amevcntvoff11_el2 +[^:]*: d53cda00 mrs x0, amevcntvoff10_el2 [^:]*: d51cda20 msr amevcntvoff11_el2, x0 -[^:]*: d53cda40 mrs x0, amevcntvoff12_el2 +[^:]*: d53cda20 mrs x0, amevcntvoff11_el2 [^:]*: d51cda40 msr amevcntvoff12_el2, x0 -[^:]*: d53cda60 mrs x0, amevcntvoff13_el2 +[^:]*: d53cda40 mrs x0, amevcntvoff12_el2 [^:]*: d51cda60 msr amevcntvoff13_el2, x0 -[^:]*: d53cda80 mrs x0, amevcntvoff14_el2 +[^:]*: d53cda60 mrs x0, amevcntvoff13_el2 [^:]*: d51cda80 msr amevcntvoff14_el2, x0 -[^:]*: d53cdaa0 mrs x0, amevcntvoff15_el2 +[^:]*: d53cda80 mrs x0, amevcntvoff14_el2 [^:]*: d51cdaa0 msr amevcntvoff15_el2, x0 -[^:]*: d53cdac0 mrs x0, amevcntvoff16_el2 +[^:]*: d53cdaa0 mrs x0, amevcntvoff15_el2 [^:]*: d51cdac0 msr amevcntvoff16_el2, x0 -[^:]*: d53cdae0 mrs x0, amevcntvoff17_el2 +[^:]*: d53cdac0 mrs x0, amevcntvoff16_el2 [^:]*: d51cdae0 msr amevcntvoff17_el2, x0 -[^:]*: d53cdb00 mrs x0, amevcntvoff18_el2 +[^:]*: d53cdae0 mrs x0, amevcntvoff17_el2 [^:]*: d51cdb00 msr amevcntvoff18_el2, x0 -[^:]*: d53cdb20 mrs x0, amevcntvoff19_el2 +[^:]*: d53cdb00 mrs x0, amevcntvoff18_el2 [^:]*: d51cdb20 msr amevcntvoff19_el2, x0 -[^:]*: d53cdb40 mrs x0, amevcntvoff110_el2 +[^:]*: d53cdb20 mrs x0, amevcntvoff19_el2 [^:]*: d51cdb40 msr amevcntvoff110_el2, x0 -[^:]*: d53cdb60 mrs x0, amevcntvoff111_el2 +[^:]*: d53cdb40 mrs x0, amevcntvoff110_el2 [^:]*: d51cdb60 msr amevcntvoff111_el2, x0 -[^:]*: d53cdb80 mrs x0, amevcntvoff112_el2 +[^:]*: d53cdb60 mrs x0, amevcntvoff111_el2 [^:]*: d51cdb80 msr amevcntvoff112_el2, x0 -[^:]*: d53cdba0 mrs x0, amevcntvoff113_el2 +[^:]*: d53cdb80 mrs x0, amevcntvoff112_el2 [^:]*: d51cdba0 msr amevcntvoff113_el2, x0 -[^:]*: d53cdbc0 mrs x0, amevcntvoff114_el2 +[^:]*: d53cdba0 mrs x0, amevcntvoff113_el2 [^:]*: d51cdbc0 msr amevcntvoff114_el2, x0 -[^:]*: d53cdbe0 mrs x0, amevcntvoff115_el2 +[^:]*: d53cdbc0 mrs x0, amevcntvoff114_el2 [^:]*: d51cdbe0 msr amevcntvoff115_el2, x0 -[^:]*: d53ce0c0 mrs x0, cntpoff_el2 +[^:]*: d53cdbe0 mrs x0, amevcntvoff115_el2 [^:]*: d51ce0c0 msr cntpoff_el2, x0 -[^:]*: d5389920 mrs x0, pmsnevfr_el1 +[^:]*: d53ce0c0 mrs x0, cntpoff_el2 [^:]*: d5189920 msr pmsnevfr_el1, x0 -[^:]*: d53c1240 mrs x0, hcrx_el2 +[^:]*: d5389920 mrs x0, pmsnevfr_el1 [^:]*: d51c1240 msr hcrx_el2, x0 -[^:]*: d538d0c0 mrs x0, rcwmask_el1 +[^:]*: d53c1240 mrs x0, hcrx_el2 [^:]*: d518d0c0 msr rcwmask_el1, x0 -[^:]*: d538d060 mrs x0, rcwsmask_el1 +[^:]*: d538d0c0 mrs x0, rcwmask_el1 [^:]*: d518d060 msr rcwsmask_el1, x0 +[^:]*: d538d060 mrs x0, rcwsmask_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s index bf555d23b82..04bd30d08d1 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s @@ -7,8 +7,8 @@ .endm .macro rwreg, name - mrs x0, \name msr \name, x0 + mrs x0, \name .endm roreg id_dfr1_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sysreg.d index 90b5be3cabf..6dfad54a72c 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.d @@ -24,12 +24,12 @@ Disassembly of section \.text: .*: d5380260 mrs x0, id_isar3_el1 .*: d5380280 mrs x0, id_isar4_el1 .*: d53802a0 mrs x0, id_isar5_el1 -.*: d538cf00 mrs x0, s3_0_c12_c15_0 -.*: d5384b00 mrs x0, s3_0_c4_c11_0 -.*: d5184b00 msr s3_0_c4_c11_0, x0 -.*: d5310300 mrs x0, trcstatr -.*: d5110300 msr trcstatr, x0 .*: d5380640 mrs x0, id_aa64isar2_el1 .*: d538065e mrs x30, id_aa64isar2_el1 .*: d5380660 mrs x0, id_aa64isar3_el1 .*: d538067e mrs x30, id_aa64isar3_el1 +.*: d538cf00 mrs x0, s3_0_c12_c15_0 +.*: d5184b00 msr s3_0_c4_c11_0, x0 +.*: d5384b00 mrs x0, s3_0_c4_c11_0 +.*: d5110300 msr trcstatr, x0 +.*: d5310300 mrs x0, trcstatr diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.s b/gas/testsuite/gas/aarch64/sysreg/sysreg.s index a3f5b793620..998f31596bd 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.s @@ -24,15 +24,15 @@ mrs x0, id_isar4_el1 mrs x0, id_isar5_el1 - mrs x0, s3_0_c12_c15_0 - mrs x0, s3_0_c4_c11_0 - msr s3_0_c4_c11_0, x0 - - mrs x0, s2_1_c0_c3_0 - msr s2_1_c0_c3_0, x0 - mrs x0, id_aa64isar2_el1 mrs x30, id_aa64isar2_el1 mrs x0, id_aa64isar3_el1 mrs x30, id_aa64isar3_el1 + + mrs x0, s3_0_c12_c15_0 + msr s3_0_c4_c11_0, x0 + mrs x0, s3_0_c4_c11_0 + + msr s2_1_c0_c3_0, x0 + mrs x0, s2_1_c0_c3_0 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg128.d b/gas/testsuite/gas/aarch64/sysreg/sysreg128.d index cb895c64503..2998c7b79a2 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg128.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg128.d @@ -6,23 +6,23 @@ Disassembly of section \.text: 0+ <\.text>: -[^:]*: d5787402 mrrs x2, x3, par_el1 [^:]*: d5587402 msrr par_el1, x2, x3 -[^:]*: d578d0c2 mrrs x2, x3, rcwmask_el1 +[^:]*: d5787402 mrrs x2, x3, par_el1 [^:]*: d558d0c2 msrr rcwmask_el1, x2, x3 -[^:]*: d578d062 mrrs x2, x3, rcwsmask_el1 +[^:]*: d578d0c2 mrrs x2, x3, rcwmask_el1 [^:]*: d558d062 msrr rcwsmask_el1, x2, x3 -[^:]*: d5782002 mrrs x2, x3, ttbr0_el1 +[^:]*: d578d062 mrrs x2, x3, rcwsmask_el1 [^:]*: d5582002 msrr ttbr0_el1, x2, x3 -[^:]*: d57d2002 mrrs x2, x3, ttbr0_el12 +[^:]*: d5782002 mrrs x2, x3, ttbr0_el1 [^:]*: d55d2002 msrr ttbr0_el12, x2, x3 -[^:]*: d57c2002 mrrs x2, x3, ttbr0_el2 +[^:]*: d57d2002 mrrs x2, x3, ttbr0_el12 [^:]*: d55c2002 msrr ttbr0_el2, x2, x3 -[^:]*: d5782022 mrrs x2, x3, ttbr1_el1 +[^:]*: d57c2002 mrrs x2, x3, ttbr0_el2 [^:]*: d5582022 msrr ttbr1_el1, x2, x3 -[^:]*: d57d2022 mrrs x2, x3, ttbr1_el12 +[^:]*: d5782022 mrrs x2, x3, ttbr1_el1 [^:]*: d55d2022 msrr ttbr1_el12, x2, x3 -[^:]*: d57c2022 mrrs x2, x3, ttbr1_el2 +[^:]*: d57d2022 mrrs x2, x3, ttbr1_el12 [^:]*: d55c2022 msrr ttbr1_el2, x2, x3 -[^:]*: d57c2102 mrrs x2, x3, vttbr_el2 -[^:]*: d55c2102 msrr vttbr_el2, x2, x3 \ No newline at end of file +[^:]*: d57c2022 mrrs x2, x3, ttbr1_el2 +[^:]*: d55c2102 msrr vttbr_el2, x2, x3 +[^:]*: d57c2102 mrrs x2, x3, vttbr_el2 \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg128.s b/gas/testsuite/gas/aarch64/sysreg/sysreg128.s index 09c9dace9b5..ee1d7cda3fa 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg128.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg128.s @@ -1,8 +1,8 @@ .arch armv9.4-a+d128+the .macro rwreg128, name - mrrs x2, x3, \name msrr \name, x2, x3 + mrrs x2, x3, \name .endm rwreg128 par_el1 From patchwork Tue Feb 27 10:59:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthieu Longo X-Patchwork-Id: 207134 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2619403dyb; Tue, 27 Feb 2024 03:00:36 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXIUwSIwkgx/mYG8ocCFdVJwwcfpalD6/L2hkqSTqHEC1PSP+RcZ9DV19YEcovllX8lidJnFKABDktCEBms0/1nUnhvAQ== X-Google-Smtp-Source: AGHT+IFfyeWeTB5CbHohCQnjnq4XyJ1ATckMYupj3+nqKAudFrH+Uu9XoFnLNuizDGR09U/dY+UB X-Received: by 2002:ac8:5a04:0:b0:42e:a11e:ed62 with SMTP id n4-20020ac85a04000000b0042ea11eed62mr879260qta.25.1709031636538; Tue, 27 Feb 2024 03:00:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709031636; cv=pass; d=google.com; s=arc-20160816; b=S9K3FcjqSw8BESJGKwUrvuk70gYf+j01ADFiC8MGyxNFnb5lS1i3XVQ5eXTkrGDcHE mH5+JWIcOCYGF9RcJqzficowonaYh3vyV6itEHTQBKbu3g9wP45ovlxBjq/zqdD1FoB6 ezBw6foURMo2tLr5l1ZwlHc8JDcQ21qLlLWpHaIPrjW63A4c/yO3D5cG5/GB1h8f6v7x spNkJEo9mP4UlDpDDMyiZpDFNMSDopWHKOp2kDdpQ8kZhwl7hYbAK2hS+fkIkvEIggIN I0YbBTstu9fkfgAgam7WdKlD5qfnED1Zz0/ARztsj6sS1gYDIkz/gxJRZ8ePXh24u5By YRpA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=NovTO1LLw7YLdIg/DGEwDVjRdm5/OFzrFtb2U1VUNvM=; fh=bcbSBk6kL0yCjqxjmEWwFzJxBMxjhnM2jUxTrAFje1Y=; b=Vtm8uw/8FWhxRSOW29f/J+a1pWfIucpdfxTpNoKjOhIq4jVzTHGHnQDHN8Eb6YaK2N AUWtDgEmQkth5VQqYcSRPx2GlO6zYPs/Zvi2aPSgFlL4/uC4Lm32xf5WNStQJvLScr7k oxK9yBO0xd5OKnEyv+74V7NP7qLdoXWzN6XeyRbUJD35mRyYTSqpLFpIQ6ZNqyIlu8ar F7Ym/oDYWhrKWDj8cg5C34i2PxP5o5eILqNGnws8CizEZBOx4/uCfAXDQ81ndki/l6Cr 23le4iZNLW2cN9wL3zzdS7PQwcS51j8cii9CS4dXyfyg69u7jfej/megOCDEewSKXKi3 pcDQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id l13-20020a05622a174d00b0042e8c831342si3349553qtk.618.2024.02.27.03.00.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 03:00:36 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7C286385840B for ; Tue, 27 Feb 2024 11:00:35 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat-cam5.arm.com [217.140.106.53]) by sourceware.org (Postfix) with ESMTPS id D702E3858438 for ; Tue, 27 Feb 2024 11:00:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D702E3858438 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D702E3858438 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.106.53 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709031609; cv=none; b=IQaWSLFtNP00Q0LA5wOJ0ZhvpZtMg9BNCXYZZcIKmzQiQx70n0B1Rb0iTqQ435acT0bafav2oq7YoEHAzcyiS2zUbYh9I29X+pnrKI2KJFd+eWiUmu268sTpE2Ywd2x1yBKfCWkHI69R4cs9j25emC8KR4KyKrqyU2LI7/BS9Lw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709031609; c=relaxed/simple; bh=FTn24p+hkFsoJXwfGStaR1GznbVZJ1WvQukp4eHzRTg=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=VW4gL9mM7zy6WbgD1mijQRMO/DKcOhmVFsuDdGmR3WhLqhBoZkNX8r7U4eScvPSiBkzmKu5ovSV3aeUWPZDoQ+HTQ2hxv3uQLTx3Ljbpo+zZjDfItW+XcLooJzlTF8QwhkApvyIG5MiZCdsuKme+twAwC8bU/e5z7cmITKGinS4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from e129756.cambridge.arm.com (e129756.arm.com [10.2.78.55]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id 41RAxnZS030743; Tue, 27 Feb 2024 10:59:58 GMT From: Matthieu Longo To: binutils@sourceware.org Cc: Richard Earnshaw , Nick Clifton , Matthieu Longo Subject: [PATCH v1 4/4] aarch64: testsuite: share test utils macros and use them Date: Tue, 27 Feb 2024 10:59:17 +0000 Message-Id: <20240227105917.295899-5-matthieu.longo@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227105917.295899-1-matthieu.longo@arm.com> References: <20240227105917.295899-1-matthieu.longo@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, KHOP_HELO_FCRDNS, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792049557220765671 X-GMAIL-MSGID: 1792049557220765671 This patch rewrites assembly tests to use utils macros declared in sysreg-test-utils.inc. Some tests were adapted to use the new macro rw_sys_reg. --- .../aarch64/sysreg/armv8_9-a-sysregs-bad.d | 2 +- .../aarch64/sysreg/armv8_9-a-sysregs-bad.l | 90 ++++- .../gas/aarch64/sysreg/armv8_9-a-sysregs.d | 3 +- .../gas/aarch64/sysreg/armv8_9-a-sysregs.s | 139 +++---- .../gas/aarch64/sysreg/illegal-sysreg-3.d | 2 +- .../gas/aarch64/sysreg/illegal-sysreg-4.d | 2 +- gas/testsuite/gas/aarch64/sysreg/sysreg-1.d | 2 + gas/testsuite/gas/aarch64/sysreg/sysreg-1.s | 223 ++++++------ gas/testsuite/gas/aarch64/sysreg/sysreg-2.d | 3 +- gas/testsuite/gas/aarch64/sysreg/sysreg-2.s | 47 ++- gas/testsuite/gas/aarch64/sysreg/sysreg-3.d | 3 +- gas/testsuite/gas/aarch64/sysreg/sysreg-3.s | 25 +- gas/testsuite/gas/aarch64/sysreg/sysreg-6.d | 2 + gas/testsuite/gas/aarch64/sysreg/sysreg-6.s | 7 +- gas/testsuite/gas/aarch64/sysreg/sysreg-7.d | 2 + gas/testsuite/gas/aarch64/sysreg/sysreg-7.s | 32 +- gas/testsuite/gas/aarch64/sysreg/sysreg-8.d | 2 + gas/testsuite/gas/aarch64/sysreg/sysreg-8.s | 339 +++++++++--------- .../gas/aarch64/sysreg/sysreg-test-utils.inc | 32 ++ gas/testsuite/gas/aarch64/sysreg/sysreg.d | 6 +- gas/testsuite/gas/aarch64/sysreg/sysreg.s | 63 ++-- gas/testsuite/gas/aarch64/sysreg/sysreg128.d | 42 +-- gas/testsuite/gas/aarch64/sysreg/sysreg128.s | 27 +- 23 files changed, 576 insertions(+), 519 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sysreg/sysreg-test-utils.inc diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.d b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.d index 2471b6b52c3..1160ec02ff7 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.d @@ -1,3 +1,3 @@ -#as: -march=armv8.8-a #source: armv8_9-a-sysregs.s +#as: -march=armv8.8-a -I$srcdir/$subdir #error_output: armv8_9-a-sysregs-bad.l diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l index d98c2ed573a..05431cc501b 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l @@ -1,90 +1,170 @@ .*: Assembler messages: .*: Error: selected processor does not support system register name 'pmsdsfr_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmsdsfr_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'erxgsr_el1' .*: Error: selected processor does not support system register name 'sctlr2_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'sctlr2_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'sctlr2_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'sctlr2_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'sctlr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'sctlr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'sctlr2_el3' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'sctlr2_el3' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'hdfgrtr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'hdfgrtr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'hdfgwtr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'hdfgwtr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'hfgrtr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'hfgrtr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'hfgwtr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'hfgwtr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pfar_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pfar_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pfar_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pfar_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pfar_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pfar_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 's1e1a' .*: Error: selected processor does not support system register name 's1e2a' .*: Error: selected processor does not support system register name 's1e3a' .*: Error: selected processor does not support system register name 'amair2_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'amair2_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'amair2_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'amair2_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'amair2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'amair2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'amair2_el3' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'amair2_el3' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mair2_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mair2_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mair2_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mair2_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mair2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mair2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mair2_el3' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mair2_el3' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pir_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pir_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pir_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pir_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pir_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pir_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pir_el3' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pir_el3' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pire0_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pire0_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pire0_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pire0_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pire0_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pire0_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 's2pir_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 's2pir_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'por_el0' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'por_el0' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'por_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'por_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'por_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'por_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'por_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'por_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'por_el3' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'por_el3' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 's2por_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 's2por_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'tcr2_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'tcr2_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'tcr2_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'tcr2_el12' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'tcr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'tcr2_el2' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mdselr_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mdselr_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmuacr_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmuacr_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmccntsvr_el1' .*: Error: selected processor does not support system register name 'pmicntsvr_el1' .*: Error: selected processor does not support system register name 'pmsscr_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmsscr_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmevcntsvr0_el1' .*: Error: selected processor does not support system register name 'pmevcntsvr10_el1' .*: Error: selected processor does not support system register name 'pmevcntsvr11_el1' @@ -116,11 +196,19 @@ .*: Error: selected processor does not support system register name 'pmevcntsvr8_el1' .*: Error: selected processor does not support system register name 'pmevcntsvr9_el1' .*: Error: selected processor does not support system register name 'pmicntr_el0' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmicntr_el0' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmicfiltr_el0' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmicfiltr_el0' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmzr_el0' .*: Error: selected processor does not support system register name 'pmecr_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmecr_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmiar_el1' -.*: Error: selected processor does not support system register name 'pmiar_el1' \ No newline at end of file +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'pmiar_el1' +.*: Info: macro invoked from here \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d index ac32b80b40c..9913c2be6d3 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d @@ -1,4 +1,5 @@ -#as: -march=armv8.9-a +#source: armv8_9-a-sysregs.s +#as: -march=armv8.9-a -I$srcdir/$subdir #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s index bf9019c9ac8..318d8bb9097 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s @@ -1,32 +1,23 @@ - msr PMSDSFR_EL1, x3 - mrs x3, PMSDSFR_EL1 + .include "sysreg-test-utils.inc" + +.text + rw_sys_reg sys_reg=PMSDSFR_EL1 xreg=x3 r=1 w=1 mrs x0, ERXGSR_EL1 - msr SCTLR2_EL1, x3 - mrs x3, SCTLR2_EL1 - msr SCTLR2_EL12, x3 - mrs x3, SCTLR2_EL12 - msr SCTLR2_EL2, x3 - mrs x3, SCTLR2_EL2 - msr SCTLR2_EL3, x3 - mrs x3, SCTLR2_EL3 - - msr HDFGRTR2_EL2, x3 - mrs x3, HDFGRTR2_EL2 - msr HDFGWTR2_EL2, x3 - mrs x3, HDFGWTR2_EL2 - msr HFGRTR2_EL2, x3 - mrs x3, HFGRTR2_EL2 - msr HFGWTR2_EL2, x3 - mrs x3, HFGWTR2_EL2 - - msr PFAR_EL1, x0 - mrs x0, PFAR_EL1 - msr PFAR_EL2, x0 - mrs x0, PFAR_EL2 - msr PFAR_EL12, x0 - mrs x0, PFAR_EL12 + rw_sys_reg sys_reg=SCTLR2_EL1 xreg=x3 r=1 w=1 + rw_sys_reg sys_reg=SCTLR2_EL12 xreg=x3 r=1 w=1 + rw_sys_reg sys_reg=SCTLR2_EL2 xreg=x3 r=1 w=1 + rw_sys_reg sys_reg=SCTLR2_EL3 xreg=x3 r=1 w=1 + + rw_sys_reg sys_reg=HDFGRTR2_EL2 xreg=x3 r=1 w=1 + rw_sys_reg sys_reg=HDFGWTR2_EL2 xreg=x3 r=1 w=1 + rw_sys_reg sys_reg=HFGRTR2_EL2 xreg=x3 r=1 w=1 + rw_sys_reg sys_reg=HFGWTR2_EL2 xreg=x3 r=1 w=1 + + rw_sys_reg sys_reg=PFAR_EL1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=PFAR_EL2 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=PFAR_EL12 xreg=x0 r=1 w=1 /* AT. */ at s1e1a, x1 @@ -34,80 +25,52 @@ at s1e3a, x5 /* FEAT_AIE. */ - msr amair2_el1, x0 - mrs x0, amair2_el1 - msr amair2_el12, x0 - mrs x0, amair2_el12 - msr amair2_el2, x0 - mrs x0, amair2_el2 - msr amair2_el3, x0 - mrs x0, amair2_el3 - msr mair2_el1, x0 - mrs x0, mair2_el1 - msr mair2_el12, x0 - mrs x0, mair2_el12 - msr mair2_el2, x0 - mrs x0, mair2_el2 - msr mair2_el3, x0 - mrs x0, mair2_el3 + rw_sys_reg sys_reg=amair2_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=amair2_el12 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=amair2_el2 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=amair2_el3 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=mair2_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=mair2_el12 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=mair2_el2 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=mair2_el3 xreg=x0 r=1 w=1 /* FEAT_S1PIE. */ - msr pir_el1, x0 - mrs x0, pir_el1 - msr pir_el12, x0 - mrs x0, pir_el12 - msr pir_el2, x0 - mrs x0, pir_el2 - msr pir_el3, x0 - mrs x0, pir_el3 - msr pire0_el1, x0 - mrs x0, pire0_el1 - msr pire0_el12, x0 - mrs x0, pire0_el12 - msr pire0_el2, x0 - mrs x0, pire0_el2 + rw_sys_reg sys_reg=pir_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=pir_el12 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=pir_el2 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=pir_el3 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=pire0_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=pire0_el12 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=pire0_el2 xreg=x0 r=1 w=1 /* FEAT_S2PIE. */ - msr s2pir_el2, x0 - mrs x0, s2pir_el2 + rw_sys_reg sys_reg=s2pir_el2 xreg=x0 r=1 w=1 /* FEAT_S1POE. */ - msr por_el0, x0 - mrs x0, por_el0 - msr por_el1, x0 - mrs x0, por_el1 - msr por_el12, x0 - mrs x0, por_el12 - msr por_el2, x0 - mrs x0, por_el2 - msr por_el3, x0 - mrs x0, por_el3 + rw_sys_reg sys_reg=por_el0 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=por_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=por_el12 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=por_el2 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=por_el3 xreg=x0 r=1 w=1 /* FEAT_S21POE. */ - msr s2por_el1, x0 - mrs x0, s2por_el1 + rw_sys_reg sys_reg=s2por_el1 xreg=x0 r=1 w=1 /* FEAT_TCR2. */ - msr tcr2_el1, x0 - mrs x0, tcr2_el1 - msr tcr2_el12, x0 - mrs x0, tcr2_el12 - msr tcr2_el2, x0 - mrs x0, tcr2_el2 + rw_sys_reg sys_reg=tcr2_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=tcr2_el12 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=tcr2_el2 xreg=x0 r=1 w=1 /* FEAT_DEBUGv8p9 Extension. */ - msr mdselr_el1, x0 - mrs x0, mdselr_el1 + rw_sys_reg sys_reg=mdselr_el1 xreg=x0 r=1 w=1 /* FEAT_PMUv3p9 Extension. */ - msr pmuacr_el1, x0 - mrs x0, pmuacr_el1 + rw_sys_reg sys_reg=pmuacr_el1 xreg=x0 r=1 w=1 /* FEAT_PMUv3_SS Extension. */ mrs x0, pmccntsvr_el1 mrs x0, pmicntsvr_el1 - msr pmsscr_el1, x0 - mrs x0, pmsscr_el1 + rw_sys_reg sys_reg=pmsscr_el1 xreg=x0 r=1 w=1 mrs x0, pmevcntsvr0_el1 mrs x0, pmevcntsvr10_el1 mrs x0, pmevcntsvr11_el1 @@ -140,14 +103,10 @@ mrs x0, pmevcntsvr9_el1 /* FEAT_PMUv3_ICNTR Extension. */ - msr pmicntr_el0, x0 - mrs x0, pmicntr_el0 - msr pmicfiltr_el0, x0 - mrs x0, pmicfiltr_el0 + rw_sys_reg sys_reg=pmicntr_el0 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=pmicfiltr_el0 xreg=x0 r=1 w=1 msr pmzr_el0, x0 /* FEAT_SEBEP Extension. */ - msr pmecr_el1, x0 - mrs x0, pmecr_el1 - msr pmiar_el1, x0 - mrs x0, pmiar_el1 + rw_sys_reg sys_reg=pmecr_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=pmiar_el1 xreg=x0 r=1 w=1 diff --git a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-3.d b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-3.d index 932eb542431..6918395a9ab 100644 --- a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-3.d +++ b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-3.d @@ -1,3 +1,3 @@ -#as: -march=armv8-a #source: sysreg-3.s +#as: -march=armv8-a -I$srcdir/$subdir #error_output: illegal-sysreg-3.l diff --git a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4.d index e1815665d96..34dd4e4ac48 100644 --- a/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4.d +++ b/gas/testsuite/gas/aarch64/sysreg/illegal-sysreg-4.d @@ -1,3 +1,3 @@ -#as: -march=armv8-a #source: sysreg-4.s +#as: -march=armv8-a #error_output: illegal-sysreg-4.l diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d index fb9991d1116..cecb1ad88ee 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d @@ -1,3 +1,5 @@ +#source: sysreg-1.s +#as: -I$srcdir/$subdir #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-1.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-1.s index 82a86d38fb4..16d8f931403 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-1.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-1.s @@ -19,111 +19,104 @@ along with this program; see the file COPYING3. If not, see . */ - .macro rw_sys_reg sys_reg xreg r w - .ifc \w, 1 - msr \sys_reg, \xreg - .endif - .ifc \r, 1 - mrs \xreg, \sys_reg - .endif - .endm + .include "sysreg-test-utils.inc" .text - rw_sys_reg sys_reg=id_aa64afr0_el1 xreg=x7 r=1 w=0 - rw_sys_reg sys_reg=id_aa64afr1_el1 xreg=x7 r=1 w=0 - rw_sys_reg sys_reg=mvfr2_el1 xreg=x7 r=1 w=0 - rw_sys_reg sys_reg=dlr_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=dspsr_el0 xreg=x7 r=1 w=1 - - rw_sys_reg sys_reg=sder32_el3 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=mdcr_el3 xreg=x7 r=1 w=1 - - rw_sys_reg sys_reg=mdccint_el1 xreg=x7 r=1 w=1 - - rw_sys_reg sys_reg=dbgvcr32_el2 xreg=x7 r=1 w=1 - - rw_sys_reg sys_reg=fpexc32_el2 xreg=x7 r=1 w=1 - - rw_sys_reg sys_reg=teecr32_el1 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=teehbr32_el1 xreg=x7 r=1 w=1 - - rw_sys_reg sys_reg=cntp_tval_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=cntp_ctl_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=cntp_cval_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=cntps_tval_el1 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=cntps_ctl_el1 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=cntps_cval_el1 xreg=x7 r=1 w=1 - - rw_sys_reg sys_reg=pmccntr_el0 xreg=x7 r=1 w=1 - - rw_sys_reg sys_reg=pmevcntr0_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr1_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr2_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr3_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr4_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr5_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr6_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr7_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr8_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr9_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr10_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr11_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr12_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr13_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr14_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr15_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr16_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr17_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr18_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr19_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr20_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr21_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr22_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr23_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr24_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr25_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr26_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr27_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr28_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr29_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevcntr30_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper0_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper1_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper2_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper3_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper4_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper5_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper6_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper7_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper8_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper9_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper10_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper11_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper12_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper13_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper14_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper15_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper16_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper17_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper18_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper19_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper20_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper21_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper22_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper23_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper24_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper25_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper26_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper27_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper28_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper29_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmevtyper30_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=pmccfiltr_el0 xreg=x7 r=1 w=1 - - rw_sys_reg sys_reg=tpidrro_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=tpidr_el0 xreg=x7 r=1 w=1 - rw_sys_reg sys_reg=cntfrq_el0 xreg=x7 r=1 w=1 + rw_sys_reg sys_reg=id_aa64afr0_el1 xreg=x7 w=0 + rw_sys_reg sys_reg=id_aa64afr1_el1 xreg=x7 w=0 + rw_sys_reg sys_reg=mvfr2_el1 xreg=x7 w=0 + rw_sys_reg sys_reg=dlr_el0 xreg=x7 + rw_sys_reg sys_reg=dspsr_el0 xreg=x7 + + rw_sys_reg sys_reg=sder32_el3 xreg=x7 + rw_sys_reg sys_reg=mdcr_el3 xreg=x7 + + rw_sys_reg sys_reg=mdccint_el1 xreg=x7 + + rw_sys_reg sys_reg=dbgvcr32_el2 xreg=x7 + + rw_sys_reg sys_reg=fpexc32_el2 xreg=x7 + + rw_sys_reg sys_reg=teecr32_el1 xreg=x7 + rw_sys_reg sys_reg=teehbr32_el1 xreg=x7 + + rw_sys_reg sys_reg=cntp_tval_el0 xreg=x7 + rw_sys_reg sys_reg=cntp_ctl_el0 xreg=x7 + rw_sys_reg sys_reg=cntp_cval_el0 xreg=x7 + rw_sys_reg sys_reg=cntps_tval_el1 xreg=x7 + rw_sys_reg sys_reg=cntps_ctl_el1 xreg=x7 + rw_sys_reg sys_reg=cntps_cval_el1 xreg=x7 + + rw_sys_reg sys_reg=pmccntr_el0 xreg=x7 + + rw_sys_reg sys_reg=pmevcntr0_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr1_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr2_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr3_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr4_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr5_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr6_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr7_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr8_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr9_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr10_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr11_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr12_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr13_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr14_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr15_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr16_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr17_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr18_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr19_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr20_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr21_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr22_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr23_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr24_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr25_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr26_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr27_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr28_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr29_el0 xreg=x7 + rw_sys_reg sys_reg=pmevcntr30_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper0_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper1_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper2_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper3_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper4_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper5_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper6_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper7_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper8_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper9_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper10_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper11_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper12_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper13_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper14_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper15_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper16_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper17_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper18_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper19_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper20_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper21_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper22_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper23_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper24_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper25_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper26_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper27_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper28_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper29_el0 xreg=x7 + rw_sys_reg sys_reg=pmevtyper30_el0 xreg=x7 + rw_sys_reg sys_reg=pmccfiltr_el0 xreg=x7 + + rw_sys_reg sys_reg=tpidrro_el0 xreg=x7 + rw_sys_reg sys_reg=tpidr_el0 xreg=x7 + rw_sys_reg sys_reg=cntfrq_el0 xreg=x7 // // Macros to generate MRS and MSR with all the implementation defined @@ -156,19 +149,19 @@ all_imple_defined 0, 7 .noaltmacro - rw_sys_reg sys_reg=dbgdtr_el0 xreg=x15 r=1 w=1 - rw_sys_reg sys_reg=dbgdtrrx_el0 xreg=x15 r=1 w=0 + rw_sys_reg sys_reg=dbgdtr_el0 xreg=x15 + rw_sys_reg sys_reg=dbgdtrrx_el0 xreg=x15 w=0 - rw_sys_reg sys_reg=rmr_el1 xreg=x15 r=1 w=1 - rw_sys_reg sys_reg=rmr_el2 xreg=x15 r=1 w=1 - rw_sys_reg sys_reg=rmr_el3 xreg=x15 r=1 w=1 + rw_sys_reg sys_reg=rmr_el1 xreg=x15 + rw_sys_reg sys_reg=rmr_el2 xreg=x15 + rw_sys_reg sys_reg=rmr_el3 xreg=x15 - rw_sys_reg sys_reg=spsr_el1 xreg=x15 r=1 w=1 - rw_sys_reg sys_reg=spsr_el2 xreg=x15 r=1 w=1 - rw_sys_reg sys_reg=spsr_el3 xreg=x15 r=1 w=1 + rw_sys_reg sys_reg=spsr_el1 xreg=x15 + rw_sys_reg sys_reg=spsr_el2 xreg=x15 + rw_sys_reg sys_reg=spsr_el3 xreg=x15 - rw_sys_reg sys_reg=s0_0_C0_C0_0 xreg=x15 r=1 w=1 - rw_sys_reg sys_reg=s1_7_C15_C15_7 xreg=x27 r=1 w=1 - rw_sys_reg sys_reg=s2_4_C6_C8_0 xreg=x14 r=1 w=1 - rw_sys_reg sys_reg=s1_2_C14_C4_2 xreg=x4 r=1 w=1 - rw_sys_reg sys_reg=s0_1_C13_C1_3 xreg=x7 r=1 w=1 + rw_sys_reg sys_reg=s0_0_C0_C0_0 xreg=x15 + rw_sys_reg sys_reg=s1_7_C15_C15_7 xreg=x27 + rw_sys_reg sys_reg=s2_4_C6_C8_0 xreg=x14 + rw_sys_reg sys_reg=s1_2_C14_C4_2 xreg=x4 + rw_sys_reg sys_reg=s0_1_C13_C1_3 xreg=x7 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d index 0a3a0c7d6b4..1845902137e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-2.d @@ -1,5 +1,6 @@ +#source: sysreg-2.s +#as: -march=armv8.2-a+profile -I$srcdir/$subdir #objdump: -dr -#as: -march=armv8.2-a+profile .*: file .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-2.s index 315e6411849..5ffb83a82f5 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-2.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-2.s @@ -1,37 +1,30 @@ /* sysreg-2.s Test file for ARMv8.2 system registers. */ - .macro rw_sys_reg sys_reg xreg r w - .ifc \w, 1 - msr \sys_reg, \xreg - .endif - .ifc \r, 1 - mrs \xreg, \sys_reg - .endif - .endm + .include "sysreg-test-utils.inc" .text - rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x0 r=1 w=0 - rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x0 r=1 w=0 - rw_sys_reg sys_reg=id_aa64mmfr3_el1 xreg=x0 r=1 w=0 - rw_sys_reg sys_reg=id_aa64mmfr4_el1 xreg=x0 r=1 w=0 + rw_sys_reg sys_reg=id_aa64mmfr1_el1 w=0 + rw_sys_reg sys_reg=id_aa64mmfr2_el1 w=0 + rw_sys_reg sys_reg=id_aa64mmfr3_el1 w=0 + rw_sys_reg sys_reg=id_aa64mmfr4_el1 w=0 /* RAS extension. */ - rw_sys_reg sys_reg=erridr_el1 xreg=x0 r=1 w=0 - rw_sys_reg sys_reg=errselr_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=erridr_el1 w=0 + rw_sys_reg sys_reg=errselr_el1 - rw_sys_reg sys_reg=erxfr_el1 xreg=x0 r=1 w=0 - rw_sys_reg sys_reg=erxctlr_el1 xreg=x0 r=1 w=1 - rw_sys_reg sys_reg=erxstatus_el1 xreg=x0 r=1 w=1 - rw_sys_reg sys_reg=erxaddr_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=erxfr_el1 w=0 + rw_sys_reg sys_reg=erxctlr_el1 + rw_sys_reg sys_reg=erxstatus_el1 + rw_sys_reg sys_reg=erxaddr_el1 - rw_sys_reg sys_reg=erxmisc0_el1 xreg=x0 r=1 w=1 - rw_sys_reg sys_reg=erxmisc1_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=erxmisc0_el1 + rw_sys_reg sys_reg=erxmisc1_el1 - rw_sys_reg sys_reg=vsesr_el2 xreg=x0 r=1 w=0 - rw_sys_reg sys_reg=disr_el1 xreg=x0 r=1 w=1 - rw_sys_reg sys_reg=vdisr_el2 xreg=x0 r=1 w=0 + rw_sys_reg sys_reg=vsesr_el2 w=0 + rw_sys_reg sys_reg=disr_el1 + rw_sys_reg sys_reg=vdisr_el2 w=0 /* DC CVAP. */ @@ -47,17 +40,17 @@ /* Statistical profiling. */ .irp reg, pmblimitr_el1, pmbptr_el1, pmbsr_el1 - rw_sys_reg sys_reg=\reg xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=\reg .endr .irp reg, pmscr_el1, pmsicr_el1, pmsirr_el1, pmsfcr_el1 - rw_sys_reg sys_reg=\reg xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=\reg .endr .irp reg, pmsevfr_el1, pmslatfr_el1, pmscr_el2, pmscr_el12 - rw_sys_reg sys_reg=\reg xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=\reg .endr .irp reg, pmbidr_el1, pmsidr_el1 - rw_sys_reg sys_reg=\reg xreg=x0 r=1 w=0 + rw_sys_reg sys_reg=\reg w=0 .endr diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d index 5ed05d6916c..0135762663a 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-3.d @@ -1,5 +1,6 @@ +#source: sysreg-3.s +#as: -march=armv8.3-a -I$srcdir/$subdir #objdump: -dr -#as: -march=armv8.3-a .*: file .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-3.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-3.s index b45f89fcf27..53c6da8104d 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-3.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-3.s @@ -1,21 +1,18 @@ /* sysreg-3.s Test file for ARMv8.3 system registers. */ - .macro test sys_reg xreg - msr \sys_reg, \xreg - mrs \xreg, \sys_reg - .endm + .include "sysreg-test-utils.inc" .text - test sys_reg=apiakeylo_el1 xreg=x0 - test sys_reg=apiakeyhi_el1 xreg=x0 - test sys_reg=apibkeylo_el1 xreg=x0 - test sys_reg=apibkeyhi_el1 xreg=x0 + rw_sys_reg sys_reg=apiakeylo_el1 + rw_sys_reg sys_reg=apiakeyhi_el1 + rw_sys_reg sys_reg=apibkeylo_el1 + rw_sys_reg sys_reg=apibkeyhi_el1 - test sys_reg=apdakeylo_el1 xreg=x0 - test sys_reg=apdakeyhi_el1 xreg=x0 - test sys_reg=apdbkeylo_el1 xreg=x0 - test sys_reg=apdbkeyhi_el1 xreg=x0 + rw_sys_reg sys_reg=apdakeylo_el1 + rw_sys_reg sys_reg=apdakeyhi_el1 + rw_sys_reg sys_reg=apdbkeylo_el1 + rw_sys_reg sys_reg=apdbkeyhi_el1 - test sys_reg=apgakeylo_el1 xreg=x0 - test sys_reg=apgakeyhi_el1 xreg=x0 + rw_sys_reg sys_reg=apgakeylo_el1 + rw_sys_reg sys_reg=apgakeyhi_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-6.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-6.d index ac928ce3037..cb9c46e26b6 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-6.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-6.d @@ -1,3 +1,5 @@ +#source: sysreg-6.s +#as: -I$srcdir/$subdir #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-6.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-6.s index c6772ae732d..16129859095 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-6.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-6.s @@ -1,2 +1,5 @@ -msr hcr_el2, x0 -mrs x0,hcr_el2 + .include "sysreg-test-utils.inc" + + .text + + rw_sys_reg sys_reg=hcr_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d index 5d74fd7056b..846ab8b96ab 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.d @@ -1,3 +1,5 @@ +#source: sysreg-7.s +#as: -I$srcdir/$subdir #objdump: -dr .*: file format .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s index 8354a44a813..e371f19bcfb 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-7.s @@ -1,20 +1,16 @@ -.arch armv8-a+lor + .include "sysreg-test-utils.inc" -msr lorc_el1, x0 -mrs x0, lorc_el1 -msr lorea_el1, x0 -mrs x0, lorea_el1 -msr lorn_el1, x0 -mrs x0, lorn_el1 -msr lorsa_el1, x0 -mrs x0, lorsa_el1 -msr icc_ctlr_el3, x0 -mrs x0, icc_ctlr_el3 -msr icc_sre_el1, x0 -mrs x0, icc_sre_el1 -msr icc_sre_el2, x0 -mrs x0, icc_sre_el2 -msr icc_sre_el3, x0 -mrs x0, icc_sre_el3 + .text -mrs x0, ich_vtr_el2 + .arch armv8-a+lor + + rw_sys_reg sys_reg=lorc_el1 + rw_sys_reg sys_reg=lorea_el1 + rw_sys_reg sys_reg=lorn_el1 + rw_sys_reg sys_reg=lorsa_el1 + rw_sys_reg sys_reg=icc_ctlr_el3 + rw_sys_reg sys_reg=icc_sre_el1 + rw_sys_reg sys_reg=icc_sre_el2 + rw_sys_reg sys_reg=icc_sre_el3 + + rw_sys_reg sys_reg=ich_vtr_el2 w=0 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d index d93b4c7da40..4ee851fc32d 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d @@ -1,3 +1,5 @@ +#source: sysreg-8.s +#as: -I$srcdir/$subdir #objdump: -dr .* diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s index 04bd30d08d1..0cf1178542a 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s @@ -1,192 +1,183 @@ - .macro roreg, name - mrs x0, \name - .endm - - .macro woreg, name - msr \name, x0 - .endm - - .macro rwreg, name - msr \name, x0 - mrs x0, \name - .endm - - roreg id_dfr1_el1 - roreg id_mmfr5_el1 - roreg id_isar6_el1 - - rwreg icc_pmr_el1 - roreg icc_iar0_el1 - woreg icc_eoir0_el1 - roreg icc_hppir0_el1 - rwreg icc_bpr0_el1 - rwreg icc_ap0r0_el1 - rwreg icc_ap0r1_el1 - rwreg icc_ap0r2_el1 - rwreg icc_ap0r3_el1 - rwreg icc_ap1r0_el1 - rwreg icc_ap1r1_el1 - rwreg icc_ap1r2_el1 - rwreg icc_ap1r3_el1 - woreg icc_dir_el1 - roreg icc_rpr_el1 - woreg icc_sgi1r_el1 - woreg icc_asgi1r_el1 - woreg icc_sgi0r_el1 - roreg icc_iar1_el1 - woreg icc_eoir1_el1 - roreg icc_hppir1_el1 - rwreg icc_bpr1_el1 - rwreg icc_ctlr_el1 - rwreg icc_igrpen0_el1 - rwreg icc_igrpen1_el1 - rwreg ich_ap0r0_el2 - rwreg ich_ap0r1_el2 - rwreg ich_ap0r2_el2 - rwreg ich_ap0r3_el2 - rwreg ich_ap1r0_el2 - rwreg ich_ap1r1_el2 - rwreg ich_ap1r2_el2 - rwreg ich_ap1r3_el2 - rwreg ich_hcr_el2 - roreg ich_misr_el2 - roreg ich_eisr_el2 - roreg ich_elrsr_el2 - rwreg ich_vmcr_el2 - rwreg ich_lr0_el2 - rwreg ich_lr1_el2 - rwreg ich_lr2_el2 - rwreg ich_lr3_el2 - rwreg ich_lr4_el2 - rwreg ich_lr5_el2 - rwreg ich_lr6_el2 - rwreg ich_lr7_el2 - rwreg ich_lr8_el2 - rwreg ich_lr9_el2 - rwreg ich_lr10_el2 - rwreg ich_lr11_el2 - rwreg ich_lr12_el2 - rwreg ich_lr13_el2 - rwreg ich_lr14_el2 - rwreg ich_lr15_el2 - rwreg icc_igrpen1_el3 + .include "sysreg-test-utils.inc" + + .text + + rw_sys_reg id_dfr1_el1 w=0 + rw_sys_reg id_mmfr5_el1 w=0 + rw_sys_reg id_isar6_el1 w=0 + + rw_sys_reg icc_pmr_el1 + rw_sys_reg icc_iar0_el1 w=0 + rw_sys_reg icc_eoir0_el1 r=0 + rw_sys_reg icc_hppir0_el1 w=0 + rw_sys_reg icc_bpr0_el1 + rw_sys_reg icc_ap0r0_el1 + rw_sys_reg icc_ap0r1_el1 + rw_sys_reg icc_ap0r2_el1 + rw_sys_reg icc_ap0r3_el1 + rw_sys_reg icc_ap1r0_el1 + rw_sys_reg icc_ap1r1_el1 + rw_sys_reg icc_ap1r2_el1 + rw_sys_reg icc_ap1r3_el1 + rw_sys_reg icc_dir_el1 r=0 + rw_sys_reg icc_rpr_el1 w=0 + rw_sys_reg icc_sgi1r_el1 r=0 + rw_sys_reg icc_asgi1r_el1 r=0 + rw_sys_reg icc_sgi0r_el1 r=0 + rw_sys_reg icc_iar1_el1 w=0 + rw_sys_reg icc_eoir1_el1 r=0 + rw_sys_reg icc_hppir1_el1 w=0 + rw_sys_reg icc_bpr1_el1 + rw_sys_reg icc_ctlr_el1 + rw_sys_reg icc_igrpen0_el1 + rw_sys_reg icc_igrpen1_el1 + rw_sys_reg ich_ap0r0_el2 + rw_sys_reg ich_ap0r1_el2 + rw_sys_reg ich_ap0r2_el2 + rw_sys_reg ich_ap0r3_el2 + rw_sys_reg ich_ap1r0_el2 + rw_sys_reg ich_ap1r1_el2 + rw_sys_reg ich_ap1r2_el2 + rw_sys_reg ich_ap1r3_el2 + rw_sys_reg ich_hcr_el2 + rw_sys_reg ich_misr_el2 w=0 + rw_sys_reg ich_eisr_el2 w=0 + rw_sys_reg ich_elrsr_el2 w=0 + rw_sys_reg ich_vmcr_el2 + rw_sys_reg ich_lr0_el2 + rw_sys_reg ich_lr1_el2 + rw_sys_reg ich_lr2_el2 + rw_sys_reg ich_lr3_el2 + rw_sys_reg ich_lr4_el2 + rw_sys_reg ich_lr5_el2 + rw_sys_reg ich_lr6_el2 + rw_sys_reg ich_lr7_el2 + rw_sys_reg ich_lr8_el2 + rw_sys_reg ich_lr9_el2 + rw_sys_reg ich_lr10_el2 + rw_sys_reg ich_lr11_el2 + rw_sys_reg ich_lr12_el2 + rw_sys_reg ich_lr13_el2 + rw_sys_reg ich_lr14_el2 + rw_sys_reg ich_lr15_el2 + rw_sys_reg icc_igrpen1_el3 .arch armv8.1-a - roreg lorid_el1 + rw_sys_reg lorid_el1 w=0 .arch armv8.3-a - roreg ccsidr2_el1 + rw_sys_reg ccsidr2_el1 w=0 .arch armv8.4-a - rwreg trfcr_el1 - roreg pmmir_el1 - rwreg trfcr_el2 - - rwreg trfcr_el12 - - rwreg amcr_el0 - roreg amcfgr_el0 - roreg amcgcr_el0 - rwreg amuserenr_el0 - rwreg amcntenclr0_el0 - rwreg amcntenset0_el0 - rwreg amcntenclr1_el0 - rwreg amcntenset1_el0 - rwreg amevcntr00_el0 - rwreg amevcntr01_el0 - rwreg amevcntr02_el0 - rwreg amevcntr03_el0 - roreg amevtyper00_el0 - roreg amevtyper01_el0 - roreg amevtyper02_el0 - roreg amevtyper03_el0 - rwreg amevcntr10_el0 - rwreg amevcntr11_el0 - rwreg amevcntr12_el0 - rwreg amevcntr13_el0 - rwreg amevcntr14_el0 - rwreg amevcntr15_el0 - rwreg amevcntr16_el0 - rwreg amevcntr17_el0 - rwreg amevcntr18_el0 - rwreg amevcntr19_el0 - rwreg amevcntr110_el0 - rwreg amevcntr111_el0 - rwreg amevcntr112_el0 - rwreg amevcntr113_el0 - rwreg amevcntr114_el0 - rwreg amevcntr115_el0 - rwreg amevtyper10_el0 - rwreg amevtyper11_el0 - rwreg amevtyper12_el0 - rwreg amevtyper13_el0 - rwreg amevtyper14_el0 - rwreg amevtyper15_el0 - rwreg amevtyper16_el0 - rwreg amevtyper17_el0 - rwreg amevtyper18_el0 - rwreg amevtyper19_el0 - rwreg amevtyper110_el0 - rwreg amevtyper111_el0 - rwreg amevtyper112_el0 - rwreg amevtyper113_el0 - rwreg amevtyper114_el0 - rwreg amevtyper115_el0 + rw_sys_reg trfcr_el1 + rw_sys_reg pmmir_el1 w=0 + rw_sys_reg trfcr_el2 + + rw_sys_reg trfcr_el12 + + rw_sys_reg amcr_el0 + rw_sys_reg amcfgr_el0 w=0 + rw_sys_reg amcgcr_el0 w=0 + rw_sys_reg amuserenr_el0 + rw_sys_reg amcntenclr0_el0 + rw_sys_reg amcntenset0_el0 + rw_sys_reg amcntenclr1_el0 + rw_sys_reg amcntenset1_el0 + rw_sys_reg amevcntr00_el0 + rw_sys_reg amevcntr01_el0 + rw_sys_reg amevcntr02_el0 + rw_sys_reg amevcntr03_el0 + rw_sys_reg amevtyper00_el0 w=0 + rw_sys_reg amevtyper01_el0 w=0 + rw_sys_reg amevtyper02_el0 w=0 + rw_sys_reg amevtyper03_el0 w=0 + rw_sys_reg amevcntr10_el0 + rw_sys_reg amevcntr11_el0 + rw_sys_reg amevcntr12_el0 + rw_sys_reg amevcntr13_el0 + rw_sys_reg amevcntr14_el0 + rw_sys_reg amevcntr15_el0 + rw_sys_reg amevcntr16_el0 + rw_sys_reg amevcntr17_el0 + rw_sys_reg amevcntr18_el0 + rw_sys_reg amevcntr19_el0 + rw_sys_reg amevcntr110_el0 + rw_sys_reg amevcntr111_el0 + rw_sys_reg amevcntr112_el0 + rw_sys_reg amevcntr113_el0 + rw_sys_reg amevcntr114_el0 + rw_sys_reg amevcntr115_el0 + rw_sys_reg amevtyper10_el0 + rw_sys_reg amevtyper11_el0 + rw_sys_reg amevtyper12_el0 + rw_sys_reg amevtyper13_el0 + rw_sys_reg amevtyper14_el0 + rw_sys_reg amevtyper15_el0 + rw_sys_reg amevtyper16_el0 + rw_sys_reg amevtyper17_el0 + rw_sys_reg amevtyper18_el0 + rw_sys_reg amevtyper19_el0 + rw_sys_reg amevtyper110_el0 + rw_sys_reg amevtyper111_el0 + rw_sys_reg amevtyper112_el0 + rw_sys_reg amevtyper113_el0 + rw_sys_reg amevtyper114_el0 + rw_sys_reg amevtyper115_el0 .arch armv8.6-a - roreg amcg1idr_el0 - roreg cntpctss_el0 - roreg cntvctss_el0 - rwreg hfgrtr_el2 - rwreg hfgwtr_el2 - rwreg hfgitr_el2 - rwreg hdfgrtr_el2 - rwreg hdfgwtr_el2 - rwreg hafgrtr_el2 - rwreg amevcntvoff00_el2 - rwreg amevcntvoff01_el2 - rwreg amevcntvoff02_el2 - rwreg amevcntvoff03_el2 - rwreg amevcntvoff04_el2 - rwreg amevcntvoff05_el2 - rwreg amevcntvoff06_el2 - rwreg amevcntvoff07_el2 - rwreg amevcntvoff08_el2 - rwreg amevcntvoff09_el2 - rwreg amevcntvoff010_el2 - rwreg amevcntvoff011_el2 - rwreg amevcntvoff012_el2 - rwreg amevcntvoff013_el2 - rwreg amevcntvoff014_el2 - rwreg amevcntvoff015_el2 - rwreg amevcntvoff10_el2 - rwreg amevcntvoff11_el2 - rwreg amevcntvoff12_el2 - rwreg amevcntvoff13_el2 - rwreg amevcntvoff14_el2 - rwreg amevcntvoff15_el2 - rwreg amevcntvoff16_el2 - rwreg amevcntvoff17_el2 - rwreg amevcntvoff18_el2 - rwreg amevcntvoff19_el2 - rwreg amevcntvoff110_el2 - rwreg amevcntvoff111_el2 - rwreg amevcntvoff112_el2 - rwreg amevcntvoff113_el2 - rwreg amevcntvoff114_el2 - rwreg amevcntvoff115_el2 - rwreg cntpoff_el2 + rw_sys_reg amcg1idr_el0 w=0 + rw_sys_reg cntpctss_el0 w=0 + rw_sys_reg cntvctss_el0 w=0 + rw_sys_reg hfgrtr_el2 + rw_sys_reg hfgwtr_el2 + rw_sys_reg hfgitr_el2 + rw_sys_reg hdfgrtr_el2 + rw_sys_reg hdfgwtr_el2 + rw_sys_reg hafgrtr_el2 + rw_sys_reg amevcntvoff00_el2 + rw_sys_reg amevcntvoff01_el2 + rw_sys_reg amevcntvoff02_el2 + rw_sys_reg amevcntvoff03_el2 + rw_sys_reg amevcntvoff04_el2 + rw_sys_reg amevcntvoff05_el2 + rw_sys_reg amevcntvoff06_el2 + rw_sys_reg amevcntvoff07_el2 + rw_sys_reg amevcntvoff08_el2 + rw_sys_reg amevcntvoff09_el2 + rw_sys_reg amevcntvoff010_el2 + rw_sys_reg amevcntvoff011_el2 + rw_sys_reg amevcntvoff012_el2 + rw_sys_reg amevcntvoff013_el2 + rw_sys_reg amevcntvoff014_el2 + rw_sys_reg amevcntvoff015_el2 + rw_sys_reg amevcntvoff10_el2 + rw_sys_reg amevcntvoff11_el2 + rw_sys_reg amevcntvoff12_el2 + rw_sys_reg amevcntvoff13_el2 + rw_sys_reg amevcntvoff14_el2 + rw_sys_reg amevcntvoff15_el2 + rw_sys_reg amevcntvoff16_el2 + rw_sys_reg amevcntvoff17_el2 + rw_sys_reg amevcntvoff18_el2 + rw_sys_reg amevcntvoff19_el2 + rw_sys_reg amevcntvoff110_el2 + rw_sys_reg amevcntvoff111_el2 + rw_sys_reg amevcntvoff112_el2 + rw_sys_reg amevcntvoff113_el2 + rw_sys_reg amevcntvoff114_el2 + rw_sys_reg amevcntvoff115_el2 + rw_sys_reg cntpoff_el2 .arch armv8.7-a - rwreg pmsnevfr_el1 - rwreg hcrx_el2 + rw_sys_reg pmsnevfr_el1 + rw_sys_reg hcrx_el2 .arch armv8-a+the - rwreg rcwmask_el1 - rwreg rcwsmask_el1 + rw_sys_reg rcwmask_el1 + rw_sys_reg rcwsmask_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-test-utils.inc b/gas/testsuite/gas/aarch64/sysreg/sysreg-test-utils.inc new file mode 100644 index 00000000000..ac618db4400 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-test-utils.inc @@ -0,0 +1,32 @@ +/** Test util to perform a READ and/or WRITE from/to a system register + * + * \param sysreg a system register. + * \param xreg any general purpose register Xn (default=x0). + * \param r boolean enabling or disabling the read test (default=1). + * \param w boolean enabling or disabling the write test (default=1). + */ +.macro rw_sys_reg sys_reg xreg=x0 r=1 w=1 +.ifc \w, 1 +msr \sys_reg, \xreg +.endif +.ifc \r, 1 +mrs \xreg, \sys_reg +.endif +.endm + +/** 128-bits version of rw_sys_reg + * + * \param sysreg a system register. + * \param xreg1 first general-purpose destination register Xn (default=x0). + * \param xreg2 second general-purpose destination register Xn (default=x1). + * \param r boolean enabling or disabling the read test (default=1). + * \param w boolean enabling or disabling the write test (default=1). + */ +.macro rw_sys_reg_128 sys_reg xreg1=x0 xreg2=x1 r=1 w=1 +.ifc \w, 1 +msrr \sys_reg, \xreg1, \xreg2 +.endif +.ifc \r, 1 +mrrs \xreg1, \xreg2, \sys_reg +.endif +.endm diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sysreg.d index 6dfad54a72c..54ade34a87e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.d @@ -1,3 +1,5 @@ +#source: sysreg.s +#as: -I$srcdir/$subdir #objdump: -dr .*: file format .* @@ -5,9 +7,9 @@ Disassembly of section \.text: 0+ <.*>: -.*: d51b9c67 msr pmovsclr_el0, x7 +.*: d51b9c60 msr pmovsclr_el0, x0 .*: d53b9c60 mrs x0, pmovsclr_el0 -.*: d51b9e67 msr pmovsset_el0, x7 +.*: d51b9e60 msr pmovsset_el0, x0 .*: d53b9e60 mrs x0, pmovsset_el0 .*: d5380140 mrs x0, id_dfr0_el1 .*: d5380100 mrs x0, id_pfr0_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.s b/gas/testsuite/gas/aarch64/sysreg/sysreg.s index 998f31596bd..9c0fd4ae2fd 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.s @@ -1,38 +1,31 @@ + .include "sysreg-test-utils.inc" - # Test case for system registers .text - msr pmovsclr_el0, x7 - mrs x0, pmovsclr_el0 - - msr pmovsset_el0, x7 - mrs x0, pmovsset_el0 - - mrs x0, id_dfr0_el1 - mrs x0, id_pfr0_el1 - mrs x0, id_pfr1_el1 - mrs x0, id_afr0_el1 - mrs x0, id_mmfr0_el1 - mrs x0, id_mmfr1_el1 - mrs x0, id_mmfr2_el1 - mrs x0, id_mmfr3_el1 - mrs x0, id_mmfr4_el1 - mrs x0, id_isar0_el1 - mrs x0, id_isar1_el1 - mrs x0, id_isar2_el1 - mrs x0, id_isar3_el1 - mrs x0, id_isar4_el1 - mrs x0, id_isar5_el1 - - mrs x0, id_aa64isar2_el1 - mrs x30, id_aa64isar2_el1 - - mrs x0, id_aa64isar3_el1 - mrs x30, id_aa64isar3_el1 - - mrs x0, s3_0_c12_c15_0 - msr s3_0_c4_c11_0, x0 - mrs x0, s3_0_c4_c11_0 - - msr s2_1_c0_c3_0, x0 - mrs x0, s2_1_c0_c3_0 + rw_sys_reg sys_reg=pmovsclr_el0 + rw_sys_reg sys_reg=pmovsset_el0 + + rw_sys_reg sys_reg=id_dfr0_el1 w=0 + rw_sys_reg sys_reg=id_pfr0_el1 w=0 + rw_sys_reg sys_reg=id_pfr1_el1 w=0 + rw_sys_reg sys_reg=id_afr0_el1 w=0 + rw_sys_reg sys_reg=id_mmfr0_el1 w=0 + rw_sys_reg sys_reg=id_mmfr1_el1 w=0 + rw_sys_reg sys_reg=id_mmfr2_el1 w=0 + rw_sys_reg sys_reg=id_mmfr3_el1 w=0 + rw_sys_reg sys_reg=id_mmfr4_el1 w=0 + rw_sys_reg sys_reg=id_isar0_el1 w=0 + rw_sys_reg sys_reg=id_isar1_el1 w=0 + rw_sys_reg sys_reg=id_isar2_el1 w=0 + rw_sys_reg sys_reg=id_isar3_el1 w=0 + rw_sys_reg sys_reg=id_isar4_el1 w=0 + rw_sys_reg sys_reg=id_isar5_el1 w=0 + + rw_sys_reg sys_reg=id_aa64isar2_el1 xreg=x0 w=0 + rw_sys_reg sys_reg=id_aa64isar2_el1 xreg=x30 w=0 + rw_sys_reg sys_reg=id_aa64isar3_el1 xreg=x0 w=0 + rw_sys_reg sys_reg=id_aa64isar3_el1 xreg=x30 w=0 + + rw_sys_reg sys_reg=s3_0_c12_c15_0 w=0 + rw_sys_reg sys_reg=s3_0_c4_c11_0 + rw_sys_reg sys_reg=s2_1_c0_c3_0 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg128.d b/gas/testsuite/gas/aarch64/sysreg/sysreg128.d index 2998c7b79a2..22df5e241b1 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg128.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg128.d @@ -1,3 +1,5 @@ +#source: sysreg128.s +#as: -I$srcdir/$subdir #objdump: -dr .* @@ -6,23 +8,23 @@ Disassembly of section \.text: 0+ <\.text>: -[^:]*: d5587402 msrr par_el1, x2, x3 -[^:]*: d5787402 mrrs x2, x3, par_el1 -[^:]*: d558d0c2 msrr rcwmask_el1, x2, x3 -[^:]*: d578d0c2 mrrs x2, x3, rcwmask_el1 -[^:]*: d558d062 msrr rcwsmask_el1, x2, x3 -[^:]*: d578d062 mrrs x2, x3, rcwsmask_el1 -[^:]*: d5582002 msrr ttbr0_el1, x2, x3 -[^:]*: d5782002 mrrs x2, x3, ttbr0_el1 -[^:]*: d55d2002 msrr ttbr0_el12, x2, x3 -[^:]*: d57d2002 mrrs x2, x3, ttbr0_el12 -[^:]*: d55c2002 msrr ttbr0_el2, x2, x3 -[^:]*: d57c2002 mrrs x2, x3, ttbr0_el2 -[^:]*: d5582022 msrr ttbr1_el1, x2, x3 -[^:]*: d5782022 mrrs x2, x3, ttbr1_el1 -[^:]*: d55d2022 msrr ttbr1_el12, x2, x3 -[^:]*: d57d2022 mrrs x2, x3, ttbr1_el12 -[^:]*: d55c2022 msrr ttbr1_el2, x2, x3 -[^:]*: d57c2022 mrrs x2, x3, ttbr1_el2 -[^:]*: d55c2102 msrr vttbr_el2, x2, x3 -[^:]*: d57c2102 mrrs x2, x3, vttbr_el2 \ No newline at end of file +.*: d5587402 msrr par_el1, x2, x3 +.*: d5787402 mrrs x2, x3, par_el1 +.*: d558d0c2 msrr rcwmask_el1, x2, x3 +.*: d578d0c2 mrrs x2, x3, rcwmask_el1 +.*: d558d062 msrr rcwsmask_el1, x2, x3 +.*: d578d062 mrrs x2, x3, rcwsmask_el1 +.*: d5582002 msrr ttbr0_el1, x2, x3 +.*: d5782002 mrrs x2, x3, ttbr0_el1 +.*: d55d2002 msrr ttbr0_el12, x2, x3 +.*: d57d2002 mrrs x2, x3, ttbr0_el12 +.*: d55c2002 msrr ttbr0_el2, x2, x3 +.*: d57c2002 mrrs x2, x3, ttbr0_el2 +.*: d5582022 msrr ttbr1_el1, x2, x3 +.*: d5782022 mrrs x2, x3, ttbr1_el1 +.*: d55d2022 msrr ttbr1_el12, x2, x3 +.*: d57d2022 mrrs x2, x3, ttbr1_el12 +.*: d55c2022 msrr ttbr1_el2, x2, x3 +.*: d57c2022 mrrs x2, x3, ttbr1_el2 +.*: d55c2102 msrr vttbr_el2, x2, x3 +.*: d57c2102 mrrs x2, x3, vttbr_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg128.s b/gas/testsuite/gas/aarch64/sysreg/sysreg128.s index ee1d7cda3fa..165dfa713d8 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg128.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg128.s @@ -1,17 +1,14 @@ - .arch armv9.4-a+d128+the + .include "sysreg-test-utils.inc" - .macro rwreg128, name - msrr \name, x2, x3 - mrrs x2, x3, \name - .endm + .arch armv9.4-a+d128+the - rwreg128 par_el1 - rwreg128 rcwmask_el1 - rwreg128 rcwsmask_el1 - rwreg128 ttbr0_el1 - rwreg128 ttbr0_el12 - rwreg128 ttbr0_el2 - rwreg128 ttbr1_el1 - rwreg128 ttbr1_el12 - rwreg128 ttbr1_el2 - rwreg128 vttbr_el2 + rw_sys_reg_128 par_el1 xreg1=x2 xreg2=x3 + rw_sys_reg_128 rcwmask_el1 xreg1=x2 xreg2=x3 + rw_sys_reg_128 rcwsmask_el1 xreg1=x2 xreg2=x3 + rw_sys_reg_128 ttbr0_el1 xreg1=x2 xreg2=x3 + rw_sys_reg_128 ttbr0_el12 xreg1=x2 xreg2=x3 + rw_sys_reg_128 ttbr0_el2 xreg1=x2 xreg2=x3 + rw_sys_reg_128 ttbr1_el1 xreg1=x2 xreg2=x3 + rw_sys_reg_128 ttbr1_el12 xreg1=x2 xreg2=x3 + rw_sys_reg_128 ttbr1_el2 xreg1=x2 xreg2=x3 + rw_sys_reg_128 vttbr_el2 xreg1=x2 xreg2=x3