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[8.43.85.97]) by mx.google.com with ESMTPS id h13-20020a05620a13ed00b00787999a440bsi6766056qkl.551.2024.02.27.00.53.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 00:53:58 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3FD853858C3A for ; Tue, 27 Feb 2024 08:53:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTPS id C31B53858D38 for ; Tue, 27 Feb 2024 08:53:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C31B53858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C31B53858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709023994; cv=none; b=Ic/FWJVnGnC7xaA2TTYmFFQddvRkFpnL+OKXBEWGXNQT1wJdsdj8/pnuOqpEQDl50pVrr83RuxfkvcTS5JzBQFxuv1AlSIaHfFZyHb7gR6Sj3+Dqfw+srgKvmALWgeV6/hLExL520z4Jww5WIMSS738Nf28A8jeYskWiNsV2eIk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709023994; c=relaxed/simple; bh=L+3bs7dLOWdRUCDvDUjR0fxgEqIdJNtq5NgDgbWWKjI=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=p7U0MSwYRJWHyZAbCWXATBDW3zLRG7GkbtZcd+MxrJUF5PYFywypl7MSrYrG+bN9gJ23iqJicHgdg8vWKQRo+Vhe321ObeCLN/YnUWY0Ee8iCwBooKnh2whsismGeaMEIr7kvi3v5Edd+bFd00vak5+I50eN6nBmQ4tZjqlpJno= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-05 (Coremail) with SMTP id zQCowAD3_6voot1lZ6eBAw--.49845S2; Tue, 27 Feb 2024 16:52:58 +0800 (CST) From: Jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@dabbelt.com, jlaw@ventanamicro.com, christoph.muellner@vrull.eu, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Chen Jiawei Subject: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture. Date: Tue, 27 Feb 2024 16:52:43 +0800 Message-Id: <20240227085243.605255-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: zQCowAD3_6voot1lZ6eBAw--.49845S2 X-Coremail-Antispam: 1UD129KBjvJXoW3ZrWfXFWDZr1Dtr4fGr4rZrb_yoWkGw4Dpr WfA3WfAr1rJrs3Wry5GF17Jw13Xa1xGw1rG34UXF48ZF45urZ7tF1DGw1Fq3s0gFWkJ3W7 uryUCa1DAr47ArUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkE14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628v n2kIc2xKxwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F4 0E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFyl IxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxV AFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j 6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUdHU DUUUUU= X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiBgsAAGXdbajPpQAAsa X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792041590392257880 X-GMAIL-MSGID: 1792041590392257880 From: Chen Jiawei Co-Authored by: Lin Jiawei This patch add XiangShan Nanhu cpu microarchitecture, Nanhu is a 6-issue, superscalar, out-of-order processor. More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): New def. (RISCV_CORE): Ditto. * config/riscv/riscv-opts.h (enum * riscv_microarchitecture_type): New option. * config/riscv/riscv.cc: New def. * config/riscv/riscv.md: New include. * config/riscv/xiangshan.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-xiangshan-nanhu.c: New test. --- gcc/config/riscv/riscv-cores.def | 6 + gcc/config/riscv/riscv-opts.h | 1 + gcc/config/riscv/riscv.cc | 17 ++ gcc/config/riscv/riscv.md | 3 +- gcc/config/riscv/xiangshan.md | 148 ++++++++++++++++++ .../gcc.target/riscv/mcpu-xiangshan-nanhu.c | 34 ++++ 6 files changed, 208 insertions(+), 1 deletion(-) create mode 100644 gcc/config/riscv/xiangshan.md create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 57928bccdc8..ab23bb7a856 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -40,6 +40,7 @@ RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info) RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) +RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) RISCV_TUNE("size", generic, optimize_size_tune_info) @@ -90,4 +91,9 @@ RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" "xtheadcondmov_xtheadfmemidx_xtheadmac_" "xtheadmemidx_xtheadmempair_xtheadsync", "thead-c906") + +RISCV_CORE("xiangshan-nanhu", "rv64imafdc_zba_zbb_zbc_zbs_" + "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_" + "svinval_zicbom_zicboz", + "xiangshan-nanhu") #undef RISCV_CORE diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 4edddbadc37..31f9bffa9b6 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -57,6 +57,7 @@ enum riscv_microarchitecture_type { sifive_7, sifive_p400, sifive_p600, + xiangshan, generic_ooo }; extern enum riscv_microarchitecture_type riscv_microarchitecture; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5e984ee2a55..aa53e25ae03 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -498,6 +498,23 @@ static const struct riscv_tune_param thead_c906_tune_info = { NULL, /* vector cost */ }; +/* Costs to use when optimizing for xiangshan nanhu. */ +static const struct riscv_tune_param xiangshan_nanhu_tune_info = { + {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_add */ + {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_mul */ + {COSTS_N_INSNS (10), COSTS_N_INSNS (20)}, /* fp_div */ + {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* int_mul */ + {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ + 6, /* issue_rate */ + 3, /* branch_cost */ + 3, /* memory_cost */ + 3, /* fmv_cost */ + true, /* slow_unaligned_access */ + false, /* use_divmod_expansion */ + RISCV_FUSE_ZEXTW | RISCV_FUSE_ZEXTH, /* fusible_ops */ + NULL, /* vector cost */ +}; + /* Costs to use when optimizing for a generic ooo profile. */ static const struct riscv_tune_param generic_ooo_tune_info = { {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* fp_add */ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1fec13092e2..8aafe19ab51 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -685,7 +685,7 @@ ;; Microarchitectures we know how to tune for. ;; Keep this in sync with enum riscv_microarchitecture. (define_attr "tune" - "generic,sifive_7,sifive_p400,sifive_p600,generic_ooo" + "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo" (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) ;; Describe a user's asm statement. @@ -3859,3 +3859,4 @@ (include "sfb.md") (include "zc.md") (include "corev.md") +(include "xiangshan.md") diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md new file mode 100644 index 00000000000..3ec89bf828e --- /dev/null +++ b/gcc/config/riscv/xiangshan.md @@ -0,0 +1,148 @@ +;; Scheduling description for XiangShan Nanhu. + +;; Nanhu is a 6-issue, superscalar, out-of-order processor. + +;; ----------------------------------------------------- +;; Nanhu Core units +;; 1*jmp + 4*alu + 2*mdu + 4*fma + 2*fmisc + 2*ld + 2*st +;; ----------------------------------------------------- + +(define_automaton "xiangshan") + +(define_cpu_unit "xs_jmp" "xiangshan") +(define_cpu_unit "xs_i2f" "xiangshan") +(define_reservation "xs_jmp_rs" "xs_jmp | xs_i2f") + +(define_cpu_unit "xs_alu_0, xs_alu_1, xs_alu_2, xs_alu_3" "xiangshan") +(define_reservation "xs_alu_rs" + "xs_alu_0 | xs_alu_1 | xs_alu_2 | xs_alu_3") + +(define_cpu_unit "xs_mul_0, xs_mul_1" "xiangshan") +(define_cpu_unit "xs_div_0, xs_div_1" "xiangshan") +(define_reservation "xs_mdu_rs" + "(xs_mul_0 + xs_div_0) | (xs_mul_1 + xs_div_1)") + +(define_cpu_unit "xs_fadd_0, xs_fadd_1, xs_fadd_2, xs_fadd_3" "xiangshan") +(define_cpu_unit "xs_fmul_0, xs_fmul_1, xs_fmul_2, xs_fmul_3" "xiangshan") +(define_reservation "xs_fma_0" "xs_fadd_0 + xs_fmul_0") +(define_reservation "xs_fma_1" "xs_fadd_1 + xs_fmul_1") +(define_reservation "xs_fma_2" "xs_fadd_2 + xs_fmul_2") +(define_reservation "xs_fma_3" "xs_fadd_3 + xs_fmul_3") + +(define_cpu_unit "xs_f2f_0, xs_f2f_1" "xiangshan") +(define_cpu_unit "xs_f2i_0, xs_f2i_1" "xiangshan") +(define_cpu_unit "xs_fdiv_0, xs_fdiv_1" "xiangshan") +(define_reservation "xs_fmisc_rs" + "(xs_f2f_0 + xs_f2i_0 + xs_fdiv_0) | (xs_f2f_1 + xs_f2i_1 + xs_fdiv_1)") + +(define_cpu_unit "xs_ld_0, xs_ld_1" "xiangshan") +(define_cpu_unit "xs_st_0, xs_st_1" "xiangshan") +(define_reservation "xs_ld_rs" "xs_ld_0 | xs_ld_1") +(define_reservation "xs_st_rs" "xs_st_0 | xs_st_1") + +;; ---------------------------------------------------- +;; Memory (load/store) +;; ---------------------------------------------------- + +(define_insn_reservation "xiangshan_load" 3 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "load")) + "xs_ld_rs") + +(define_insn_reservation "xiangshan_fpload" 3 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "fpload")) + "xs_ld_rs") + +(define_insn_reservation "xiangshan_store" 1 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "store")) + "xs_st_rs") + +(define_insn_reservation "xiangshan_fpstore" 1 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "fpstore")) + "xs_st_rs") + +;; ---------------------------------------------------- +;; Int +;; ---------------------------------------------------- + +(define_insn_reservation "xiangshan_jump" 1 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "jump,call,auipc,unknown")) + "xs_jmp_rs") + +(define_insn_reservation "xiangshan_i2f" 3 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "mtc")) + "xs_jmp_rs") + +(define_insn_reservation "xiangshan_mul" 3 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "imul")) + "xs_mdu_rs") + +(define_insn_reservation "xiangshan_div" 21 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "idiv")) + "xs_mdu_rs") + +(define_insn_reservation "xiangshan_alu" 1 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "nop,const,branch,arith,shift,slt,multi,logical,move,bitmanip,unknown")) + "xs_alu_rs") + +;; ---------------------------------------------------- +;; Float +;; ---------------------------------------------------- + + +(define_insn_reservation "xiangshan_fma" 5 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "fmadd")) + "xs_fma_0 | xs_fma_1 | xs_fma_2 | xs_fma_3") + +(define_insn_reservation "xiangshan_fadd" 3 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "fadd")) + "xs_fadd_0 | xs_fadd_1 | xs_fadd_2 | xs_fadd_3") + +(define_insn_reservation "xiangshan_fmul" 3 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "fmul")) + "xs_fmul_0 | xs_fmul_1 | xs_fmul_2 | xs_fmul_3") + +(define_insn_reservation "xiangshan_f2f" 3 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "fcvt,fmove")) + "xs_fmisc_rs") + +(define_insn_reservation "xiangshan_f2i" 3 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "mfc,fcmp")) + "xs_fmisc_rs") + +(define_insn_reservation "xiangshan_sfdiv" 11 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "fdiv") + (eq_attr "mode" "SF")) + "xs_fmisc_rs") + +(define_insn_reservation "xiangshan_sfsqrt" 17 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "fsqrt") + (eq_attr "mode" "SF")) + "xs_fmisc_rs") + +(define_insn_reservation "xiangshan_dfdiv" 21 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "fdiv") + (eq_attr "mode" "DF")) + "xs_fmisc_rs") + +(define_insn_reservation "xiangshan_dfsqrt" 37 + (and (eq_attr "tune" "xiangshan") + (eq_attr "type" "fsqrt") + (eq_attr "mode" "DF")) + "xs_fmisc_rs") diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c new file mode 100644 index 00000000000..2903c88d91c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xiangshan-nanhu" { target { rv64 } } } */ +/* XiangShan Nanhu => rv64imafdc_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd + _zkne_zknh_zksed_zksh_svinval_zicbom_zicboz */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zbkb) \ + && defined(__riscv_zbkc) \ + && defined(__riscv_zbkx) \ + && defined(__riscv_zknd) \ + && defined(__riscv_zkne) \ + && defined(__riscv_zknh) \ + && defined(__riscv_zksed) \ + && defined(__riscv_zksh) \ + && defined(__riscv_svinval)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +}