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h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=YICLj1cb0/0C4sYh6YiWKD8yLR75xOEfdvu/Qs4aFT0yAKDqHbZ/X9S2GGcuWDQF7DXnc19cwFzMozEK3gjTMDwuF9C476tsITH4c+2h7i0PTgr60+JdabHj8isaIZ7aR54cAsqbZ5AJVnfQfBPLlYOVLDKPKtsFSIYmxTB8Wc0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=tecon.ru; spf=pass smtp.mailfrom=tecon.ru; arc=none smtp.client-ip=82.112.190.120 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=tecon.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tecon.ru From: Dmitry Dunaev To: CC: , Dmitry Dunaev , Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , , Subject: [PATCH] mtd: spi-nor: Add Puya Semiconductor chips driver Date: Mon, 26 Feb 2024 12:23:10 +0300 Message-ID: <20240226092312.1834584-1-dunaev@tecon.ru> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791955082519073850 X-GMAIL-MSGID: 1791955082519073850 Add a SPI NOR manufacturer driver for Puya Semiconductor chips Signed-off-by: Dmitry Dunaev --- drivers/mtd/spi-nor/Makefile | 1 + drivers/mtd/spi-nor/puya.c | 64 ++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 drivers/mtd/spi-nor/puya.c diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index 5e68468b72fc..3e22039d0432 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -10,6 +10,7 @@ spi-nor-objs += intel.o spi-nor-objs += issi.o spi-nor-objs += macronix.o spi-nor-objs += micron-st.o +spi-nor-objs += puya.o spi-nor-objs += spansion.o spi-nor-objs += sst.o spi-nor-objs += winbond.o diff --git a/drivers/mtd/spi-nor/puya.c b/drivers/mtd/spi-nor/puya.c new file mode 100644 index 000000000000..2198a9ed7101 --- /dev/null +++ b/drivers/mtd/spi-nor/puya.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Tecon MT LLC. + */ + +#include + +#include "core.h" + +/* Puya Semiconductor (Shanghai) Co., Ltd */ +static const struct flash_info puya_nor_parts[] = { + { + .id = SNOR_ID(0x85, 0x60, 0x10), + .name = "p25q05h", + .size = SZ_64K, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0x85, 0x60, 0x11), + .name = "p25q10h", + .size = SZ_128K, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0x85, 0x60, 0x12), + .name = "p25q20h", + .size = SZ_256K, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0x85, 0x60, 0x13), + .name = "p25q40h", + .size = SZ_512K, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0x85, 0x60, 0x14), + .name = "p25q80h", + .size = SZ_1M, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0x85, 0x60, 0x15), + .name = "p25q16h", + .size = SZ_2M, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0x85, 0x60, 0x16), + .name = "p25q32h", + .size = SZ_4M, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0x85, 0x60, 0x17), + .name = "p25q64h", + .size = SZ_8M, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0x85, 0x60, 0x18), + .name = "p25q128h", + .size = SZ_8M, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + } +}; + +const struct spi_nor_manufacturer spi_nor_puya = { + .name = "puya", + .parts = puya_nor_parts, + .nparts = ARRAY_SIZE(puya_nor_parts), +};