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[88.207.99.145]) by smtp.googlemail.com with ESMTPSA id b14-20020aa7dc0e000000b00462e1d8e914sm7931341edu.68.2022.11.16.13.48.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:48:44 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 1/9] arm64: dts: qcom: ipq8074: fix Gen2 PCIe QMP PHY Date: Wed, 16 Nov 2022 22:48:33 +0100 Message-Id: <20221116214841.1116735-1-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749691086618236259?= X-GMAIL-MSGID: =?utf-8?q?1749691086618236259?= Serdes register space sizes are incorrect, update them to match the actual sizes from downstream QCA 5.4 kernel. Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 4b4cd3eaf6c8..6649a758d8df 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -277,9 +277,9 @@ pcie_qmp1: phy@8e000 { status = "disabled"; pcie_phy1: phy@8e200 { - reg = <0x8e200 0x16c>, + reg = <0x8e200 0x130>, <0x8e400 0x200>, - <0x8e800 0x4f4>; + <0x8e800 0x1f8>; #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_PCIE1_PIPE_CLK>; From patchwork Wed Nov 16 21:48:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 21301 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp78188wrr; Wed, 16 Nov 2022 13:50:46 -0800 (PST) X-Google-Smtp-Source: AA0mqf5Wgmk6lRptmg7eQS//wa2O+aFYEe9tIbQRWkpfgLstxAh7dSmzeDHuY5GC0nGUFaEutMNR X-Received: by 2002:a62:62c2:0:b0:56e:e2f4:4191 with SMTP id w185-20020a6262c2000000b0056ee2f44191mr29526pfb.27.1668635446470; Wed, 16 Nov 2022 13:50:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668635446; cv=none; d=google.com; s=arc-20160816; b=JHKB3v+FtKLAUca7oiOpa92JQzABA/wE229KQ6C1WkvJNHkU+1t5UC9/NrjBxhMdIW LbhoxypT9uryUNKAvaM1bpJrZ6OufapZFdQEUfidJeE0ZEsrIeU9CN1zIeZcfNpWitgS VP/JKW+V2yVUFHBF4v0h41Kd0sg+Cxs2lBZq17YNigo/Jn6Q1Pv0CkApJf2pE6juThCD gokTQP7V7d5miU5SifsP+Orpd7qUUmAvfoTh+6IRmKG5rN/j5ewYF04GmBiXxddOVK/5 Z6ESoNXHksxutgTUkx3c9RTKa/ta2i/nuatkkrToxHaPp4XDBYrEouFr4gedtkcjl8zy hx5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EAzlL7OKuIzPWhKNqIVY4e+Q/KWJKsIpn67snRSlq5k=; b=JyzBDmLVgPzFRLEJEGc738uilfVoUXItt8wxEAPL9d7WDaFkIKugSIFilurWbVnqUZ uGqnIywhbl8w9RH8gbni4FxajUDfheXDgj7ztpNKHvlCFxOgEgQJm8dRt794uJkJaSn5 txzGtuwqr2Yd3VrgKdtFdqLxJg95p4ODN52b5RsafNFQrFQMpWlYHg23OjXwLmkLzpFS thhhFY0VI8RbW9gGwf/6nEOPITevR+UFuJxagMt8qDBmgrAp86+He5R9iOYtQYgpaRMn JYxda+jdjOSHhRSRp6ogjdW+9kXTuZjzB/1hcIAXKo1vduD2h+2Fa57hNTN185Ka5IeO e5Pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=S1L7JT3k; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[88.207.99.145]) by smtp.googlemail.com with ESMTPSA id b14-20020aa7dc0e000000b00462e1d8e914sm7931341edu.68.2022.11.16.13.48.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:48:45 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 2/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY Date: Wed, 16 Nov 2022 22:48:34 +0100 Message-Id: <20221116214841.1116735-2-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116214841.1116735-1-robimarko@gmail.com> References: <20221116214841.1116735-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749691081846011141?= X-GMAIL-MSGID: =?utf-8?q?1749691081846011141?= IPQ8074 comes in 2 silicon versions: * v1 with 2x Gen2 PCIe ports and QMP PHY-s * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC. Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support by fixing the Gen3 QMP PHY node first. Change the compatible to the Gen3 QMP PHY, correct the register space start and size, add the missing misc PCS register space. Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 6649a758d8df..9503dfb25d50 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -232,9 +232,9 @@ qusb_phy_0: phy@79000 { status = "disabled"; }; - pcie_qmp0: phy@86000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x00086000 0x1c4>; + pcie_qmp0: phy@84000 { + compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; + reg = <0x00084000 0x1bc>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -248,10 +248,11 @@ pcie_qmp0: phy@86000 { "common"; status = "disabled"; - pcie_phy0: phy@86200 { - reg = <0x86200 0x16c>, - <0x86400 0x200>, - <0x86800 0x4f4>; + pcie_phy0: phy@84200 { + reg = <0x84200 0x16c>, + <0x84400 0x200>, + <0x84800 0x1f0>, + <0x84c00 0xf4>; #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_PCIE0_PIPE_CLK>; From patchwork Wed Nov 16 21:48:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 21305 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp78552wrr; Wed, 16 Nov 2022 13:51:54 -0800 (PST) X-Google-Smtp-Source: AA0mqf6216YKRrugDipsi2nbPg3Nylf8pkx1xBA3eAiAHi6SdoX7TjXIgjvwSxm041PQ150YgTt8 X-Received: by 2002:a17:90a:f982:b0:210:7cd5:db0e with SMTP id cq2-20020a17090af98200b002107cd5db0emr5873873pjb.30.1668635513717; Wed, 16 Nov 2022 13:51:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668635513; cv=none; d=google.com; s=arc-20160816; b=CllrnX/8rQk4WBYPXAa8tZ2w0655gC8ajgo7WZI3sdLVX0GBd9pLnYJ3oDs2O6KA7j RvTTAwJeLUP2o/S2A3tUgvtoZZBh+Offka2xDK+hkc3eMmRX1iWlyyh0Lu6a3RACqDcB Xt00QxDKinPKiLqaRL2+j8mmST2WhFNLOBZGnjz6zFUs9fgtpzyfRcBua6m5+S00ptex 2B0HGVk4COxfl3rMNC2isiIeFeImCIjdTnoT2hWqeK+5dFUb44yawVot6UVfh1q7MxfX xP7KItMnjwHMF3AbTG4MSpd7BtcRlOOqDw2TvxBJRaE3dXNw8V5ssNQF8DMQ2PafoKOX Ux4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zruJLlJ8a35SxUsYi/AnlLXhcK2EHytmRl4aws2VY94=; b=HlnraazmdxSz2MGZSNmDEb/00l/8ugnBCQELKALlclqjTbM9YQgGVi767VJpv+ChYM 7nQ8b5SZY0vFYmJFwTf/UNMNEh20mPUYP8NwOnwZGYd21RilychX3P/qxywaHP1MYPI8 lzYc/6WnVIyvURAeYSUN7/tkMxSa1U0Pq4hM1IVeVcN9ctf+pVjK8pS1zt9TsdsjjE2J xjWUuIG1PNsG363VkseBMgoy3uOZnb3fpcZUMp3yHP/HF1sUtvsHvzK6oZ7USIAFJrrg dIef+hTpLZogMapqZbP6Y9Zs7TDnTTJn2fAUIKIW3RpVtDPmoCZCqMom2CklUuNg1z6G FRxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=kyOPa3lU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[88.207.99.145]) by smtp.googlemail.com with ESMTPSA id b14-20020aa7dc0e000000b00462e1d8e914sm7931341edu.68.2022.11.16.13.48.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:48:46 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 3/9] arm64: dts: qcom: ipq8074: correct Gen2 PCIe ranges Date: Wed, 16 Nov 2022 22:48:35 +0100 Message-Id: <20221116214841.1116735-3-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116214841.1116735-1-robimarko@gmail.com> References: <20221116214841.1116735-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749691152312255603?= X-GMAIL-MSGID: =?utf-8?q?1749691152312255603?= Current ranges property set in Gen2 PCIe node is incorrect, replace it with the downstream 5.4 QCA kernel value. Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 9503dfb25d50..b1decedbd080 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -808,9 +808,9 @@ pcie1: pci@10000000 { phy-names = "pciephy"; ranges = <0x81000000 0 0x10200000 0x10200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x10300000 0x10300000 - 0 0xd00000>; /* non-prefetchable memory */ + 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0x10220000 0x10220000 + 0 0xfde0000>; /* non-prefetchable memory */ interrupts = ; interrupt-names = "msi"; From patchwork Wed Nov 16 21:48:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 21308 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp78589wrr; Wed, 16 Nov 2022 13:52:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf5CxKuDSmchAS0Hn1HeIluEV2pRenABX5/nAVHN91T841QJqcbxwU2fCJXOq4hOcsjTFTq6 X-Received: by 2002:a17:90a:71c5:b0:213:b0e:ede8 with SMTP id m5-20020a17090a71c500b002130b0eede8mr5657119pjs.89.1668635522353; Wed, 16 Nov 2022 13:52:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668635522; cv=none; d=google.com; s=arc-20160816; b=cGUJLgeqTu+alIuDAmqinpyC/gwnOv2K951rre+RCBv3fXplpYxHxkafgCduD90ilh lx8C0i7bBsHxpZdMO8qVDXTw+NftkUtdzsW5Jg8XdkfDSx33U5qgtD628CUDhfLUAHo7 Hf1BRmiNi1Rw2P8kmJVFNfJOZ+cKpk0WPJg/npGl/0iazODhTd0cOof+QWXnenzPUn+8 PjvdLpp26J5FLSu2MLpZoxuAqJ1ei/V9cmgSfXRc2Q9zZy71VIwQcJXPA99i18x+Mvd7 3dEJ3pzWeLOtFs1Ir2iLLbHMpmboIwGYn8BRPfsoTyZkJ1/X9axwZua/KNFY6YxnvDLz k/YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=loIeYsbIfqk2P074OtBAWf7HGIfr867twQZf+5G/rew=; b=ZhZvf0qwTJCixQ7x4frhVkqgjqFruJ8vZ/l6FrbL6foOsBiubQTjR8XZ8ynWBgnzIO HjCLPpKW7JJxD/3E8TgiJgxjMRr9KMBv583W14ammUafAnaEL48llhb7JBGAShXGr0OG zEeqV4Fn1SFG27MMuUWYCGJswRIHuNiRTpEb8WVXqu0htQw8m2QgVSSJZd3W6L/Or+5U ASDH1C1y9v6ep+ujnF7jd5T934xy/ojyAuGD5Q+QGGMrYwP7Oe06d+EboHO5VNcj+rOY G72jFnIjTVnUAjU+X4FJo3xcAoL7AgdvVLbI0dllVeD4z5Nk2YiUT7mZlvs2eG6fpJEW DGBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="aPwVJ/UR"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[88.207.99.145]) by smtp.googlemail.com with ESMTPSA id b14-20020aa7dc0e000000b00462e1d8e914sm7931341edu.68.2022.11.16.13.48.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:48:47 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 4/9] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed Date: Wed, 16 Nov 2022 22:48:36 +0100 Message-Id: <20221116214841.1116735-4-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116214841.1116735-1-robimarko@gmail.com> References: <20221116214841.1116735-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749691161379297461?= X-GMAIL-MSGID: =?utf-8?q?1749691161379297461?= Add the generic 'max-link-speed' property to describe the Gen2 PCIe link generation limit. This allows the generic DWC code to configure the link speed correctly. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index b1decedbd080..585e5f0a139d 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -801,6 +801,7 @@ pcie1: pci@10000000 { linux,pci-domain = <1>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; From patchwork Wed Nov 16 21:48:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 21304 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp78452wrr; Wed, 16 Nov 2022 13:51:31 -0800 (PST) X-Google-Smtp-Source: AA0mqf7vLg07LOcqxNdTpxWGDkIbuqCVP51SfWC/dAkVvK3QrAr1FaqXKwpeDTX6CjAJAon0Trh7 X-Received: by 2002:a17:902:e94d:b0:187:2430:d37d with SMTP id b13-20020a170902e94d00b001872430d37dmr10776818pll.28.1668635491179; Wed, 16 Nov 2022 13:51:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668635491; cv=none; d=google.com; s=arc-20160816; b=vO0LeEuD8d4Xb2duCHeG4DdWQbSZalVVHQp9nKIN1wo6AGtsmeIUtePqgEOprsmO+m gWsTgrooez2k+iCcYorHhaPt/KteQQaFWCxZe9rmmQW4ZrtmLktrry4OFb4B0bjkK5/C QJEQ5Awxw6U8B2RDu5hEHwcxtW9u9tqCznPelLWjlbrIpJpMCFfCuvnUoskpmYKnwrP5 ElsSsFDmhRJJkOqgWcQ9RvMGO9KG7ejNiGS78jj2ASSd2KGniDOeH6s6SrEaDItMHXzi 3Y0L2rrcPT3iOecj5gOClzlumgBgngantiY9p8QBIoe9OOITeDTImwjhxe1ZyTf74VDS Do/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1EGkalAXlOl0NBxY3u6qgvGXD8V2PCW1rraeENgVJy4=; b=WLvNTwZUyGFN/7EF9mQnAAzl6H/uZ9tt/BsO8jeNS/w3AyWK4e68EKs8HRr/raOqql oAmPLnUDZH09JPAJQGymtc41Hucsd5UubRCPiI5ITByaZVdzmy4GlUwntQFYA4O61e6N uTto4ZFZnsqv9aJCMm77uJ77hANxVQyCy1ZukLJVetTLzqYQt8yVpljarlMOxOzLMqvx YrlQHN1YTrVC3Jjf8QWBz57jwAm7hnmdiWgLUqYPEtttBCyC0I7wEq94rJ2KAoAjQ4oo G9llhvunpm+m65pismrrMSJM8J8KoJlkWf6Qx4IYaj4bwEiJx/utY77R6tB6rrA0Ah7b r3pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=aKUwugI5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[88.207.99.145]) by smtp.googlemail.com with ESMTPSA id b14-20020aa7dc0e000000b00462e1d8e914sm7931341edu.68.2022.11.16.13.48.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:48:49 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 5/9] dt-bindings: PCI: qcom: alphabetically sort compatibles Date: Wed, 16 Nov 2022 22:48:37 +0100 Message-Id: <20221116214841.1116735-5-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116214841.1116735-1-robimarko@gmail.com> References: <20221116214841.1116735-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749691128820116955?= X-GMAIL-MSGID: =?utf-8?q?1749691128820116955?= Sort the compatibles list alphabetically for maintenance. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 2f851c804bb0..1e94c210429a 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -17,13 +17,14 @@ description: | properties: compatible: enum: - - qcom,pcie-ipq8064 - - qcom,pcie-ipq8064-v2 - qcom,pcie-apq8064 - qcom,pcie-apq8084 - - qcom,pcie-msm8996 - qcom,pcie-ipq4019 + - qcom,pcie-ipq6018 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 + - qcom,pcie-msm8996 - qcom,pcie-qcs404 - qcom,pcie-sa8540p - qcom,pcie-sc7280 @@ -34,7 +35,6 @@ properties: - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - - qcom,pcie-ipq6018 reg: minItems: 4 From patchwork Wed Nov 16 21:48:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 21309 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp78623wrr; Wed, 16 Nov 2022 13:52:10 -0800 (PST) X-Google-Smtp-Source: AA0mqf7LsrW7+slC3H+O6IoM9LeU+OjZegp0rCTyldjV7fbcYodKZ+xSty0v5KuSLBKu/M+tQ9mp X-Received: by 2002:a17:90a:f982:b0:210:7cd5:db0e with SMTP id cq2-20020a17090af98200b002107cd5db0emr5874768pjb.30.1668635529996; Wed, 16 Nov 2022 13:52:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668635529; cv=none; d=google.com; s=arc-20160816; b=U1TPDCjzenp0veRatLpy7CgwFAEULOUnLxI7Oc9Ad4eBBUI/Cc5Pl8J+3TPqkpK9yp hGcFWaZ5OhUHpjrE1aQjL1NfCRv1IsjoNQTD+71MSE2R+5FnmJMJdPGCvYTtk8nwkys+ dkWCfMNyxrkvDbEK7eqhKNz1KQLetG9yzJwyMp6vqFmqUsJ1A91mSC7OEATmPDFflzSB vVMj+lHkiVoPus+9TlgvtmnRliX2LIwGkX303tJzplUS1uznZBGYVVndGds/PC0Ie+3p g0heAGnePjNvnqBA0nU3RltR15sFHg+p4xFaP8YNZAWBS5oEMgNJ3WWAp3mHiNyPOJfd 9V1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2YHxYmic2BMW4CGYYVCcf0TtkyGIao9/HDkKDNLiz8s=; b=IRL7Q2xR3TIMAecF86zO2Nktuxrp+pQzBuckcp/YYsnkxGBdIpiTmEFr7cm2y9B0ri v1wh5n5kOukTYIJUHfgBZAxGLgOeZ8DTx5620CVpsV1bLi//ew+/Tmd0fbLqR6eAA7N6 q9jpdEscnrZAEUIBtF1e9624dUOKk/D0b2hyrVSDydIlrevwGoU8EPynYeikT2CM9oVn IcrZ4Iu5fkqZkWl3XAUrWrIYMBVFRWduTba+FMH7x3FrOUU6mnZtG3qWf9lJwAyiuf/U OCwhQG9nzAkEJwuqso6XO8PYsZArMjU9hcz77sbDELZy3kMrHkoSMSZdnB5V9bB1YaYM jnxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=pZBB47yG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[88.207.99.145]) by smtp.googlemail.com with ESMTPSA id b14-20020aa7dc0e000000b00462e1d8e914sm7931341edu.68.2022.11.16.13.48.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:48:50 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 6/9] dt-bindings: PCI: qcom: document IPQ8074 Gen3 port Date: Wed, 16 Nov 2022 22:48:38 +0100 Message-Id: <20221116214841.1116735-6-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116214841.1116735-1-robimarko@gmail.com> References: <20221116214841.1116735-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749691169427846999?= X-GMAIL-MSGID: =?utf-8?q?1749691169427846999?= IPQ8074 has one Gen2 and one Gen3 PCIe port, with Gen2 already supported. Document Gen3 port which uses the same controller as IPQ6018. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 1e94c210429a..59f4c9990f85 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -24,6 +24,7 @@ properties: - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - qcom,pcie-sa8540p @@ -151,6 +152,7 @@ allOf: contains: enum: - qcom,pcie-ipq6018 + - qcom,pcie-ipq8074-gen3 then: properties: reg: @@ -371,6 +373,7 @@ allOf: contains: enum: - qcom,pcie-ipq6018 + - qcom,pcie-ipq8074-gen3 then: properties: clocks: @@ -662,6 +665,7 @@ allOf: - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 then: required: @@ -744,6 +748,7 @@ allOf: - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 - qcom,pcie-sa8540p then: From patchwork Wed Nov 16 21:48:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 21306 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp78581wrr; Wed, 16 Nov 2022 13:52:01 -0800 (PST) X-Google-Smtp-Source: AA0mqf7E+e5Y8BbuJT4iUVxUsLvba4ke1gjglloOvb20G0XUWcMFeL305Kc5BONCod9Ftjluwrom X-Received: by 2002:a17:90a:8005:b0:200:462f:6419 with SMTP id b5-20020a17090a800500b00200462f6419mr5725571pjn.135.1668635521206; Wed, 16 Nov 2022 13:52:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668635521; cv=none; d=google.com; s=arc-20160816; b=h1G9XEWbXFUlQ4KRTna7XCjUc6emITCGSUBJyk28cflCVPI8j2RW+MOHthmVCyylp2 yEtXKHYVSreh6MVXG37/ZxPL8ShE9RiZkM8teUe0J/0EUn2JTgDH+gVWLMBQoGUOIXAP qzKmbXmlwC24OFDuVLL/3yGCooA63EfkLpJAVsvYCNUTvHzRtrfxr66jHuOMbXJbfEdi Gr7tWXhnSKiW+no4kE2cJqL/Uppr5GI6+//IwmgO8YkjoNrl1/UR7RTMehZsNpMhyydX gyeJi/BXy3MyXZktP9Jz/Z+X57Xmon7s7G2e7yE2RjXSzmTzdKvZ42wcV3XexuWbB20a oMNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XhziJCTfYAX8UUJF9yrOBjkYfO4Z58hl4/PJ9cRFK4w=; b=EhTJn8RZT9f3H3m5Y0GYV5aWi/yMm4TK4E5O2JvadAYdDpCNTHacHnYHNL4Jtt11gI 6gYoBfBWOKGcCRmW1wqzUqHyWVn/WCYzFb9kAwPbuXvaG/Y9yN6mMv2VZ7N64eaoaHYo XLMnsSs5wK2rraqgy/PC5n2mgEJCC+KifwFWjlIPSmCfRWq6PpZ+Cce5hYaeg6Kku6WJ XaVaAWV1UFPJ0fp6EZ14YmGbHxuE9ElENJ4Vt2IPZo4sK+mkVDQCJy6Vgdv44n1Ifa8g KKGGlNj02a/6xaistb9fhcF6ar0KcruE8Ph8uK56RV66df1oQBZhPd6UanMuGBp5Stjt 74og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=UUMk7NQB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[88.207.99.145]) by smtp.googlemail.com with ESMTPSA id b14-20020aa7dc0e000000b00462e1d8e914sm7931341edu.68.2022.11.16.13.48.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:48:52 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 7/9] PCI: qcom: add support for IPQ8074 Gen3 port Date: Wed, 16 Nov 2022 22:48:39 +0100 Message-Id: <20221116214841.1116735-7-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116214841.1116735-1-robimarko@gmail.com> References: <20221116214841.1116735-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749691160502109915?= X-GMAIL-MSGID: =?utf-8?q?1749691160502109915?= IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported. Add compatible for Gen3 port which uses the same controller as IPQ6018. Signed-off-by: Robert Marko Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 77e5dc7b88ad..97e8510c53fb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1817,6 +1817,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, + { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 }, From patchwork Wed Nov 16 21:48:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 21307 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp78583wrr; Wed, 16 Nov 2022 13:52:01 -0800 (PST) X-Google-Smtp-Source: AA0mqf6XY027fmwIQhxaWS9aTAQHZgIDyPqbK+uOZY6L03GIfEOEllkApC9Fw+LSNgGF5ls0g/2t X-Received: by 2002:a05:6a00:11:b0:56c:a2f1:2783 with SMTP id h17-20020a056a00001100b0056ca2f12783mr62857pfk.7.1668635521329; Wed, 16 Nov 2022 13:52:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668635521; cv=none; d=google.com; s=arc-20160816; b=iktwBFk43ylKRsLK2AV9HfYZh48Da3NpcuARb0qH6mUEIaJV9AC8wquo+lG4PvfWZ7 EccNjYtIcIHloO3sCjOtOeIKWvPJeXZRhHkKNOkQ9MR3vfODgQdWKyvWegYleQTtsapE IvtfTJgRVsWt/XPyenflTEgXSbjKOuY+ErfH4mZOSkDZd4+tc0OsdZ3bbHk29l7YnCS+ s7jPqY4l7IQg3lYON5PJ+VQdfhByOrq4ez24gJvgq+JSZjQa7uXAWRtUslUq8d21uoe8 dj7aPhVvSnVGdzyp2G35Srt+NqAfFIztEdGLpSEuwZ0LsO5Axi84lYLhpoGyNX/PwYPc z1UQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oqP3TbX6KVo39b2lQABBBQ0jY7NpQinCFYzDvvPTOAQ=; b=VYirf9JMoEgzYJ7mHcODFViSsuSa3459yw2xozTL9xb9mdsakKuSy0hl+B+UowicFP O7WkiNHse1TPrI1FPvsODZLAATVtdkQrj9sGhYhrkN8AQiZBLGF8F/+doGaCPmssfdQt 5XLQweUsV05AR2pGV8J2dqxODeNieoMiVbIkFjN8zJOaVNr2e+fjqcKxOW4sYyXj/omy R2hWM1gtYFeWojkkAsFhtymN+7V3KU6Dwt+asfAA1/HCnzSC2yG9Iyp1iUCmwlvo4Fnb Q2uAAjL9rzrZaXhNG80WKKQKAdg07OqQ68WPJuEefOhdCyEdghH1p/FhUGyjGo/httmJ 01yQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=mdrUYfp7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[88.207.99.145]) by smtp.googlemail.com with ESMTPSA id b14-20020aa7dc0e000000b00462e1d8e914sm7931341edu.68.2022.11.16.13.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:48:53 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 8/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe node Date: Wed, 16 Nov 2022 22:48:40 +0100 Message-Id: <20221116214841.1116735-8-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116214841.1116735-1-robimarko@gmail.com> References: <20221116214841.1116735-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749691160309913922?= X-GMAIL-MSGID: =?utf-8?q?1749691160309913922?= IPQ8074 comes in 2 silicon versions: * v1 with 2x Gen2 PCIe ports and QMP PHY-s * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC. Finish the PCIe fixup by using the correct compatible, adding missing ATU register space, declaring max-link-speed, use correct ranges, add missing clocks and resets. Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 30 +++++++++++++++------------ 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 585e5f0a139d..c76c6ee9acb6 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -854,16 +854,18 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ }; pcie0: pci@20000000 { - compatible = "qcom,pcie-ipq8074"; + compatible = "qcom,pcie-ipq8074-gen3"; reg = <0x20000000 0xf1d>, <0x20000f20 0xa8>, - <0x00080000 0x2000>, + <0x20001000 0x1000>, + <0x00080000 0x4000>, <0x20100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; + reg-names = "dbi", "elbi", "atu", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <3>; #address-cells = <3>; #size-cells = <2>; @@ -871,9 +873,9 @@ pcie0: pci@20000000 { phy-names = "pciephy"; ranges = <0x81000000 0 0x20200000 0x20200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x20300000 0x20300000 - 0 0xd00000>; /* non-prefetchable memory */ + 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0x20220000 0x20220000 + 0 0xfde0000>; /* non-prefetchable memory */ interrupts = ; interrupt-names = "msi"; @@ -891,28 +893,30 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, <&gcc GCC_PCIE0_AXI_M_CLK>, <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, - <&gcc GCC_PCIE0_AUX_CLK>; - + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>; clock-names = "iface", "axi_m", "axi_s", - "ahb", - "aux"; + "axi_bridge", + "rchng"; + resets = <&gcc GCC_PCIE0_PIPE_ARES>, <&gcc GCC_PCIE0_SLEEP_ARES>, <&gcc GCC_PCIE0_CORE_STICKY_ARES>, <&gcc GCC_PCIE0_AXI_MASTER_ARES>, <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; reset-names = "pipe", "sleep", "sticky", "axi_m", "axi_s", "ahb", - "axi_m_sticky"; + "axi_m_sticky", + "axi_s_sticky"; status = "disabled"; }; }; From patchwork Wed Nov 16 21:48:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 21310 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp78628wrr; Wed, 16 Nov 2022 13:52:10 -0800 (PST) X-Google-Smtp-Source: AA0mqf7SDeFUhp1sMrOyWtPHekR0zrNQd8DnYNdMHqvH7O5DnMLeH2ys0fu/QElKSrYa5fGv8k7m X-Received: by 2002:a63:4087:0:b0:44e:46f9:7eeb with SMTP id n129-20020a634087000000b0044e46f97eebmr22380236pga.3.1668635530619; Wed, 16 Nov 2022 13:52:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668635530; cv=none; d=google.com; s=arc-20160816; b=k69oM1kaN+5VkjtusoOOeCPaMmTdM2Cyn8NdCXTp/gZOUb5g72VIGT/uVUUBuMeFiJ GvLaAKbci3IoFr0/1cuXsQxaKTwD/QrdzGa8+hv1QKJqXraxL98k0ASv9qgmvNZgRwTR gGjs4Vrn3uPvgVU90HZkXSUlxcdhdPAv1JPS6lC3mCO1pIjDrRMFcJ0K5TjNDovNcCPQ qsFHMTj8CIfbFHZrpdY50aN1e+jfUpkDl4acu+iAAE8on6NnxFPt2+wWZT16YFsIxHkz 21Ny0/2226PK+zuqBm5xvMuMu6pWBr4wX+xieYzuSTBKu5HE/ZFZAoVA4zPw+H4DSjCJ HnWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZHuhgPHSj8IDOBxbmjfqfqORtE7/J1Jlb4tgqi6UVDE=; b=JxgOCFetoD070Xt6Cf4J7tGWEDd4kCikE/xRJ1EaEcHVqAF9RfnFDzfM1aFAHkeIO8 aBq/5mN3f94RGLkl1AdusNN/SddIERdV/lmI94MvVgqeeYS5UrwIpf9VUQiqILQUX0b1 PYHpsM6/g9+mc46+bF5aX9XNBrSXo4gQikEa5cvEeRTIevai+N4am9nopwtZpXs2k7dC hwyRvBcAKuqJ6F2A/um4uw00tRbOhgLsE/4CIFnz+ENYiaDUDjcYjnjHUDr5VV/4eyaF PssVFx8j3y2g3r2Q5Vlef+GsjKybnGEQ3yd5vVIdcJjDEOcnwqDeCM94Rc0+8uLZM/eN aazQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=Sr6BfiXr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[88.207.99.145]) by smtp.googlemail.com with ESMTPSA id b14-20020aa7dc0e000000b00462e1d8e914sm7931341edu.68.2022.11.16.13.48.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:48:54 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 9/9] arm64: dts: qcom: ipq8074: correct PCIe QMP PHY output clock names Date: Wed, 16 Nov 2022 22:48:41 +0100 Message-Id: <20221116214841.1116735-9-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116214841.1116735-1-robimarko@gmail.com> References: <20221116214841.1116735-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749691169790245859?= X-GMAIL-MSGID: =?utf-8?q?1749691169790245859?= Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC driver is relying on the old names to match them as they are being used as the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk. This broke parenting as GCC could not find the parent clock, so fix it by changing to the names that driver is expecting. Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index c76c6ee9acb6..6f5d447c9ee7 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -257,7 +257,7 @@ pcie_phy0: phy@84200 { #clock-cells = <0>; clocks = <&gcc GCC_PCIE0_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "pcie_0_pipe_clk"; + clock-output-names = "pcie20_phy0_pipe_clk"; }; }; @@ -285,7 +285,7 @@ pcie_phy1: phy@8e200 { #clock-cells = <0>; clocks = <&gcc GCC_PCIE1_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "pcie_1_pipe_clk"; + clock-output-names = "pcie20_phy1_pipe_clk"; }; };