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[88.207.99.145]) by smtp.googlemail.com with ESMTPSA id qx17-20020a170906fcd100b0073d7ab84375sm7420078ejb.92.2022.11.16.13.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:46:57 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko , Christian Marangi Subject: [PATCH v2] clk: qcom: ipq8074: populate fw_name for all parents Date: Wed, 16 Nov 2022 22:46:55 +0100 Message-Id: <20221116214655.1116467-1-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749691052331951499?= X-GMAIL-MSGID: =?utf-8?q?1749691052331951499?= It appears that having only .name populated in parent_data for clocks which are only globally searchable currently will not work as the clk core won't copy that name if there is no .fw_name present as well. So, populate .fw_name for all parent clocks in parent_data. Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data") Co-developed-by: Christian Marangi Signed-off-by: Christian Marangi Signed-off-by: Robert Marko --- Changes in v2: * Add fw_name for PCIe PHY pipe clocks as well --- drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++----------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index d231866804f6..8374cc40915a 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src = { }; static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = { - { .name = "pcie20_phy0_pipe_clk" }, + { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" }, { .fw_name = "xo", .name = "xo" }, }; @@ -733,7 +733,7 @@ static struct clk_rcg2 pcie1_aux_clk_src = { }; static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = { - { .name = "pcie20_phy1_pipe_clk" }, + { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" }, { .fw_name = "xo", .name = "xo" }, }; @@ -1137,7 +1137,7 @@ static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = { static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = { { .fw_name = "xo", .name = "xo" }, - { .name = "bias_pll_nss_noc_clk" }, + { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll2.clkr.hw }, }; @@ -1362,7 +1362,7 @@ static const struct freq_tbl ftbl_nss_ppe_clk_src[] = { static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = { { .fw_name = "xo", .name = "xo" }, - { .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll4.clkr.hw }, { .hw = &nss_crypto_pll.clkr.hw }, @@ -1413,10 +1413,10 @@ static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = { static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = { { .fw_name = "xo", .name = "xo" }, - { .name = "uniphy0_gcc_rx_clk" }, - { .name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, }; static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = { @@ -1465,10 +1465,10 @@ static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = { static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = { { .fw_name = "xo", .name = "xo" }, - { .name = "uniphy0_gcc_tx_clk" }, - { .name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, }; static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = { @@ -1696,12 +1696,12 @@ static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = { { .fw_name = "xo", .name = "xo" }, - { .name = "uniphy0_gcc_rx_clk" }, - { .name = "uniphy0_gcc_tx_clk" }, - { .name = "uniphy1_gcc_rx_clk" }, - { .name = "uniphy1_gcc_tx_clk" }, + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" }, + { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, }; static const struct parent_map @@ -1758,12 +1758,12 @@ static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = { { .fw_name = "xo", .name = "xo" }, - { .name = "uniphy0_gcc_tx_clk" }, - { .name = "uniphy0_gcc_rx_clk" }, - { .name = "uniphy1_gcc_tx_clk" }, - { .name = "uniphy1_gcc_rx_clk" }, + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" }, + { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, }; static const struct parent_map @@ -1820,10 +1820,10 @@ static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = { { .fw_name = "xo", .name = "xo" }, - { .name = "uniphy2_gcc_rx_clk" }, - { .name = "uniphy2_gcc_tx_clk" }, + { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" }, + { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, }; static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = { @@ -1877,10 +1877,10 @@ static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = { { .fw_name = "xo", .name = "xo" }, - { .name = "uniphy2_gcc_tx_clk" }, - { .name = "uniphy2_gcc_rx_clk" }, + { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" }, + { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, }; static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {