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[2001:14ba:a00e:a300:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id u19-20020a2e8553000000b002d11ef66881sm713092ljj.91.2024.02.25.18.28.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 18:28:00 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 26 Feb 2024 04:27:59 +0200 Subject: [PATCH v4 1/3] drm/msm/dpu: make "vblank timeout" more useful Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240226-fd-dpu-debug-timeout-v4-1-51eec83dde23@linaro.org> References: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> In-Reply-To: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Steev Klimaszewski , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1113; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=u/LLMAwCactui0InH0azxw69mOb5zZdT0MKFe0dxyYY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBl2/cv3wmpf4E4iBAzHWRmMIm2xXfZ9nq0MLbMk UhPkkONCbSJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZdv3LwAKCRCLPIo+Aiko 1cuxB/9yyz8H/zy2dEohWWy29s9WbXojtz4t+WYhhbEzbRHqJkpqoSL92QjfIFdLuv/iJWazADD tuZyzZgMYyO1Qqlod5lZXLlm7WoelkQGBZzk3xoFSpQWM16HypNWEmxwkgaqyGfos3Alp+L9T4t weBlSTgaKeo2WlkB48Rzmk8FRuaPyoQymxyixCFUUb1hy4RF4+XCm0U3wZ8H9d3bdobv4Vu76gG IplHCwPOr5aNPomk0hJuxBB6hxHgHPUB9cAuFxKwp+iu6zSXJXUsiLwzFU+9L2hLEffhsycs3aF r/Nz9q77g0+W4klVprofqOqI38IMGl7grLFd2vfRAJfyntSP X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791926760098274536 X-GMAIL-MSGID: 1791926760098274536 We have several reports of vblank timeout messages. However after some debugging it was found that there might be different causes to that. To allow us to identify the DPU block that gets stuck, include the actual CTL_FLUSH value into the timeout message. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 2aa72b578764..6058706f03e4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -480,7 +480,7 @@ static int dpu_encoder_phys_vid_wait_for_commit_done( (hw_ctl->ops.get_flush_register(hw_ctl) == 0), msecs_to_jiffies(50)); if (ret <= 0) { - DPU_ERROR("vblank timeout\n"); + DPU_ERROR("vblank timeout: %x\n", hw_ctl->ops.get_flush_register(hw_ctl)); return -ETIMEDOUT; } From patchwork Mon Feb 26 02:28:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 206178 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp1831554dyb; Sun, 25 Feb 2024 18:29:05 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWLTOEeS3vpKWTr+x/TykvZiQzAA1PJLFoQpxnoiPaXhLlHKAbOKCbFbsgBWXrcNSnV25heWfx/0X5DIBRi4LqsW2hCxg== X-Google-Smtp-Source: AGHT+IEwQJ18Py7cpnTsAzC+6C8AaNBw1vE6rjyS6ikPnyypOcvBKPWBtw2kvBOvVJwa3xBX8zFg X-Received: by 2002:a05:6402:5186:b0:565:a6a4:2ecc with SMTP id q6-20020a056402518600b00565a6a42eccmr3273284edd.2.1708914545747; Sun, 25 Feb 2024 18:29:05 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708914545; cv=pass; d=google.com; s=arc-20160816; b=PO5hSy+Il4Fg0JtLY9gUzkL21aQjqYKClV7Z5W48O4dp0xaCbcVe7GJ7E0dtGNiHAr CXKBB2vavw5Bj95lq6ilmXszlEFQWLlWgUyjrOnU70co9L6Hr1Op9onOwM2kWi1vtpMb Ad6ayp0wHAWB/fZaGUnJwH/uiWlGBa9ZB1xORpT0bbVlXP1MGfmngnbHp8w7yHNbHuuf SddGL+Axo0Ljq2hXM+e2hVqirjSOhEy7RNlf+DeN75QP5L21AyZoIay1p1zucE9TzdSA OWkGGwdZc0jVqsDGgOaXVfLcNvD0zYOKHd3JWwFO8crp5btzYqsLHLJPCAY+OKZ87Qpc qgFQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=tV02SgjOyPaysYl2sk5YoJSWDm5/B3zf/otAVWITiRM=; fh=QNmprlBsilFHGUPbFrpLmzRosrfnjnajb9mWWAbHiIg=; b=WNla0KouA6YovTPwg4sOUKBARVXFxUEo25teYmojWlKszXIhECA5BCDJV21yw2sJo6 I9m8RL3BUMlnYuA17rD0IzcL6kn7E0HQYAOc9jhyRXfa1yzEBXenVFLK7vTTxNPiiDEi YEbccQfEteA+uLNu+MHZ6kmnvK7+w8baxGFxdpJVJIqbcPU8LvcmPceHoOJxfek2JBj4 QpXxOU4CyMhMIQsyR/4bpbES4PQjAaqfzl3bwt1AUvh0hkUHN477uP4/E5Tl/34+j+5q x11VIH3rj5VIdfjuj5K5Kqqa8Eo/IGc1YBDZkulIGCfVOPI9J1iNW07Volg7n65cZ0dG 6glA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u+ORK5Q+; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-80410-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-80410-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[2001:14ba:a00e:a300:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id u19-20020a2e8553000000b002d11ef66881sm713092ljj.91.2024.02.25.18.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 18:28:01 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 26 Feb 2024 04:28:00 +0200 Subject: [PATCH v4 2/3] drm/msm/dpu: split dpu_encoder_wait_for_event into two functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240226-fd-dpu-debug-timeout-v4-2-51eec83dde23@linaro.org> References: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> In-Reply-To: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Steev Klimaszewski , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7035; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=T/nDwtWkZJz2c5DNMYBy+x3YSHr3nDrORy9I9wO68cg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBl2/cvHa9Gq7SAR1+xB/8u/bpTCuKYCMf7BYQGF HzOBt4WNsaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZdv3LwAKCRCLPIo+Aiko 1VwwB/9j8v/rw9GsVqw0b0HfZ/eATkxlPA1WzAOSnqcDMjew1j+NOw1xQHiYxBDSRp5WjOhcCL9 E7Lok1h6uqF2Ob852mParQ5Fs4+6wMe5St6yZC3525Ktww7mNlYF8lLo6oCGWu1qG7gglJLD3MW iBunufpYen3vSFNDm6tiRnnp6s8xbi30Jp+XpJrBDHviAto9H5Zyl4U+3FicG4L1YGiyFQxEggA 82wF4q1gsXWswWAHQXEDAOXeZaZ499e1j/Ve0DlkvgklguqoV1nM9SRITIwoZvaZKg3ajSVPXtN 12KNcJOXyoXosKcGD+TvB43iBKKIOmKATF+Bxh7J5R/Z+EbD X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791926778707302698 X-GMAIL-MSGID: 1791926778707302698 Stop multiplexing several events via the dpu_encoder_wait_for_event() function. Split it into two distinct functions two allow separate handling of those events. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 70 +++++++++++++++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 22 ++------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- drivers/gpu/drm/msm/msm_drv.h | 10 ----- 4 files changed, 55 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 194dbb08331d..c99c7fd770f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1282,7 +1282,7 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, trace_dpu_enc_disable(DRMID(drm_enc)); /* wait for idle */ - dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); + dpu_encoder_wait_for_tx_complete(drm_enc); dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); @@ -2402,10 +2402,18 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, return &dpu_enc->base; } -int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, - enum msm_event_wait event) +/** + * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state + * @drm_enc: encoder pointer + * + * Wait for hardware to have flushed the current pending changes to hardware at + * a vblank or CTL_START. Physical encoders will map this differently depending + * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START. + * + * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise + */ +int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc) { - int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; struct dpu_encoder_virt *dpu_enc = NULL; int i, ret = 0; @@ -2419,23 +2427,47 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - switch (event) { - case MSM_ENC_COMMIT_DONE: - fn_wait = phys->ops.wait_for_commit_done; - break; - case MSM_ENC_TX_COMPLETE: - fn_wait = phys->ops.wait_for_tx_complete; - break; - default: - DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", - event); - return -EINVAL; + if (phys->ops.wait_for_commit_done) { + DPU_ATRACE_BEGIN("wait_for_commit_done"); + ret = phys->ops.wait_for_commit_done(phys); + DPU_ATRACE_END("wait_for_commit_done"); + if (ret) + return ret; } + } + + return ret; +} + +/** + * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel + * @drm_enc: encoder pointer + * + * Wait for the hardware to transfer all the pixels to the panel. Physical + * encoders will map this differently depending on the type: vid mode -> vsync_irq, + * cmd mode -> pp_done. + * + * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise + */ +int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc = NULL; + int i, ret = 0; + + if (!drm_enc) { + DPU_ERROR("invalid encoder\n"); + return -EINVAL; + } + dpu_enc = to_dpu_encoder_virt(drm_enc); + DPU_DEBUG_ENC(dpu_enc, "\n"); + + for (i = 0; i < dpu_enc->num_phys_encs; i++) { + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (fn_wait) { - DPU_ATRACE_BEGIN("wait_for_completion_event"); - ret = fn_wait(phys); - DPU_ATRACE_END("wait_for_completion_event"); + if (phys->ops.wait_for_tx_complete) { + DPU_ATRACE_BEGIN("wait_for_tx_complete"); + ret = phys->ops.wait_for_tx_complete(phys); + DPU_ATRACE_END("wait_for_tx_complete"); if (ret) return ret; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index fe6b1d312a74..0c928d1876e4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -93,25 +93,9 @@ void dpu_encoder_kickoff(struct drm_encoder *encoder); */ int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time); -/** - * dpu_encoder_wait_for_event - Waits for encoder events - * @encoder: encoder pointer - * @event: event to wait for - * MSM_ENC_COMMIT_DONE - Wait for hardware to have flushed the current pending - * frames to hardware at a vblank or ctl_start - * Encoders will map this differently depending on the - * panel type. - * vid mode -> vsync_irq - * cmd mode -> ctl_start - * MSM_ENC_TX_COMPLETE - Wait for the hardware to transfer all the pixels to - * the panel. Encoders will map this differently - * depending on the panel type. - * vid mode -> vsync_irq - * cmd mode -> pp_done - * Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise - */ -int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder, - enum msm_event_wait event); +int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder); + +int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_encoder); /* * dpu_encoder_get_intf_mode - get interface mode of the given encoder diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index d6412395bacc..26b5e54031d9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -476,7 +476,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, * mode panels. This may be a no-op for command mode panels. */ trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); - ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); + ret = dpu_encoder_wait_for_commit_done(encoder); if (ret && ret != -EWOULDBLOCK) { DPU_ERROR("wait for commit done returned %d\n", ret); break; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 762e13e2df74..91cf57f72321 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -74,16 +74,6 @@ enum msm_dsi_controller { #define MSM_GPU_MAX_RINGS 4 #define MAX_H_TILES_PER_DISPLAY 2 -/** - * enum msm_event_wait - type of HW events to wait for - * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW - * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel - */ -enum msm_event_wait { - MSM_ENC_COMMIT_DONE = 0, - MSM_ENC_TX_COMPLETE, -}; - /** * struct msm_display_topology - defines a display topology pipeline * @num_lm: number of layer mixers used From patchwork Mon Feb 26 02:28:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 206177 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp1831551dyb; Sun, 25 Feb 2024 18:29:04 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWoVH2OxD55oVr1qHe0KoCOaqEsUGhx1mbcWtq0Td8LWiPGYV5z4lPk9AyoUUmZMITPjTiAqturErqYkinPWG/oqu/AgA== X-Google-Smtp-Source: AGHT+IF/ptu1S6EFjuo38pnQvP8yC55c0id2xbPlmMk6xu2sHxAs75sRbVUy4TFAa0WnQVr52tai X-Received: by 2002:a05:6512:b0f:b0:512:b71d:3283 with SMTP id w15-20020a0565120b0f00b00512b71d3283mr4093466lfu.67.1708914544661; Sun, 25 Feb 2024 18:29:04 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708914544; cv=pass; d=google.com; s=arc-20160816; b=HcLU3dTDLHeopquOxTdnlJ4p+zERWIVeHbL4yG+EMPEfp3kFSOZpunMuWR/t+fIpfg S67Wpv0Y1WEvIq69IXzpsWrkzQQZVKBwxDVopXpJtQCqHrOrolnom3ya+yi8PfhuvMgk aTM5EkSsO1Z81HJRa/XK2L7aRKgbQVksaN8SoJCFzpKa1tdpadfAVxHZX7tvaUGOitoj n/scizWLMgGvnDGKHY4AyoTsb/fs9gz+RdE8pQoNACqnav3AybBCrbPLYp5AyiCE1+2h fbo5TR3VsNiSIh9AT+ynTyBo5E2MhmGGX3is2owJ7dMZzOP4gDvOE0fP6O+EJvulSLEF BLrg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=2zrSUS1oI8t8ANu34PzPLXDrLfaANT7YZx3X0xgYm0k=; fh=6VJs9BaSzPk4PJKLNMw04BcYmZ5SCzBjSAX/QgqDG+U=; b=HTKukoc4qc3o/pgVltdzfNfomM8FHR/DmJKvhUqYrxlsfb4ys0US2sPJmyN8nvKxPo wC3FFxinKS/jTRDacBb8jrjKcjFippEgiWFcH04SNaHfx0U4x8SW+1LoGWvSNU93EmBF +D6i/p3U344CpnrUP1PU6P6oadRyvbIr1qhmXS6sA9ru+YQBchjILeVLxkUsrs1DgZ9O 7XVVfl7ST1/GDJyPG2GjnFEFcLDeYmCKIxIkcRoiR3GFEvUf+b8nZDouONzz94sn1B1f t5msLfztAPzQMgq5x8Su1BV1tzR+GvrY2+2iYQ63fIKGfLqt3ED0dEoVH0z2YbbdIrx4 jgWA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EMhWeRLm; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-80411-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-80411-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[2001:14ba:a00e:a300:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id u19-20020a2e8553000000b002d11ef66881sm713092ljj.91.2024.02.25.18.28.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 18:28:02 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 26 Feb 2024 04:28:01 +0200 Subject: [PATCH v4 3/3] drm/msm/dpu: capture snapshot on the first commit_done timeout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240226-fd-dpu-debug-timeout-v4-3-51eec83dde23@linaro.org> References: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> In-Reply-To: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Steev Klimaszewski , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2187; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=DcJkg8xY9yU1wn7LtAuvfIPSDQOSJ+nJ+ORj2FrKvhg=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ+rt7/oaDYu8RNoPts+ZddbZcfsC6eypMzb3mR1w/7Pvs Ilev7RRJ6MxCwMjF4OsmCKLT0HL1JhNyWEfdkythxnEygQyhYGLUwAmskaV/X9y3YNSk7+/8w1W 3k3ge/RaK+Z1dUKrak9sw5z6AGvZsu/veVIYS0tnyPGsbQn9zFe81oF9y6/pC7fZWCwTXvHs6rM zk5jm23h+cVgTUdrp31ac26J6r51n0/sJd02dqiT+Jrbxz7yRo7nPJHO/1dar+kt+C9VtOzi7Mj qfOXd9opRLvIurnZTjktlim/Vapp2+uidq7uZb1fH3L2vwbgrq0X5YNrO1faLI3c5yw3u73vF2B HS5C/pJvS8xvFB9tuY5a8fz+D/fnXy07AOWeIrcq0vltRLXNzvNHz3BstBPz8j1r+FLh4bU+jvl SeGT7P/sl/ZdLuj6anHp6fO3QhWrhXZE+sbvmRBv6GEGAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791926777394194398 X-GMAIL-MSGID: 1791926777394194398 In order to debug commit_done timeouts, capture the devcoredump state when the first timeout occurs after the encoder has been enabled. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index c99c7fd770f6..c45edcde7ebc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -126,6 +126,8 @@ enum dpu_enc_rc_states { * @base: drm_encoder base class for registration with DRM * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes * @enabled: True if the encoder is active, protected by enc_lock + * @commit_done_timedout: True if there has been a timeout on commit after + * enabling the encoder. * @num_phys_encs: Actual number of physical encoders contained. * @phys_encs: Container of physical encoders managed. * @cur_master: Pointer to the current master in this mode. Optimization @@ -172,6 +174,7 @@ struct dpu_encoder_virt { spinlock_t enc_spinlock; bool enabled; + bool commit_done_timedout; unsigned int num_phys_encs; struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; @@ -1226,6 +1229,8 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, else if (disp_info->intf_type == INTF_DSI) dpu_enc->wide_bus_en = msm_dsi_wide_bus_enabled(priv->dsi[index]); + dpu_enc->commit_done_timedout = false; + mutex_lock(&dpu_enc->enc_lock); cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; @@ -2431,6 +2436,10 @@ int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc) DPU_ATRACE_BEGIN("wait_for_commit_done"); ret = phys->ops.wait_for_commit_done(phys); DPU_ATRACE_END("wait_for_commit_done"); + if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) { + dpu_enc->commit_done_timedout = true; + msm_disp_snapshot_state(drm_enc->dev); + } if (ret) return ret; }