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Reviewed-by: Manivannan Sadhasivam Acked-by: Rob Herring Signed-off-by: Krishna chaitanya chundru --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a93ab3b54066..5ad5c4cfd2a8 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -834,6 +834,8 @@ allOf: - qcom,pcie-sa8540p - qcom,pcie-sa8775p - qcom,pcie-sc8280xp + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 then: required: - interconnects From patchwork Fri Feb 23 14:47:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 205445 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp631521dyb; Fri, 23 Feb 2024 06:50:18 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWR8l5IlDRBJxVo225b5WbTkIqAo1WDWbhCOOEXe6cMQqrxsViUDokbBzebnehLuqbAhWnwYPqFAbG3gp/246Io4ayUJA== X-Google-Smtp-Source: AGHT+IGWW7/9SV4xiEWNrpR3yuM1emNCjy6Dhy4mpW8OmtsIA3tc0FXNntVZbO94bFlBwHGLRnn2 X-Received: by 2002:a62:5e07:0:b0:6e3:fe0b:527 with SMTP id s7-20020a625e07000000b006e3fe0b0527mr2094137pfb.30.1708699818046; Fri, 23 Feb 2024 06:50:18 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708699818; cv=pass; d=google.com; s=arc-20160816; b=HLaE6DNg4CNTEUinVR5MREaZyhizzeB+yKN+AzWx8sFJbCS1fRoX/NM9FSFKjJlZi4 rnMkhNBgu9sm/M9cofULzP7sNd9DccDqBUc8kw/J+C0AFtrdm89Xs1lvZY7Om7imNlIQ 5cPyUc9cQzztoXAO2aBZN0NAzpg8Tk9F2e0AMDYFRofU3ry8G1lrmi+PRmddIAvLxXzI Ly/crf8X4H8BGJC5VJ4652zOlDQMMVWJ7DqPOAL9mZxVB9ppNTFOycQkPKDKvA/vs428 HBftz4ZS4KMEadBOw3R6Sc+UKh8V6+ugg03ErbcPAjLdYdXKy8+xhUoLakGFk7Gx2D5z 4NBw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=3FogZb3RjOu/p0gevLn/krzCPQWG9ibDSved21e76mM=; fh=mLeyOiXXxJHJYs8dxImKbmNctx3gBpnhH0V2tKEUcOs=; b=BhPcNFwgJMfRXoqt3UFV9paAIgIav/6HfcUgOE4xGSBoq6QDD8cgETctjpX67W9WKl pdHKqvp7KlGGI04v7f3/ZOVAvlqDt3WwsuXMG6Mum7IPvCQmpngAkAyCGCC7Wl2/aQVH ml/96ounXEaxpd+3Szgg4CNexjgaatiNpNEbE73IQmZM8Hjbc4K2r/X9ii17LHGIQa0b CAzKjPT6PVXYS5DgBnC8smkKqyQ/6NZvVz+nWAfJTmm/lUsaN8ktc2DKNHkyMP5JeeHK TEJseT3Rg9VCfyWKew7jgPQDabme1hvNu3SmLlnp2Qel+T8uaMQxPwZ6SkgQFe3uocyp /kdw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=gMODVeD7; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-78532-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-78532-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 01e4dfc4babd..6b1d2e0d9d14 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1781,6 +1781,10 @@ pcie0: pcie@1c00000 { <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie0_phy>, @@ -1890,6 +1894,10 @@ pcie1: pcie@1c08000 { <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, <&pcie1_phy>, From patchwork Fri Feb 23 14:48:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 205446 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp631667dyb; Fri, 23 Feb 2024 06:50:35 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWf4J2Y5LrGVrg4HWJH9Sp41XGO4wPENc0LBvX1e/Lyu/FA5pxHXja6d82OZyFlujsQOp0O9+A1jorGeexhm0wOsw6f+g== X-Google-Smtp-Source: AGHT+IFHM5KGInLdu6RgAdOGQN/kyUQwDiIneUAkuu5S5hZNe87jIt2FyvGyTVLsD02lpESHSZeP X-Received: by 2002:a17:902:8c8a:b0:1db:ff7b:d202 with SMTP id t10-20020a1709028c8a00b001dbff7bd202mr33720plo.11.1708699834867; Fri, 23 Feb 2024 06:50:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708699834; cv=pass; d=google.com; s=arc-20160816; b=UkXCFkxKR4OOjGEO5C6Ux6shU5FIMe+q1u1AUVc3UmdcXBTrSBvqatOC2hg6y93TJ9 bPUuLw82ob/7BbU5YYPub/esHncJhOGjgsxXpCXTqF/dyUJQBS9KoP1YGqM8NTCnFaMX VSnNyOnjHmUBlWlgx6tsHpdqhCLDJgu0fnV8DwIxz8D5Ye0euVsR5JwZO94+BIvT77s1 cAgQO9znQtuWe6t3F43GvcpCHO4QGTgce7kbrc5JgYSfRcViRmjBsube7RQlH3XmQ6y+ RD47OSHELwuIFFqia+23UrglvkKBi7wn6oL0yUWtsIaAju6VtekTVYlRTGPpESmdnY2z laPQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=ioNHvIch7dV1L9IffTvensIGOBfZ95sdZbeKQgtA32w=; fh=5wKdp1w3tJCZLDv0YnxzrGW5vWq2MtI74/8F2XmS3Nc=; b=OCPPksKoD1kA3w2agPErruuNF6xCDqL3ZLdPif6NekZGPHnC2hrSzh8yyia0n0vteB l1qLBtPgs1ZeJv1HcZXTU/uS2mKVcL2RNMyytIjEnc0u0J2UtnafogzDkj6/InFUzTUW 9LhqWWFUu+eiyRBmunkZkP/TnpqvQFO9+2wMgsDguCWvJZYN6n8R/y4b7YfR5s+IAcGS Jt6PXKz9OrA7pVxS11LdPJ1tVMsWC3AXy3Az83bVHh6YjKxIjbgiP/Pda4auqUeGQYNh sOzu1zKsy+VloCU906NUF92zQ1ZcZiwzoB3JBBrTayPfu7XG3AatZ3syPtM9nz8hfAaH JxWw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=HdHpmetc; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-78533-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-78533-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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We are surviving because of other driver vote for this path. As there is less access on this path compared to PCIe to mem path add minimum vote i.e 1KBps bandwidth always. In suspend remove the disable this path after register space access is done. Reviewed-by: Bryan O'Donoghue Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 37 ++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 10f2d0bb86be..088ebd2e5865 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -240,6 +240,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; struct icc_path *icc_mem; + struct icc_path *icc_cpu; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; @@ -1372,6 +1373,9 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) if (IS_ERR(pcie->icc_mem)) return PTR_ERR(pcie->icc_mem); + pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); + if (IS_ERR(pcie->icc_cpu)) + return PTR_ERR(pcie->icc_cpu); /* * Some Qualcomm platforms require interconnect bandwidth constraints * to be set before enabling interconnect clocks. @@ -1381,7 +1385,18 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) */ ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + dev_err(pci->dev, "failed to set interconnect bandwidth for pcie-mem: %d\n", + ret); + return ret; + } + + /* + * The config space, BAR space and registers goes through cpu-pcie path. + * Set peak bandwidth to 1KBps as recommended by HW team for this path all the time. + */ + ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth for cpu-pcie: %d\n", ret); return ret; } @@ -1573,7 +1588,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev) */ ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); if (ret) { - dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret); + dev_err(dev, "Failed to set interconnect bandwidth for pcie-mem: %d\n", ret); return ret; } @@ -1597,6 +1612,18 @@ static int qcom_pcie_suspend_noirq(struct device *dev) pcie->suspended = true; } + /* Remove cpu path vote after all the register access is done */ + ret = icc_disable(pcie->icc_cpu); + if (ret) { + dev_err(dev, "failed to disable icc path of cpu-pcie: %d\n", ret); + if (pcie->suspended) { + qcom_pcie_host_init(&pcie->pci->pp); + pcie->suspended = false; + } + qcom_pcie_icc_opp_update(pcie); + return ret; + } + return 0; } @@ -1605,6 +1632,12 @@ static int qcom_pcie_resume_noirq(struct device *dev) struct qcom_pcie *pcie = dev_get_drvdata(dev); int ret; + ret = icc_enable(pcie->icc_cpu); + if (ret) { + dev_err(dev, "failed to enable icc path of cpu-pcie: %d\n", ret); + return ret; + } + if (pcie->suspended) { ret = qcom_pcie_host_init(&pcie->pci->pp); if (ret) From patchwork Fri Feb 23 14:48:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 205447 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp631965dyb; Fri, 23 Feb 2024 06:51:05 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVsY7O/xjRGDPjXBWmnC6d21T+COhTkDRXzuAgfRIBdzO27eBS++Z1dTBNMwDdMGj2hA6ww4dtt68d0zsM7PTNo3dKWVw== X-Google-Smtp-Source: AGHT+IGsWq2zFWi0W+LEkvt2+EEhx0QMvAMYD4tvTWFYouD2mVrsAj6K0KhCJ9/n/q2EJegX35fN X-Received: by 2002:a05:620a:444f:b0:787:a7ef:7c1e with SMTP id w15-20020a05620a444f00b00787a7ef7c1emr29404qkp.47.1708699865714; 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Adding the Operating Performance Points table allows to adjust power domain performance state and icc peak bw, depending on the PCIe gen speed and width. Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krishna chaitanya chundru --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 5ad5c4cfd2a8..e1d75cabb1a9 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -127,6 +127,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + operating-points-v2: true + opp-table: + type: object + required: - compatible - reg From patchwork Fri Feb 23 14:48:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 205448 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp632115dyb; Fri, 23 Feb 2024 06:51:22 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVqqhcgcZrgZQAwbwfZdpupSzqZlrFYaY2Ipnv9pirw/+9EZEU97kqIzw26Y1Yh7KaQ9m3eQz5BJZ1J/oIgCpW4yfWgWQ== X-Google-Smtp-Source: AGHT+IEuKX488DziqfW5ewb9JrEF3vcwRGJWM6sQMOyZe41xr+WbEf8Va5NZxVWB0bbgbvyy2edI X-Received: by 2002:ac8:6702:0:b0:42d:cfbe:33cf with SMTP id e2-20020ac86702000000b0042dcfbe33cfmr1862509qtp.60.1708699882602; Fri, 23 Feb 2024 06:51:22 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708699882; cv=pass; d=google.com; s=arc-20160816; b=zAYETyfI2wRwqG67OpSbrrJ5bEbes6Vjh29lrz0tWM09dpsJrIOs+gDuBObP4VwhWf cVZ4Za0AkWjY30jEKSli9Ox0Up7JtOiUabbXSGB6H1wEn99DzTwsaYDIIG8FoPDLKlxi kez55+uLDtnZJ2rFDO9P4TtexuBMFp2N1NNrMpyrBQ/56TTWiVNbVNVsDNOgIAj2DLQQ lPXt2nxfReMgnWzctLw7fDAq/MyFDO20Bn86yXnKlBeM/PBGLPEeZ76aIPMhxl6kLKnK gxOy9wHWXJC1eT4Tdgf5mifrSAz3+6xFeLjbvx1BM5xt+uVezuiZ2UB7dEwUAp/0HQPP k0XA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=MWJFlLU/eSswcHRepliMx7VnE186DBZvx1uc7BliI60=; fh=mLeyOiXXxJHJYs8dxImKbmNctx3gBpnhH0V2tKEUcOs=; b=DumRqzX/Dmy5dZU3Dmgw0Z7w0RgeJyuJ1m5iAHVQTNoZxGM1vOXUMcSRs7rpZy0HVM SKN7B/O8CsAmJ0LOCp58aXkzzv0/7pSvoxU1p5O6ERH/dwZZDk5XKkdaC3bfGF/OzfFp vu2eSH1lmo+emeJ+ZdhXrxU4nCFkrOUbInPOLbQnvN3/Nx0tWy6GQHY3P46Z2WlOg8wf ts4YajPeBxsfvZKEKxIomlm2qvdBqLkmXVzw45l2m7rNJky0ljGbxSO65YzQWKhE964U Lq7/rB36MhwfILrVAnvFBCTw5HnKsv2Hsx7mklvXQMBJ8UmA7bLMIOVMf1DFlZi11HD5 hLQA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Mv3QhKHA; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-78536-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-78536-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Add the OPP table support to specify RPMH performance states and interconnect peak bandwidth. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 74 ++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 6b1d2e0d9d14..662f2129f20d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1827,7 +1827,32 @@ pcie0: pcie@1c00000 { pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + }; + }; pcie0_phy: phy@1c06000 { @@ -1938,7 +1963,56 @@ pcie1: pcie@1c08000 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1x2 GEN 2x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3x2 GEN 4x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + }; pcie1_phy: phy@1c0e000 { From patchwork Fri Feb 23 14:48:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 205449 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp632274dyb; Fri, 23 Feb 2024 06:51:40 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXFLI/PBCzDngscw/4OWn0voXwH1qM0y2uNldP02PoPTuME3cPGTfoQzu6aQFvOrjim6zYIGDhIh5XC5ADQvR2m6+wY8g== X-Google-Smtp-Source: AGHT+IFp4vGFXrgn4thWaIFvVx9/BM4vERrtASeaVgfLQuA/UwwVg1isFxdLfYpokxAa3HrOzAmR X-Received: by 2002:ac8:5e52:0:b0:42d:ad3f:6c3f with SMTP id i18-20020ac85e52000000b0042dad3f6c3fmr2825487qtx.49.1708699900310; Fri, 23 Feb 2024 06:51:40 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708699900; cv=pass; d=google.com; s=arc-20160816; b=mdy9RduHx5pVMxkJGbx4hPBx7WHcmmQDz+oSYxbwPJ9cK1KACLmbAalN6oN8h7H3rp fHEa6DxnN+VcniepKcHZWVm5DO6yTe+rNPAK7CcJ4hHu43p1z8Z88okWPqlAJmCr5TFu 8HjCTPNNssbOppvRaN8IQ6KFM4qjNqAxwETce/hyBl5Vx/Fi5C3DM3uGC/GZAclNt5Ul Mm9wvlbdGTx7AkjNXlFDU0PsjltD/2edRjiEbGe6BxkCwEcLDO6HjUX70bvdVkzQWY6O ZEi73iIOOOQX86IznjanC6Z/eXhr+dG9k7hKXJo692kE9KZvb8RoojXriG0IF8kTsNkb mSIQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=wbeG60PGiWYs8AGZnrSHodCHU/ETFy6J6eK7ZeNFV5o=; fh=mLeyOiXXxJHJYs8dxImKbmNctx3gBpnhH0V2tKEUcOs=; b=OE3ElKGn1HbQ+KqR7HiKMyLffpdYkr6mXx6yb4pccuMP+yMomxoHc2jcxlPhr/bdHv FfJ6IUxFrqma2iDjJISLgxgDvgAaCXeeTYo4jim3yGNzaCP9thINKNaUOQRLofQ0uiLg Iz429kT4MEvrT9ijfY6EaeCJUuSZb0RKSj6gD3O/ecSPFTvghoUfghCZ9jm+m0Y/zc17 V7QTdGo9hJogTALt+Lfwz64sVvDzXfxJOsO7jUs9LVsYy2aYMleVO5kC1vv2itXZPGpM qID+U63B4HBc9WrpQVCdaDJLTWd/VsYSNdMQCw5ehnnFpyNrtA3N4dgW7jTHV9WCnjxT LTsA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=UQhEbcjp; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-78537-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-78537-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Create a new macro to convert from MBps to frequency. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/pci.c | 19 +------------------ drivers/pci/pci.h | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d8f11a078924..b441ab862a8d 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6309,24 +6309,7 @@ int pcie_link_speed_mbps(struct pci_dev *pdev) if (err) return err; - switch (to_pcie_link_speed(lnksta)) { - case PCIE_SPEED_2_5GT: - return 2500; - case PCIE_SPEED_5_0GT: - return 5000; - case PCIE_SPEED_8_0GT: - return 8000; - case PCIE_SPEED_16_0GT: - return 16000; - case PCIE_SPEED_32_0GT: - return 32000; - case PCIE_SPEED_64_0GT: - return 64000; - default: - break; - } - - return -EINVAL; + return pcie_link_speed_to_mbps(to_pcie_link_speed(lnksta)); } EXPORT_SYMBOL(pcie_link_speed_mbps); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2336a8d1edab..82e715ebe383 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -282,6 +282,30 @@ void pci_bus_put(struct pci_bus *bus); (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 0) +static inline int pcie_link_speed_to_mbps(enum pci_bus_speed speed) +{ + switch (speed) { + case PCIE_SPEED_2_5GT: + return 2500; + case PCIE_SPEED_5_0GT: + return 5000; + case PCIE_SPEED_8_0GT: + return 8000; + case PCIE_SPEED_16_0GT: + return 16000; + case PCIE_SPEED_32_0GT: + return 32000; + case PCIE_SPEED_64_0GT: + return 64000; + default: + break; + } + + return -EINVAL; +} + +#define PCIE_MBS2FREQ(speed) (pcie_link_speed_to_mbps(speed) * 1000) + const char *pci_speed_string(enum pci_bus_speed speed); enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); From patchwork Fri Feb 23 14:48:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 205450 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp632456dyb; Fri, 23 Feb 2024 06:52:02 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVsH7qR/FLTx4sl9nJikeyKP9ZsXGzM16+GSU8ybsHYJKMRNRwrn9+Nsw0YaS+Kaxq5s9LQW+grLviGV9WGotiuOe2hOw== X-Google-Smtp-Source: AGHT+IHzm52cHe8RBi1mV0ctPMCQHoRgeSriY16qR6UHcmTePKGgKPjuyfpQQV8kscJNbEVcdZGK X-Received: by 2002:a17:906:1353:b0:a3d:1df3:9d35 with SMTP id x19-20020a170906135300b00a3d1df39d35mr30291ejb.23.1708699922138; Fri, 23 Feb 2024 06:52:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708699922; cv=pass; d=google.com; s=arc-20160816; b=JbwBT0yYs2YqFBTpScMWJnWpJyv/RxLKZUBXmiF8zO5Ed9n8EXoCl4DlD4Gg4rTiuD MPIilHQBqgN5gu5Grs/IR3JsX6bPalfXyk99M9AFUkp15TY8gizC6w39MMAOFKpY4Oyv 0PLAuiOkTP7yxK5usdWYNqChEFs0eqHY8vUO5KfVYtJjbpeGqjTLw6QZI03ER5vkeyVU RwMUXo+YE8s/fyO0IkvV1nQE6KRIQlr80KAlpYskyW0ZzjJ/ERykj41q/eYwPmklVRg3 RQJo1olhbufobmBHjy2wl9KFB31MPNkss/xYk/zQA6GyqkFplxQR++RZ70OHO8AU3GPW xOSg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=bIFvd5a7Gq+s8Ic6RoQhPi68JfGBADm7tLEEN1LBupU=; fh=mLeyOiXXxJHJYs8dxImKbmNctx3gBpnhH0V2tKEUcOs=; b=hXHi4onaeu9aXYNW2bRZqFzik1ltl5Yuy8RlsF8+jSMeNkHEhQKcUwTiQ1qJlGkxuU 6uQAzz+wonDETasqdpcxF9ia/xa1Wote8+n9WiFOWAL8a50G/lzseD5/PL4XnXaxCjwK I6GJPszCUuuvLPgSb//iKVCYmFr1jKbPwRgQFUFtA1pXlNMX+rubdaO2Y3xTfigKUBvE PCpdN+FNl7Abqpe8iKcWoaS7SPIVYE5xBMkTxS2ZFA1/qEIY7XWC8jYGPeVcCsV9dO/f WKDImy+Rzo7wwmIe0wrBFVcRd4yrSWDEf33FFR4bqfibpQ/P5tQGQOWLaEJyVQ+tLjo0 LxuA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=VJ1AqxM7; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-78538-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-78538-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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PCIe controller can operate on different RPMh performance state of power domain based up on the speed of the link. And this performance state varies from target to target. It is manadate to scale the performance state based up on the PCIe speed link operates so that SoC can run under optimum power conditions. Add Operating Performance Points(OPP) support to vote for RPMh state based upon the speed link is operating. OPP can handle ICC bw voting also, so move ICC bw voting through OPP framework if OPP entries are present. In PCIe certain speeds like GEN1x2 & GEN2x1 or GEN3x2 & GEN4x1 use same bw and frequency and thus the OPP entry, so use frequency based search to reduce number of entries in the OPP table. Don't initialize ICC if OPP is supported. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 75 +++++++++++++++++++++++++++------- 1 file changed, 61 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 088ebd2e5865..c608bec8b9cb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -244,6 +245,7 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; + bool opp_supported; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -1404,16 +1406,14 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) return 0; } -static void qcom_pcie_icc_update(struct qcom_pcie *pcie) +static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; - u32 offset, status; + u32 offset, status, freq; + struct dev_pm_opp *opp; int speed, width; int ret; - if (!pcie->icc_mem) - return; - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); @@ -1424,11 +1424,26 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); - ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); - if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", - ret); + if (pcie->opp_supported) { + freq = PCIE_MBS2FREQ(pcie_link_speed[speed]); + + opp = dev_pm_opp_find_freq_exact(pci->dev, freq * width, true); + if (!IS_ERR(opp)) { + ret = dev_pm_opp_set_opp(pci->dev, opp); + if (ret) + dev_err(pci->dev, "Failed to set opp: freq %ld ret %d\n", + dev_pm_opp_get_freq(opp), ret); + dev_pm_opp_put(opp); + } + } else { + ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth for pcie-mem: %d\n", + ret); + } } + + return; } static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) @@ -1471,8 +1486,10 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; + unsigned long max_freq = INT_MAX; struct device *dev = &pdev->dev; struct qcom_pcie *pcie; + struct dev_pm_opp *opp; struct dw_pcie_rp *pp; struct resource *res; struct dw_pcie *pci; @@ -1539,9 +1556,36 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } - ret = qcom_pcie_icc_init(pcie); - if (ret) + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(dev); + if (ret && ret != -ENODEV) { + dev_err_probe(dev, ret, "Failed to add OPP table\n"); goto err_pm_runtime_put; + } + + /* + * Use highest OPP here if the OPP table is present. At the end of the probe(), + * OPP will be updated using qcom_pcie_icc_opp_update(). + */ + if (ret != -ENODEV) { + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (!IS_ERR(opp)) { + ret = dev_pm_opp_set_opp(dev, opp); + if (ret) + dev_err_probe(pci->dev, ret, + "Failed to set opp: freq %ld\n", + dev_pm_opp_get_freq(opp)); + dev_pm_opp_put(opp); + } + pcie->opp_supported = true; + } + + /* Skip ICC init if OPP is supported as ICC bw vote is handled by OPP framework */ + if (!pcie->opp_supported) { + ret = qcom_pcie_icc_init(pcie); + if (ret) + goto err_pm_runtime_put; + } ret = pcie->cfg->ops->get_resources(pcie); if (ret) @@ -1561,7 +1605,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } - qcom_pcie_icc_update(pcie); + qcom_pcie_icc_opp_update(pcie); if (pcie->mhi) qcom_pcie_init_debugfs(pcie); @@ -1612,7 +1656,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev) pcie->suspended = true; } - /* Remove cpu path vote after all the register access is done */ + /* Remove CPU path vote after all the register access is done */ ret = icc_disable(pcie->icc_cpu); if (ret) { dev_err(dev, "failed to disable icc path of cpu-pcie: %d\n", ret); @@ -1624,6 +1668,9 @@ static int qcom_pcie_suspend_noirq(struct device *dev) return ret; } + if (pcie->opp_supported) + dev_pm_opp_set_opp(pcie->pci->dev, NULL); + return 0; } @@ -1646,7 +1693,7 @@ static int qcom_pcie_resume_noirq(struct device *dev) pcie->suspended = false; } - qcom_pcie_icc_update(pcie); + qcom_pcie_icc_opp_update(pcie); return 0; }