From patchwork Fri Feb 23 09:43:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot2 for Thomas Gleixner X-Patchwork-Id: 205268 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp481313dyb; Fri, 23 Feb 2024 01:53:53 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUX3BLE9CGuLLL+BFJ5iTSgpVMmNnysTKvL6rEAW1Z2MwuE3L0Wc9nfKDo/TK+Y3rUt7UypvZCKPrsgBKK89cGI0pJKOg== X-Google-Smtp-Source: AGHT+IFHr3N1okfFtMvKaBHprXC/TugbW/ciF4nqfgkQC2q9nr+2jZkIcDGjIZ2gdSTVGmC+I8Sb X-Received: by 2002:a05:6a20:d81a:b0:1a0:e19e:b91e with SMTP id iv26-20020a056a20d81a00b001a0e19eb91emr999389pzb.52.1708682033767; Fri, 23 Feb 2024 01:53:53 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708682033; cv=pass; d=google.com; s=arc-20160816; b=hFxJYkhozu07KICKw2AwwEQN2/WzNcllI6Od4K8FloFGiUW2NDkiQiPNDH9allJx+v hJA+bh7sQyaYApbgeIxWO0lWdVV2+Of2t3JEhujynnbD64jOcUC9ZaY8goZm57FUdw5w 8rdCxZHxtNSM96vXX+jICCZHIGK728QX4AVdB93r0oTXT2fgXK2w1tAl151oexq9XFP1 x//K5eDNwIAqLLFUZVcQms5M5Sszwu6xmKLBwziIoo27C4ULVNc+XN5yEMTWuL/ru3DB PJmUIjcIHi0lbLuOOPPDO0yISjimdFs1QYh+HGZo0tAwVS5tB4whKbqi260HaiVuByRn f79A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:precedence:robot-unsubscribe:robot-id :message-id:mime-version:list-unsubscribe:list-subscribe:list-id :precedence:references:in-reply-to:cc:subject:to:reply-to:sender :from:dkim-signature:dkim-signature:date; bh=S2PMHFcB61+S0C8W7aEcqQTPMtADdl+pSwMYbvkIl9Y=; fh=546OEPtoZUYjWwSPOd/hX3L3p6biPmSjgTUnSRYaJpA=; b=AX3nW+T5DGnP4rcsKUZEWHxW+l5FiF9oTZSMclz0jKV7ZLzWQPjx2OmSNg4DsqDznJ DAolhIcZw6lU45lxnQVwM1itoFDBxxPj38XYdeyoQV/dcqnWQTx+GvDdcaQ0d4cST4Sv h8i68md/i6bk5eXjaGWyf4PcEz5iDv8jvIrXta+VrGJBt2MC7H/lBZwgvwaEe7ioGowL WMzMPOXYFhk7978d1/mdNcBXBQcSkgZasPcDTXKn/DhaSOtVYsOyhphPF24VMG/NjMAY pST5c4v1vUUaCh5xsbc4CQQ4B9xEHHDMOvPS1iJRsD8vQblpXfk9D0rRaMda+JB8wnyG vTpA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=CLkG47L4; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=kyd5PNDA; arc=pass (i=1 spf=pass spfdomain=linutronix.de dkim=pass dkdomain=linutronix.de dmarc=pass fromdomain=linutronix.de); spf=pass (google.com: domain of linux-kernel+bounces-78057-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-78057-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [147.75.48.161]) by mx.google.com with ESMTPS id f12-20020a17090a654c00b002997165bd74si882256pjs.83.2024.02.23.01.53.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Feb 2024 01:53:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-78057-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=CLkG47L4; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=kyd5PNDA; arc=pass (i=1 spf=pass spfdomain=linutronix.de dkim=pass dkdomain=linutronix.de dmarc=pass fromdomain=linutronix.de); spf=pass (google.com: domain of linux-kernel+bounces-78057-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-78057-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 0119AB2535E for ; Fri, 23 Feb 2024 09:46:41 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BADD95D736; Fri, 23 Feb 2024 09:44:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CLkG47L4"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kyd5PNDA" Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DAA65CDF4; Fri, 23 Feb 2024 09:44:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708681448; cv=none; b=lo3RCuifs9ZnG9MCrWCdnWAqj5aOuP/o8Tj8Zfa++gIxLARCl1nIQTICgSA/MxhT/A0Ks4LDA+7lwhGqufO4bs3twAqXKIv/3dvGkWKNUlO9ClFIgVGRiOfYb6Foh8i8mLSJXn5O7ruJktG9Tljygha2LVmFEqtSdg9ovwqC6tA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708681448; c=relaxed/simple; bh=AlEbOermp1F8Q0iqHlsvfS2M6+5oyBEWffzt7PjJrJ8=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=IfQ9TsReDQ4j+JosJ1vGQ5dTw4vb6xH87LobBm9oDv5Ou8F2qZ6t90WwVe/OSqHnp6pfg7P6ZTr3DpAx81kSHNFxt4HjZFCs4/gLQeRA2bwetRpQDAOoC9NiRhm5M8VRqSxAB7c+AIaX5vrd0Hw/I2QLjjsuhThCz31FEWWsmX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CLkG47L4; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=kyd5PNDA; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Date: Fri, 23 Feb 2024 09:43:58 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1708681439; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S2PMHFcB61+S0C8W7aEcqQTPMtADdl+pSwMYbvkIl9Y=; b=CLkG47L4XHhZD4PJEV5f/d11RzCLduhLuu9Mm4zBlsbMI4CZiDSxT5ug8p9ORvxM/ixKZ2 7KtEMAvwQHhTBhltmW5XCdzhsF32Nl1GEdbOG2aoQ7bMa+HcbiDHg5DBgyFgeBKFhoucPH tezDax9FCmEv1YSSQrlraRtjaVRQedZ/4RrgDXRm+eXQz7A49LI7bvpNKj48cCBFZmcEN9 hHRawsn/jwo3fQ1T0uy1A2L/98OjqOGoNBJFXFGdDKy8vX3I4kb6hVXAPjsBGVUu/dACN6 drnLQCD4SNmlp/38gXV9nCkTQAB0S8RVU0k+HKfjIvK5v2vdAhRXWpwZHeUsKA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1708681439; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S2PMHFcB61+S0C8W7aEcqQTPMtADdl+pSwMYbvkIl9Y=; b=kyd5PNDAkiiirulIbEms9VKPyeLmdmzbOU2iXISycjnr6kW+LC/aB4zivP3rfAKW9Qy+e+ GGqlg/LoSz0r6cAw== From: "tip-bot2 for Anup Patel" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/msi] irqchip/sifive-plic: Convert PLIC driver into a platform driver Cc: Anup Patel , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20240222094006.1030709-2-apatel@ventanamicro.com> References: <20240222094006.1030709-2-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170868143850.398.12304285170769867752.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791591559002948295 X-GMAIL-MSGID: 1791682972471568377 The following commit has been merged into the irq/msi branch of tip: Commit-ID: 8ec99b033147ef3bb8f0a560c24eb1baec3bc0be Gitweb: https://git.kernel.org/tip/8ec99b033147ef3bb8f0a560c24eb1baec3bc0be Author: Anup Patel AuthorDate: Thu, 22 Feb 2024 15:09:49 +05:30 Committer: Thomas Gleixner CommitterDate: Fri, 23 Feb 2024 10:18:43 +01:00 irqchip/sifive-plic: Convert PLIC driver into a platform driver The PLIC driver does not require very early initialization so convert it into a platform driver. After conversion, the PLIC driver is probed after CPUs are brought-up so setup cpuhp state after context handler of all online CPUs are initialized otherwise PLIC driver crashes for platforms with multiple PLIC instances. Signed-off-by: Anup Patel Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240222094006.1030709-2-apatel@ventanamicro.com --- drivers/irqchip/irq-sifive-plic.c | 101 +++++++++++++++++------------ 1 file changed, 61 insertions(+), 40 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 5b7bc4f..7400a07 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -64,6 +64,7 @@ #define PLIC_QUIRK_EDGE_INTERRUPT 0 struct plic_priv { + struct device *dev; struct cpumask lmask; struct irq_domain *irqdomain; void __iomem *regs; @@ -406,30 +407,50 @@ static int plic_starting_cpu(unsigned int cpu) return 0; } -static int __init __plic_init(struct device_node *node, - struct device_node *parent, - unsigned long plic_quirks) +static const struct of_device_id plic_match[] = { + { .compatible = "sifive,plic-1.0.0" }, + { .compatible = "riscv,plic0" }, + { .compatible = "andestech,nceplic100", + .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, + { .compatible = "thead,c900-plic", + .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, + {} +}; + +static int plic_probe(struct platform_device *pdev) { int error = 0, nr_contexts, nr_handlers = 0, i; - u32 nr_irqs; - struct plic_priv *priv; + struct device *dev = &pdev->dev; + unsigned long plic_quirks = 0; struct plic_handler *handler; + struct plic_priv *priv; + bool cpuhp_setup; unsigned int cpu; + u32 nr_irqs; + + if (is_of_node(dev->fwnode)) { + const struct of_device_id *id; + + id = of_match_node(plic_match, to_of_node(dev->fwnode)); + if (id) + plic_quirks = (unsigned long)id->data; + } priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; + priv->dev = dev; priv->plic_quirks = plic_quirks; - priv->regs = of_iomap(node, 0); + priv->regs = of_iomap(to_of_node(dev->fwnode), 0); if (WARN_ON(!priv->regs)) { error = -EIO; goto out_free_priv; } error = -EINVAL; - of_property_read_u32(node, "riscv,ndev", &nr_irqs); + of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", &nr_irqs); if (WARN_ON(!nr_irqs)) goto out_iounmap; @@ -439,13 +460,13 @@ static int __init __plic_init(struct device_node *node, if (!priv->prio_save) goto out_free_priority_reg; - nr_contexts = of_irq_count(node); + nr_contexts = of_irq_count(to_of_node(dev->fwnode)); if (WARN_ON(!nr_contexts)) goto out_free_priority_reg; error = -ENOMEM; - priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1, - &plic_irqdomain_ops, priv); + priv->irqdomain = irq_domain_add_linear(to_of_node(dev->fwnode), nr_irqs + 1, + &plic_irqdomain_ops, priv); if (WARN_ON(!priv->irqdomain)) goto out_free_priority_reg; @@ -455,7 +476,7 @@ static int __init __plic_init(struct device_node *node, int cpu; unsigned long hartid; - if (of_irq_parse_one(node, i, &parent)) { + if (of_irq_parse_one(to_of_node(dev->fwnode), i, &parent)) { pr_err("failed to parse parent for context %d.\n", i); continue; } @@ -491,7 +512,7 @@ static int __init __plic_init(struct device_node *node, /* Find parent domain and register chained handler */ if (!plic_parent_irq && irq_find_host(parent.np)) { - plic_parent_irq = irq_of_parse_and_map(node, i); + plic_parent_irq = irq_of_parse_and_map(to_of_node(dev->fwnode), i); if (plic_parent_irq) irq_set_chained_handler(plic_parent_irq, plic_handle_irq); @@ -533,20 +554,29 @@ done: /* * We can have multiple PLIC instances so setup cpuhp state - * and register syscore operations only when context handler - * for current/boot CPU is present. + * and register syscore operations only once after context + * handlers of all online CPUs are initialized. */ - handler = this_cpu_ptr(&plic_handlers); - if (handler->present && !plic_cpuhp_setup_done) { - cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, - "irqchip/sifive/plic:starting", - plic_starting_cpu, plic_dying_cpu); - register_syscore_ops(&plic_irq_syscore_ops); - plic_cpuhp_setup_done = true; + if (!plic_cpuhp_setup_done) { + cpuhp_setup = true; + for_each_online_cpu(cpu) { + handler = per_cpu_ptr(&plic_handlers, cpu); + if (!handler->present) { + cpuhp_setup = false; + break; + } + } + if (cpuhp_setup) { + cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, + "irqchip/sifive/plic:starting", + plic_starting_cpu, plic_dying_cpu); + register_syscore_ops(&plic_irq_syscore_ops); + plic_cpuhp_setup_done = true; + } } - pr_info("%pOFP: mapped %d interrupts with %d handlers for" - " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); + pr_info("%pOFP: mapped %d interrupts with %d handlers for %d contexts.\n", + to_of_node(dev->fwnode), nr_irqs, nr_handlers, nr_contexts); return 0; out_free_enable_reg: @@ -563,20 +593,11 @@ out_free_priv: return error; } -static int __init plic_init(struct device_node *node, - struct device_node *parent) -{ - return __plic_init(node, parent, 0); -} - -IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); -IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ - -static int __init plic_edge_init(struct device_node *node, - struct device_node *parent) -{ - return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT)); -} - -IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init); -IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init); +static struct platform_driver plic_driver = { + .driver = { + .name = "riscv-plic", + .of_match_table = plic_match, + }, + .probe = plic_probe, +}; +builtin_platform_driver(plic_driver);