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Thu, 22 Feb 2024 13:22:07 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 22 Feb 2024 13:22:07 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 794AE3F719F; Thu, 22 Feb 2024 11:17:23 -0800 (PST) From: Elad Nachman To: , , , , CC: , Subject: [PATCH v3 1/2] mmc: xenon: fix PHY init clock stability Date: Thu, 22 Feb 2024 21:17:13 +0200 Message-ID: <20240222191714.1216470-2-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240222191714.1216470-1-enachman@marvell.com> References: <20240222191714.1216470-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: bYNSWMlj2hCJ90jrCB0PWeMEwubrjedi X-Proofpoint-ORIG-GUID: bYNSWMlj2hCJ90jrCB0PWeMEwubrjedi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-22_15,2024-02-22_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791640591138244215 X-GMAIL-MSGID: 1791640591138244215 From: Elad Nachman Each time SD/mmc phy is initialized, at times, in some of the attempts, phy fails to completes its initialization which results into timeout error. Per the HW spec, it is a pre-requisite to ensure a stable SD clock before a phy initialization is attempted. Fixes: 06c8b667ff5b ("mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC") Acked-by: Adrian Hunter Cc: stable@vger.kernel.org Signed-off-by: Elad Nachman --- drivers/mmc/host/sdhci-xenon-phy.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c index 8cf3a375de65..c3096230a969 100644 --- a/drivers/mmc/host/sdhci-xenon-phy.c +++ b/drivers/mmc/host/sdhci-xenon-phy.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include "sdhci-pltfm.h" @@ -216,6 +217,19 @@ static int xenon_alloc_emmc_phy(struct sdhci_host *host) return 0; } +static int xenon_check_stability_internal_clk(struct sdhci_host *host) +{ + u32 reg; + int err; + + err = read_poll_timeout(sdhci_readw, reg, reg & SDHCI_CLOCK_INT_STABLE, + 1100, 20000, false, host, SDHCI_CLOCK_CONTROL); + if (err) + dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n"); + + return err; +} + /* * eMMC 5.0/5.1 PHY init/re-init. * eMMC PHY init should be executed after: @@ -232,6 +246,11 @@ static int xenon_emmc_phy_init(struct sdhci_host *host) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; + int ret = xenon_check_stability_internal_clk(host); + + if (ret) + return ret; + reg = sdhci_readl(host, phy_regs->timing_adj); reg |= XENON_PHY_INITIALIZAION; sdhci_writel(host, reg, phy_regs->timing_adj); From patchwork Thu Feb 22 19:17:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 205173 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp319234dyb; Thu, 22 Feb 2024 17:16:31 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVIDCyN2Ox4U28E1zZoNqt5xolZrOHARwLPeYQbWF4FqgZZ1xG94rjLGoeO4ezaStdz016ka5HhhEsbLpFSkkU8p4VPjg== X-Google-Smtp-Source: AGHT+IEPhbJr66fJs4jGUxm9JGJlYAVetAxrlyz31wLHsGjGsOjpgyRSZOeMeF0D6GJyJpoOnhGo X-Received: by 2002:a17:906:71da:b0:a3f:7e2:84cc with SMTP id i26-20020a17090671da00b00a3f07e284ccmr351682ejk.6.1708650991718; Thu, 22 Feb 2024 17:16:31 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708650991; cv=pass; d=google.com; s=arc-20160816; b=gyfNv7A3H7J0JaP88tIs5IGHnncMUXIot7uf0btGI0+qlGsSh0VdKIPAe2ztCSjkkW JsSFg1a1gtZ0I3o4YOIgyq7xo+NinXCOY2hEXmkDrbCF44cLL2g8Br/q6MMsOWCjPYW9 tE1BzJyzxKA/Gjf1z4OA+VUQOIEutI96Yvv0roVF2lhDDiLkq406HnYMM8Ydzo3qJFI4 2dtB8pPR9XcTK1vPlSGzdulANRla6W5+j4/IH76vFBNNi+tEUYaUb8VVGGyFIs0hgsv1 uu6YVNqzojfKIgXkLYnAbUj3vck2VAVnmxE78mKTpQiDvNr4L7DzaQI3FPrDYV5Mn5M0 2kXw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=HrWkWQ/kQqJLWulKnPDqvSBRFwR5PnOwvL6KFpRQKR4=; fh=M1RO158Os50Y+7jr9jkWOUUFaYJ+PXra7vMPvfQbgto=; b=BY3N10WOrxHvMnbuxjNWTYhuHXAx3UzGw39Hi/0/FdGYKTPPOqGt+FTJ5nymt3KHLW O57dyhpLGWiuGc2QClIxByd0THc3lydM/teCJoObwBLVP++z3y6wVDVh2IPqqU4nODy3 TBL9XRebvau79Oc7JWPAp2JIS9iN8V8QmjVTE5s4MgEc0mXpTUdAu2U6dd8ozJEemTUx KO4ZucGt+ifEPLYOoc3BkTXU0WEe021Y7Sx5gOxZrbPpDnLlIwj5abX86vCb79jYsL0S cj17uZO6zQqmBcrSjhF4SOvuDFtMQhtg5R4wK1yRKzOGKGeObS1ueNxnQUnycQnEvgse ibYg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=R90OHXsV; arc=pass (i=1 dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: domain of linux-kernel+bounces-77240-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77240-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Thu, 22 Feb 2024 11:17:28 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 22 Feb 2024 11:17:28 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 022903F71A7; Thu, 22 Feb 2024 11:17:25 -0800 (PST) From: Elad Nachman To: , , , , CC: , Subject: [PATCH v3 2/2] mmc: xenon: add timeout for PHY init complete Date: Thu, 22 Feb 2024 21:17:14 +0200 Message-ID: <20240222191714.1216470-3-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240222191714.1216470-1-enachman@marvell.com> References: <20240222191714.1216470-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: DACLmym6ivxWFILuGJkemDOU3edTaUwM X-Proofpoint-ORIG-GUID: DACLmym6ivxWFILuGJkemDOU3edTaUwM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-22_15,2024-02-22_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791650422579790090 X-GMAIL-MSGID: 1791650422579790090 From: Elad Nachman AC5X spec says PHY init complete bit must be polled until zero. We see cases in which timeout can take longer than the standard calculation on AC5X, which is expected following the spec comment above. According to the spec, we must wait as long as it takes for that bit to toggle on AC5X. Cap that with 100 delay loops so we won't get stuck forever. Fixes: 06c8b667ff5b ("mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC") Acked-by: Adrian Hunter Cc: stable@vger.kernel.org Signed-off-by: Elad Nachman --- drivers/mmc/host/sdhci-xenon-phy.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c index c3096230a969..cc9d28b75eb9 100644 --- a/drivers/mmc/host/sdhci-xenon-phy.c +++ b/drivers/mmc/host/sdhci-xenon-phy.c @@ -110,6 +110,8 @@ #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18) #define XENON_LOGIC_TIMING_VALUE 0x00AA8977 +#define XENON_MAX_PHY_TIMEOUT_LOOPS 100 + /* * List offset of PHY registers and some special register values * in eMMC PHY 5.0 or eMMC PHY 5.1 @@ -278,18 +280,27 @@ static int xenon_emmc_phy_init(struct sdhci_host *host) /* get the wait time */ wait /= clock; wait++; - /* wait for host eMMC PHY init completes */ - udelay(wait); - reg = sdhci_readl(host, phy_regs->timing_adj); - reg &= XENON_PHY_INITIALIZAION; - if (reg) { + /* + * AC5X spec says bit must be polled until zero. + * We see cases in which timeout can take longer + * than the standard calculation on AC5X, which is + * expected following the spec comment above. + * According to the spec, we must wait as long as + * it takes for that bit to toggle on AC5X. + * Cap that with 100 delay loops so we won't get + * stuck here forever: + */ + + ret = read_poll_timeout(sdhci_readl, reg, + !(reg & XENON_PHY_INITIALIZAION), + wait, XENON_MAX_PHY_TIMEOUT_LOOPS * wait, + false, host, phy_regs->timing_adj); + if (ret) dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", - wait); - return -ETIMEDOUT; - } + wait * XENON_MAX_PHY_TIMEOUT_LOOPS); - return 0; + return ret; } #define ARMADA_3700_SOC_PAD_1_8V 0x1