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It precedes normally very early things like setup_arch() or the processor initialization code. That means that 'boot_cpu_data' is garbage. It has not even established the utter basics like if the CPU supports the CPUID instruction. Unfortunately get_cpu_cap() requires this exact information. Nevertheless xen_start_kernel() calls get_cpu_cap(). But it works out in practice because it's looking for the NX bit which comes from an extended CPUID leaf that doesn't depend on c->cpuid_level being set. This also implicitly assumes that Xen PV guests support CPUID. Leave the hack in place, but at least explain some of what is going on. Signed-off-by: Dave Hansen Cc: Juergen Gross --- b/arch/x86/xen/enlighten_pv.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff -puN arch/x86/xen/enlighten_pv.c~xen-explain1 arch/x86/xen/enlighten_pv.c --- a/arch/x86/xen/enlighten_pv.c~xen-explain1 2024-02-22 10:08:48.404451146 -0800 +++ b/arch/x86/xen/enlighten_pv.c 2024-02-22 10:08:48.404451146 -0800 @@ -1372,7 +1372,11 @@ asmlinkage __visible void __init xen_sta /* Get mfn list */ xen_build_dynamic_phys_to_machine(); - /* Work out if we support NX */ + /* + * This is a hack. 'boot_cpu_data' is not filled out enough + * for get_cpu_cap() to function fully. But it _can_ fill out + * the leaves where NX is. Gross, but it works. + */ get_cpu_cap(&boot_cpu_data); x86_configure_nx(); From patchwork Thu Feb 22 18:39:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205029 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp176723dyb; Thu, 22 Feb 2024 12:00:20 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWIXtHkPc8aTqfTkSI95pNqZNZkdTVZZ1MfkCCvROxxRwe7kUrx6qAIcjqOi7pB4P0f5V2XZCF8w2bwe5lr7lH0CbfigQ== X-Google-Smtp-Source: AGHT+IHzuI8aYFKAIpglaNaRIUPZM0I//wR2yuEU1qJQX8T9ZmSJsQNVYCE16s2ppOj0Cm/AJo/F X-Received: by 2002:a05:6214:230b:b0:68f:6314:e130 with SMTP id gc11-20020a056214230b00b0068f6314e130mr213264qvb.59.1708632020678; Thu, 22 Feb 2024 12:00:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708632020; cv=pass; d=google.com; s=arc-20160816; b=1AcXzeGxDS27YDiI5xqXiCbaRgbeVmuyMhWhbF9TRDNmqoHb+OIa/2F7fN3aVRuQCc WMBDinQ0coLInMMPzec4slzeB6M/84QIkt88KowYuJnOd7TBf2xFrDWkUUe++o51pJZ1 4r8D+6AtLo7b5u/49PWHY0g1t5vCQx0hpyGYdqQcolzIixR8/pq5DNB72ky9enR3F2g1 yy9LAz+frmQpkx7dp17DYTk70pzuRSFR+cKsPwotU9z9+n6ugIpa5+7KJQzgXv4gvhXb 2/ZwyzMTCBIiCyoJAI29xiLokra/fQ+vrG2fP/M/RBYK5x9VDZoe1GkBm8jLMJzdjs36 jJ9A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=D1xRWi9U0yhojPXJE3o5bjLPkSW80R/pGw6Kwqvm1X0=; fh=xj59RmQDS9mmOGS7FeYRHGvCt6y/iPU5U+DbB/Pwa4E=; b=0xsjckz0ZbLf2fRePjExe/FzyW/d3Xr4S8OGetAdt3TUS3bldrbj+fm5HpchGnq1+w vMEB31iIsWIuJH4znE0mpEBuVI7UMHACUFhyqbotE3jQItQcdRZ6abT87U01TRU+86cD E9o0c5MeJvdRHubjaAZAr0jEPsObxB4XTxER+RG405e1sn4U9dFJSpfiEZBnU2e0jQXM SY7m7r6946O7OioAYTJHZw2an+CScNKilmptoQaw95YAbbrktN4FRPobuK+hw2soalFO NXVSn4Gnw5RZtEaU5F933EseGHNr1AGuRmWXK2DkpkABSubmoC/dadJIWesooipeg5E/ +Nag==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CoSQBoF7; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77156-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77156-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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One of those debugging checks is whether the physical address is valid on the platform. That information is normally available via CPUID. But the __pa() code currently looks it up in 'boot_cpu_data' which is not fully set up in early Xen PV boot. The Xen PV code currently tries to get this info with get_cpu_address_sizes() which also depends on 'boot_cpu_data' to be at least somewhat set up. The result is that the c->x86_phys_bits gets a sane value, but not one that has anything to do with the hardware. In other words, the CONFIG_DEBUG_VIRTUAL checks are performed with what amounts to garbage inputs. Garbage checks are worse than no check at all. Move over to the "nodebug" variant to axe the checks. Signed-off-by: Dave Hansen Cc: Juergen Gross --- b/arch/x86/xen/enlighten_pv.c | 2 +- b/arch/x86/xen/mmu_pv.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff -puN arch/x86/xen/enlighten_pv.c~xen-no-early-__pa arch/x86/xen/enlighten_pv.c --- a/arch/x86/xen/enlighten_pv.c~xen-no-early-__pa 2024-02-22 10:08:48.868469363 -0800 +++ b/arch/x86/xen/enlighten_pv.c 2024-02-22 10:08:48.872469519 -0800 @@ -1452,7 +1452,7 @@ asmlinkage __visible void __init xen_sta boot_params.hdr.type_of_loader = (9 << 4) | 0; boot_params.hdr.ramdisk_image = initrd_start; boot_params.hdr.ramdisk_size = xen_start_info->mod_len; - boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line); + boot_params.hdr.cmd_line_ptr = __pa_nodebug(xen_start_info->cmd_line); boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN; if (!xen_initial_domain()) { diff -puN arch/x86/xen/mmu_pv.c~xen-no-early-__pa arch/x86/xen/mmu_pv.c --- a/arch/x86/xen/mmu_pv.c~xen-no-early-__pa 2024-02-22 10:08:48.872469519 -0800 +++ b/arch/x86/xen/mmu_pv.c 2024-02-22 10:08:48.872469519 -0800 @@ -2006,7 +2006,7 @@ void __init xen_reserve_special_pages(vo { phys_addr_t paddr; - memblock_reserve(__pa(xen_start_info), PAGE_SIZE); + memblock_reserve(__pa_nodebug(xen_start_info), PAGE_SIZE); if (xen_start_info->store_mfn) { paddr = PFN_PHYS(mfn_to_pfn(xen_start_info->store_mfn)); memblock_reserve(paddr, PAGE_SIZE); From patchwork Thu Feb 22 18:39:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205097 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp270133dyb; Thu, 22 Feb 2024 15:05:02 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXo4dSLyn5wmQPSowWL5byKvEXw/Kc5eE1MTxSxAcuEKn5Ww0Sf3hoIOsxm1uawXE4OhRBuanzuAlcdNSTNznAiYdy5HQ== X-Google-Smtp-Source: AGHT+IEYlvSpl2TniUiPAYR1XIm4tmreiNqv2hf6ijs6ozgDxanKf4G34sQcmJODB6K3s4hpcl+j X-Received: by 2002:a05:6a20:438a:b0:1a0:e09d:8ebf with SMTP id i10-20020a056a20438a00b001a0e09d8ebfmr401553pzl.0.1708643102762; Thu, 22 Feb 2024 15:05:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708643102; cv=pass; d=google.com; s=arc-20160816; b=MLMt+ZCdbVPp0HrVNkaKxpOvv+N4UEVcEX+/lYHgI0z6ro1VPt2EqL4IDqvw6IkQUY eWJicPXHTg4CX0J2qgrOCV+sDvAyIaiOLHzTrip8EzAjiy69FgoaOjyYG48fgV0GxCy+ spjUYNKxeCOyDWXdw1aTM47p+ZGxupneuSR5S1Fzs+GIKyEkPUKP2AXUZ2Dw0qiNcAlZ gxaUi3P8UWZ8KzoVXHgKQY40h/W9YuefyPKAL0WQL2GXY57fQVzAgraeYHcjCl+fn3eo NORrT4R+VDJDA01ojUYJ4K+CgY+WzeujFwuV2ihoLBz73XXfsGWqyJxvQFqhrmyf/4Ka nfcQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=1/fX26JDlAaqqAJniW3LfEEgT/3VqQtr7lSaAI9WgVo=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=k+fMZR1w4Zjb6/tmEDd8iduqDdDthSAEsPbo/OxKNqUxrC1xwte2I84aCG/mMXAsOb nhHxPn8OphdbkKkwaN96AnYAsHJczKdnv3fpgSLZZLUw21KZrjSUQd0UF06Z5jdl0AVN cmtZzIRS6ijptuvBg5Vq2y4tUK45JTdrZu/THvsrIhubwIejXGoXU8XimszwAPbX3Acd zdfgf+NPhGmIfRRJA8JvOZ7A557rP7hk2eJ3VIlTBs4iYHJYVHWWoA06/zR4iKi4c6D6 x3Fwc0zAGtT1i8FdTF+gRtKD75NlAYqSy4PV/I758sDTrmPk5dZH59sp40GFbfULv4uA XNNg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=SJgXYgLr; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77157-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77157-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Use that fact to avoid handling the case where it is not set. There may have been a time when the Xen PV call in here way too early. But it calls get_cpu_address_sizes() before calling here now. It should also be safe. Note: This series will eventually return sane defaults even very early in boot. I believe this is safe now, but it becomes *really* safe later on. Signed-off-by: Dave Hansen --- b/arch/x86/pci/common.c | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) diff -puN arch/x86/pci/common.c~x86-pci-clflush-size arch/x86/pci/common.c --- a/arch/x86/pci/common.c~x86-pci-clflush-size 2024-02-22 10:08:49.356488521 -0800 +++ b/arch/x86/pci/common.c 2024-02-22 10:08:49.356488521 -0800 @@ -480,22 +480,9 @@ void pcibios_scan_root(int busnum) void __init pcibios_set_cache_line_size(void) { - struct cpuinfo_x86 *c = &boot_cpu_data; - - /* - * Set PCI cacheline size to that of the CPU if the CPU has reported it. - * (For older CPUs that don't support cpuid, we se it to 32 bytes - * It's also good for 386/486s (which actually have 16) - * as quite a few PCI devices do not support smaller values. - */ - if (c->x86_clflush_size > 0) { - pci_dfl_cache_line_size = c->x86_clflush_size >> 2; - printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n", - pci_dfl_cache_line_size << 2); - } else { - pci_dfl_cache_line_size = 32 >> 2; - printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n"); - } + pci_dfl_cache_line_size = boot_cpu_data.x86_clflush_size >> 2; + printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n", + pci_dfl_cache_line_size << 2); } int __init pcibios_init(void) From patchwork Thu Feb 22 18:39:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205090 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp261174dyb; Thu, 22 Feb 2024 14:45:27 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUsytng6REKq1OvINL7uc36SlUhxq+vQDptoDRyI2F3KkORpTcJY9Ur6UhPNL3yuTVvdt+/ITG6Wsoxn6Va9KwaYttkJw== X-Google-Smtp-Source: AGHT+IFOGRbN3VKoQe4gaa7plDA5AQADlDAGbTIfYScRCupCYmnSYf7XXFSnskvV6E0+lWi7mxVs X-Received: by 2002:a05:6a20:e687:b0:19e:aa08:1a0 with SMTP id mz7-20020a056a20e68700b0019eaa0801a0mr4930041pzb.8.1708641927487; Thu, 22 Feb 2024 14:45:27 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708641927; cv=pass; d=google.com; s=arc-20160816; b=HTFtVADiw0p7lxC+deE1kyQTqaskDhANGvP2ty6MeKktIZbgx3TyCkMVj6UYXVoP3s tsJPgBnxOibzImas/OgYTsxk2mm+2i9i3iFo13tOQF+u1hKLY0yPLugvCCE4y6dwhkiV h8UmfL5/ew6AAiEhUyA4xcIvV22ua3Y5LyxrsZ/XXzsOs5BmUWfTXjsIlTcHg5zHAYJ3 0YbtA584dXkxMttvhI16QTzbzfJ2sDiauLvxde46KHlCf3TXaCTmQLLkCv14dJXncnZb IPew2xzx6NyD/tc3mCj6661toldHXAgR3H++g0S/qLj6C942xdiHOzQ1csT0XUOOgNRA xMKQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=TluosU8735OW3JgarVYBEoLEU/x2Gtog+xYSffnuyac=; fh=0emyRx9yc67h3QZVFGJ+w9u3Ehva+ijGVrI+thK1p/w=; b=vx3iatJ2mkpKMl3T/qRlgzyPIBcJG5PimIUVwn+c214XbNJw+O6HMwGSeaCK1Ehmja Zn+LWStZJWzjWhbyIVfxRvzWWLDo5ajt5pasru1MRn4lg/aTrDmThvAXE5UVObiBbDTE 4JBwuI9f7rJz3twzHxYwhZJ5YzxAmLaVEolEpApMex3iz5EBO5g1qZ8Qgjo2IJzwLk0R zenntPn9LhqLTZHnNya8NTi6/pDJtiLy37RWz/xnqEXf0jymYWksCROiHyahi/M0tIip A20vpBWTX/3hlLm3eyNEn7Vvc3HmRXQJ4nRmSwSIbC7LoLTesTxq05imu3xAbLW+GGIB 0Rrg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=A5zMDDeZ; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77158-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77158-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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The kernel stashes this information for each CPU in 'cpuinfo_x86'. Like a lot of system-wide configuration, in practice the kernel only uses this information from the boot CPU. That makes a lot of sense because the kernel can't practically support two CPUs with such different fundamental support as the size of the address spaces. Having a per-cpu copy of this data is silly. It is, at best, a waste of space to keep it around for the non-boot CPUs. At worst, it is yet another bit of data that must be initialized in a particular order and can be a source of bugs. Introduce a helper to look up the number of supported physical address bits: x86_phys_bits() Replace most open-coded references to boot_cpu_data.x86_phys_bits. This form is more compact and also opens up the door to adding some centralized checking and enforcing rules around this important system- wide value. Signed-off-by: Dave Hansen Cc: "Rafael J. Wysocki" Cc: Len Brown Reviewed-by: Kai Huang --- b/arch/x86/include/asm/kmsan.h | 2 +- b/arch/x86/include/asm/mce.h | 2 +- b/arch/x86/include/asm/processor.h | 5 +++++ b/arch/x86/kernel/cpu/mtrr/cleanup.c | 2 +- b/arch/x86/kernel/cpu/mtrr/generic.c | 2 +- b/arch/x86/kernel/cpu/mtrr/mtrr.c | 5 ++--- b/arch/x86/kernel/setup.c | 2 +- b/arch/x86/kvm/cpuid.c | 2 +- b/arch/x86/kvm/mmu.h | 10 +++++----- b/arch/x86/kvm/mmu/spte.c | 2 +- b/arch/x86/kvm/svm/svm.c | 2 +- b/arch/x86/kvm/vmx/vmx.c | 10 +++++----- b/arch/x86/kvm/vmx/vmx.h | 2 +- b/arch/x86/mm/physaddr.h | 2 +- b/drivers/acpi/acpi_fpdt.c | 2 +- 15 files changed, 28 insertions(+), 24 deletions(-) diff -puN arch/x86/include/asm/kmsan.h~introduce-x86_phys_bits arch/x86/include/asm/kmsan.h --- a/arch/x86/include/asm/kmsan.h~introduce-x86_phys_bits 2024-02-22 10:08:49.828507052 -0800 +++ b/arch/x86/include/asm/kmsan.h 2024-02-22 10:08:49.852507994 -0800 @@ -52,7 +52,7 @@ static inline void *arch_kmsan_get_meta_ static inline bool kmsan_phys_addr_valid(unsigned long addr) { if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) - return !(addr >> boot_cpu_data.x86_phys_bits); + return !(addr >> x86_phys_bits()); else return true; } diff -puN arch/x86/include/asm/mce.h~introduce-x86_phys_bits arch/x86/include/asm/mce.h --- a/arch/x86/include/asm/mce.h~introduce-x86_phys_bits 2024-02-22 10:08:49.828507052 -0800 +++ b/arch/x86/include/asm/mce.h 2024-02-22 10:08:49.852507994 -0800 @@ -89,7 +89,7 @@ #define MCI_MISC_ADDR_GENERIC 7 /* generic */ /* MCi_ADDR register defines */ -#define MCI_ADDR_PHYSADDR GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0) +#define MCI_ADDR_PHYSADDR GENMASK_ULL(x86_phys_bits() - 1, 0) /* CTL2 register defines */ #define MCI_CTL2_CMCI_EN BIT_ULL(30) diff -puN arch/x86/include/asm/processor.h~introduce-x86_phys_bits arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~introduce-x86_phys_bits 2024-02-22 10:08:49.828507052 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:08:49.852507994 -0800 @@ -767,4 +767,9 @@ static inline void weak_wrmsr_fence(void alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); } +static inline u8 x86_phys_bits(void) +{ + return boot_cpu_data.x86_phys_bits; +} + #endif /* _ASM_X86_PROCESSOR_H */ diff -puN arch/x86/kernel/cpu/mtrr/cleanup.c~introduce-x86_phys_bits arch/x86/kernel/cpu/mtrr/cleanup.c --- a/arch/x86/kernel/cpu/mtrr/cleanup.c~introduce-x86_phys_bits 2024-02-22 10:08:49.832507209 -0800 +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c 2024-02-22 10:08:49.852507994 -0800 @@ -170,7 +170,7 @@ set_var_mtrr(unsigned int reg, unsigned return; } - mask = (1ULL << boot_cpu_data.x86_phys_bits) - 1; + mask = (1ULL << x86_phys_bits()) - 1; mask &= ~((((u64)sizek) << 10) - 1); base = ((u64)basek) << 10; diff -puN arch/x86/kernel/cpu/mtrr/generic.c~introduce-x86_phys_bits arch/x86/kernel/cpu/mtrr/generic.c --- a/arch/x86/kernel/cpu/mtrr/generic.c~introduce-x86_phys_bits 2024-02-22 10:08:49.832507209 -0800 +++ b/arch/x86/kernel/cpu/mtrr/generic.c 2024-02-22 10:08:49.852507994 -0800 @@ -660,7 +660,7 @@ static void __init print_mtrr_state(void } pr_info("MTRR variable ranges %sabled:\n", mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); - high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; + high_width = (x86_phys_bits() - (32 - PAGE_SHIFT) + 3) / 4; for (i = 0; i < num_var_ranges; ++i) { if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V) diff -puN arch/x86/kernel/cpu/mtrr/mtrr.c~introduce-x86_phys_bits arch/x86/kernel/cpu/mtrr/mtrr.c --- a/arch/x86/kernel/cpu/mtrr/mtrr.c~introduce-x86_phys_bits 2024-02-22 10:08:49.836507366 -0800 +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c 2024-02-22 10:08:49.852507994 -0800 @@ -252,8 +252,7 @@ int mtrr_add_page(unsigned long base, un return -EINVAL; } - if ((base | (base + size - 1)) >> - (boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) { + if ((base | (base + size - 1)) >> (x86_phys_bits() - PAGE_SHIFT)) { pr_warn("base or size exceeds the MTRR width\n"); return -EINVAL; } @@ -556,7 +555,7 @@ void __init mtrr_bp_init(void) const char *why = "(not available)"; unsigned long config, dummy; - phys_hi_rsvd = GENMASK(31, boot_cpu_data.x86_phys_bits - 32); + phys_hi_rsvd = GENMASK(31, x86_phys_bits() - 32); if (!generic_mtrrs && mtrr_state.enabled) { /* diff -puN arch/x86/kernel/setup.c~introduce-x86_phys_bits arch/x86/kernel/setup.c --- a/arch/x86/kernel/setup.c~introduce-x86_phys_bits 2024-02-22 10:08:49.836507366 -0800 +++ b/arch/x86/kernel/setup.c 2024-02-22 10:08:49.852507994 -0800 @@ -813,7 +813,7 @@ void __init setup_arch(char **cmdline_p) */ early_reserve_memory(); - iomem_resource.end = (1ULL << boot_cpu_data.x86_phys_bits) - 1; + iomem_resource.end = (1ULL << x86_phys_bits()) - 1; e820__memory_setup(); parse_setup_data(); diff -puN arch/x86/kvm/cpuid.c~introduce-x86_phys_bits arch/x86/kvm/cpuid.c --- a/arch/x86/kvm/cpuid.c~introduce-x86_phys_bits 2024-02-22 10:08:49.836507366 -0800 +++ b/arch/x86/kvm/cpuid.c 2024-02-22 10:08:49.852507994 -0800 @@ -1236,7 +1236,7 @@ static inline int __do_cpuid_func(struct * the HPAs do not affect GPAs. */ if (!tdp_enabled) - g_phys_as = boot_cpu_data.x86_phys_bits; + g_phys_as = x86_phys_bits(); else if (!g_phys_as) g_phys_as = phys_as; diff -puN arch/x86/kvm/mmu.h~introduce-x86_phys_bits arch/x86/kvm/mmu.h --- a/arch/x86/kvm/mmu.h~introduce-x86_phys_bits 2024-02-22 10:08:49.840507523 -0800 +++ b/arch/x86/kvm/mmu.h 2024-02-22 10:08:49.852507994 -0800 @@ -84,10 +84,10 @@ static inline gfn_t kvm_mmu_max_gfn(void static inline u8 kvm_get_shadow_phys_bits(void) { /* - * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected - * in CPU detection code, but the processor treats those reduced bits as - * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at - * the physical address bits reported by CPUID. + * x86_phys_bits() is reduced when MKTME or SME are detected in CPU + * detection code, but the processor treats those reduced bits as 'keyID' + * thus they are not reserved bits. Therefore KVM needs to look at the + * physical address bits reported by CPUID. */ if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008)) return cpuid_eax(0x80000008) & 0xff; @@ -97,7 +97,7 @@ static inline u8 kvm_get_shadow_phys_bit * custom CPUID. Proceed with whatever the kernel found since these features * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008). */ - return boot_cpu_data.x86_phys_bits; + return x86_phys_bits(); } void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask); diff -puN arch/x86/kvm/mmu/spte.c~introduce-x86_phys_bits arch/x86/kvm/mmu/spte.c --- a/arch/x86/kvm/mmu/spte.c~introduce-x86_phys_bits 2024-02-22 10:08:49.840507523 -0800 +++ b/arch/x86/kvm/mmu/spte.c 2024-02-22 10:08:49.852507994 -0800 @@ -468,7 +468,7 @@ void kvm_mmu_reset_all_pte_masks(void) * the most significant bits of legal physical address space. */ shadow_nonpresent_or_rsvd_mask = 0; - low_phys_bits = boot_cpu_data.x86_phys_bits; + low_phys_bits = x86_phys_bits(); if (boot_cpu_has_bug(X86_BUG_L1TF) && !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >= 52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) { diff -puN arch/x86/kvm/svm/svm.c~introduce-x86_phys_bits arch/x86/kvm/svm/svm.c --- a/arch/x86/kvm/svm/svm.c~introduce-x86_phys_bits 2024-02-22 10:08:49.840507523 -0800 +++ b/arch/x86/kvm/svm/svm.c 2024-02-22 10:08:49.852507994 -0800 @@ -5054,7 +5054,7 @@ static __init void svm_adjust_mmio_mask( return; enc_bit = cpuid_ebx(0x8000001f) & 0x3f; - mask_bit = boot_cpu_data.x86_phys_bits; + mask_bit = x86_phys_bits(); /* Increment the mask bit if it is the same as the encryption bit */ if (enc_bit == mask_bit) diff -puN arch/x86/kvm/vmx/vmx.c~introduce-x86_phys_bits arch/x86/kvm/vmx/vmx.c --- a/arch/x86/kvm/vmx/vmx.c~introduce-x86_phys_bits 2024-02-22 10:08:49.844507680 -0800 +++ b/arch/x86/kvm/vmx/vmx.c 2024-02-22 10:08:49.852507994 -0800 @@ -8444,14 +8444,14 @@ static void __init vmx_setup_me_spte_mas * kvm_get_shadow_phys_bits() returns shadow_phys_bits. Use * the former to avoid exposing shadow_phys_bits. * - * On pre-MKTME system, boot_cpu_data.x86_phys_bits equals to + * On pre-MKTME system, x86_phys_bits() equals to * shadow_phys_bits. On MKTME and/or TDX capable systems, - * boot_cpu_data.x86_phys_bits holds the actual physical address - * w/o the KeyID bits, and shadow_phys_bits equals to MAXPHYADDR + * x86_phys_bits() holds the actual physical address w/o the + * KeyID bits, and shadow_phys_bits equals to MAXPHYADDR * reported by CPUID. Those bits between are KeyID bits. */ - if (boot_cpu_data.x86_phys_bits != kvm_get_shadow_phys_bits()) - me_mask = rsvd_bits(boot_cpu_data.x86_phys_bits, + if (x86_phys_bits() != kvm_get_shadow_phys_bits()) + me_mask = rsvd_bits(x86_phys_bits(), kvm_get_shadow_phys_bits() - 1); /* * Unlike SME, host kernel doesn't support setting up any diff -puN arch/x86/kvm/vmx/vmx.h~introduce-x86_phys_bits arch/x86/kvm/vmx/vmx.h --- a/arch/x86/kvm/vmx/vmx.h~introduce-x86_phys_bits 2024-02-22 10:08:49.844507680 -0800 +++ b/arch/x86/kvm/vmx/vmx.h 2024-02-22 10:08:49.852507994 -0800 @@ -721,7 +721,7 @@ static inline bool vmx_need_pf_intercept if (!enable_ept) return true; - return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits; + return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < x86_phys_bits(); } static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu) diff -puN arch/x86/mm/physaddr.h~introduce-x86_phys_bits arch/x86/mm/physaddr.h --- a/arch/x86/mm/physaddr.h~introduce-x86_phys_bits 2024-02-22 10:08:49.848507837 -0800 +++ b/arch/x86/mm/physaddr.h 2024-02-22 10:08:49.852507994 -0800 @@ -4,7 +4,7 @@ static inline int phys_addr_valid(resource_size_t addr) { #ifdef CONFIG_PHYS_ADDR_T_64BIT - return !(addr >> boot_cpu_data.x86_phys_bits); + return !(addr >> x86_phys_bits()); #else return 1; #endif diff -puN drivers/acpi/acpi_fpdt.c~introduce-x86_phys_bits drivers/acpi/acpi_fpdt.c --- a/drivers/acpi/acpi_fpdt.c~introduce-x86_phys_bits 2024-02-22 10:08:49.848507837 -0800 +++ b/drivers/acpi/acpi_fpdt.c 2024-02-22 10:08:49.852507994 -0800 @@ -151,7 +151,7 @@ static bool fpdt_address_valid(u64 addre * On some systems the table contains invalid addresses * with unsuppored high address bits set, check for this. */ - return !(address >> boot_cpu_data.x86_phys_bits); + return !(address >> x86_phys_bits()); } #else static bool fpdt_address_valid(u64 address) From patchwork Thu Feb 22 18:39:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205075 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp225455dyb; Thu, 22 Feb 2024 13:41:53 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXb47UDpjJ4vXl9i09ddCBsu08QoIBLFx0SmvmHSe2gezx1aUepcVZJNchn24kRHWhS4Q+lbd2Vx3i2MvtP6DH/rFIgYQ== X-Google-Smtp-Source: AGHT+IGDsQqe33p3crZ+EprS+ohUCfgiabt+1+IfcJyIg7CRtqY/vNRyL5ZkYFY9xCtAqVdJ8iWy X-Received: by 2002:aa7:cf17:0:b0:565:789:3058 with SMTP id a23-20020aa7cf17000000b0056507893058mr12253edy.23.1708638113504; Thu, 22 Feb 2024 13:41:53 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708638113; cv=pass; d=google.com; s=arc-20160816; b=i2qJn0uoDmpipoFhDLeQqGhMDW6FkuYQSCI41kJJI6OK+gR+dZC72YVWtg0i2Go9hM sx1b10C3v0yZT1DyZe3OT4mzsDjVV0JpIuYBHmHmiIGiyDEI1QkLFppakV4gJArN+ysF b2oMIwkdNwPHX6DdhxzHgVpk9iIoSQ7KgBESsxdfi+n1+twtkaHeNp/SfvnRrv6myw1A +vqInjn7ZnLA8afK0gJljAYPLD/w+hBrsP2LLKIHYnABPV2K2j1EEmfQgUsXmFDJPO0t nd/qbIojkS/z9sxdZsMdwVvfbxE7vGXL+/po7wnQ+/WEL0sGWKsvK/dyssIhddO9rs8b AZlA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=74A8zq/rmtnQliyT5PClq5K782LGzRAIYblFfL3VNJM=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=G2TkzfDqXtn+9wpi7dkRbwsgwFjPgikD6LaW6sXjOpE7+1es7VSqN3EEUF+AKbFIx1 znzMJAm5Cyg14Nyq/YMEF1DhhUn8TEi6cFzKJNzuZS3dg6QVLFqvpfPdEvb7KN5/7Lgi C9broC7zYVcVHRRzKJdbnUmJP+eUGUERhSOzazQiEgUONEYjgHU9eBED6N53Kpo/m49w Eae6hku1l/7P6eaF3vQVnw/kw56MblNtQCZyZ378XoM21rF/EyvbA8VI7+3/lmuQWEif pZHqg0v2I8vDu4URDLUxaqupyjoP2ePgX6Ua+L0FcFdKjqHKpjwMdhNnm6WUjEYZ6ksC pjBQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Z4S1+zlp; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77159-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77159-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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It is theoretically possible to have this value vary from CPU to CPU. But in practice nobody builds systems that way. Continue outputting the value in /proc, but read it from the global configuration. Signed-off-by: Dave Hansen Reviewed-by: Kai Huang --- b/arch/x86/kernel/cpu/proc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff -puN arch/x86/kernel/cpu/proc.c~proc-global-x86-phys-bits arch/x86/kernel/cpu/proc.c --- a/arch/x86/kernel/cpu/proc.c~proc-global-x86-phys-bits 2024-02-22 10:08:50.584536732 -0800 +++ b/arch/x86/kernel/cpu/proc.c 2024-02-22 10:08:50.584536732 -0800 @@ -133,7 +133,7 @@ static int show_cpuinfo(struct seq_file seq_printf(m, "clflush size\t: %u\n", c->x86_clflush_size); seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment); seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n", - c->x86_phys_bits, c->x86_virt_bits); + x86_phys_bits(), c->x86_virt_bits); seq_puts(m, "power management:"); for (i = 0; i < 32; i++) { From patchwork Thu Feb 22 18:39:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 204995 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp137896dyb; Thu, 22 Feb 2024 10:44:30 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWSoH2qK4g1E8F9nnts2lVyf39EJMN+5DKL0SjU+Q+2ce8orpvHuvtrQ6gf7pUl+mHXjCYEjkRvehraCsrkF4AXpOcWUQ== X-Google-Smtp-Source: AGHT+IHAnrOROLircJ2pWzFltUvXzlTFFMrr9TT9789/REM0zX+3gsF7u6kzBL0KYtz1SCiemOXt X-Received: by 2002:a05:6402:351:b0:565:1a91:94ad with SMTP id r17-20020a056402035100b005651a9194admr2913434edw.22.1708627469761; Thu, 22 Feb 2024 10:44:29 -0800 (PST) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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They are not stable during early boot and readers end up getting a random mishmash of hard-coded defaults or CPUID-provided values based on when the values are read. iomem_resource.end is one of these users. Because of where it is called, it ended up seeing .x86_phys_bits==MAX_PHYSMEM_BITS which is (mostly) a compile-time default. But iomem_resource.end is never updated if the runtime CPUID x86_phys_bits is lower. Set iomem_resource.end to the compile-time value explicitly. It does not need to be precise as this is mostly to ensure that insane values can't be reserved in 'iomem_resource'. Make MAX_PHYSMEM_BITS available outside of sparsemem configurations by removing the #ifdef CONFIG_SPARSEMEM in the header. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/sparsemem.h | 3 --- b/arch/x86/kernel/setup.c | 10 +++++++++- 2 files changed, 9 insertions(+), 4 deletions(-) diff -puN arch/x86/kernel/setup.c~iomem_resource_end arch/x86/kernel/setup.c --- a/arch/x86/kernel/setup.c~iomem_resource_end 2024-02-22 10:08:51.048554948 -0800 +++ b/arch/x86/kernel/setup.c 2024-02-22 10:21:04.485531464 -0800 @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -813,7 +814,14 @@ void __init setup_arch(char **cmdline_p) */ early_reserve_memory(); - iomem_resource.end = (1ULL << x86_phys_bits()) - 1; + /* + * This was too big before. It ended up getting MAX_PHYSMEM_BITS + * even if .x86_phys_bits was eventually lowered below that. + * But that was evidently harmless, so leave it too big, but + * set it explicitly to MAX_PHYSMEM_BITS instead of taking a + * trip through .x86_phys_bits. + */ + iomem_resource.end = (1ULL << MAX_PHYSMEM_BITS) - 1; e820__memory_setup(); parse_setup_data(); diff -puN arch/x86/include/asm/sparsemem.h~iomem_resource_end arch/x86/include/asm/sparsemem.h --- a/arch/x86/include/asm/sparsemem.h~iomem_resource_end 2024-02-22 10:19:56.842831828 -0800 +++ b/arch/x86/include/asm/sparsemem.h 2024-02-22 10:20:21.207804806 -0800 @@ -4,7 +4,6 @@ #include -#ifdef CONFIG_SPARSEMEM /* * generic non-linear memory support: * @@ -29,8 +28,6 @@ # define MAX_PHYSMEM_BITS (pgtable_l5_enabled() ? 52 : 46) #endif -#endif /* CONFIG_SPARSEMEM */ - #ifndef __ASSEMBLY__ #ifdef CONFIG_NUMA_KEEP_MEMINFO extern int phys_to_target_node(phys_addr_t start); From patchwork Thu Feb 22 18:39:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205031 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp176893dyb; Thu, 22 Feb 2024 12:00:34 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVLtn2Wj+M+MmWTUixxP4SpbICzOCpOQbjyrK3x+3mgvRg098VfIUQeeu4Ejoh47eav6fme980ullZtlJrFBIlh70hTHA== X-Google-Smtp-Source: AGHT+IF7XK++ilqCbbnD7GO5aTXMOitDE/bsWc6nOFvApDpQii5uMwdxZ89wMhKMZUc8B0/02OjY X-Received: by 2002:a05:6902:510:b0:dc6:4b5a:410a with SMTP id x16-20020a056902051000b00dc64b5a410amr183679ybs.12.1708632033830; Thu, 22 Feb 2024 12:00:33 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708632033; cv=pass; d=google.com; s=arc-20160816; b=LlLV0SdMwRnh9XuHxM28/X/Ezs5pNNmd5e/SMjQCLwEZKO97pyeLr263JAWbWeVOMn mAHEnEcJNOKwJPWcZbB1mdHbBfhlnpBpshxTKjbm0/c0nI1KeaJM0P1fDokGuP9vsonB i4l2ibwGNGHcja0NNlURusxc3id2qsKktE61n0GgincI2D7O4AXbJqgAd3jgSO7eI1al h0flAhYPiVs/49eMM4A6ensH/jIFiT7bprIrGamqp6Tr/J9B6KjJBnNGxl7PK/hW9X76 JkkGQA+4dSb1LzkKnbQdOLFbk4cwFL+7tD/4eKLvf2ehn5LDi+YqBSsY1171BgmD/9c+ orNg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=foGMvudsd7WfiIpJQAJrh6w+6rc64QUxHF01rh6aHec=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=eSMVNHAeXzN15qkFIn/FFV4QYGdnqjxmnUtDlfy1P4cU6FinuNqXMBlMRwtjzpDou/ GM8H2zw29JxF1rY2FuZon60y2kvsE6lsqdFhWElmLW6JJvDW8Uzsyvnmxir5A7+/PALC 7KRyhDh9HOes6tvCkkmedUp7SHE60W7ZlUHY97cnMh5k+QOgdR1hbBUkl6pBHZMqbfZt UmPLkHOSgAmy95vCf5uYtUZUQWKhoyD3ipjlmkbMys7klVnAuAZpUFlmcp0vwLMorSka cfAAF2FJQEk+yvY/tXtHK4YVHfOHJYPpO6oa9hK9jO0unPpkRknfv+K+UNVYH23hdb5I A67Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Ke59vf46; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77161-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77161-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Introduce a system-wide helper for users to query the size of the virtual address space: x86_virt_bits() Signed-off-by: Dave Hansen Reviewed-by: Kai Huang --- b/arch/x86/events/amd/brs.c | 2 +- b/arch/x86/events/amd/lbr.c | 2 +- b/arch/x86/events/intel/pt.c | 4 ++-- b/arch/x86/include/asm/processor.h | 5 +++++ b/arch/x86/kernel/cpu/proc.c | 2 +- b/arch/x86/mm/maccess.c | 4 ++-- 6 files changed, 12 insertions(+), 7 deletions(-) diff -puN arch/x86/events/amd/brs.c~x86_virt_bits-func arch/x86/events/amd/brs.c --- a/arch/x86/events/amd/brs.c~x86_virt_bits-func 2024-02-22 10:08:51.528573793 -0800 +++ b/arch/x86/events/amd/brs.c 2024-02-22 10:08:51.536574107 -0800 @@ -285,7 +285,7 @@ void amd_brs_drain(void) struct perf_branch_entry *br = cpuc->lbr_entries; union amd_debug_extn_cfg cfg; u32 i, nr = 0, num, tos, start; - u32 shift = 64 - boot_cpu_data.x86_virt_bits; + u32 shift = 64 - x86_virt_bits(); /* * BRS event forced on PMC0, diff -puN arch/x86/events/amd/lbr.c~x86_virt_bits-func arch/x86/events/amd/lbr.c --- a/arch/x86/events/amd/lbr.c~x86_virt_bits-func 2024-02-22 10:08:51.528573793 -0800 +++ b/arch/x86/events/amd/lbr.c 2024-02-22 10:08:51.536574107 -0800 @@ -89,7 +89,7 @@ static __always_inline u64 amd_pmu_lbr_g static __always_inline u64 sign_ext_branch_ip(u64 ip) { - u32 shift = 64 - boot_cpu_data.x86_virt_bits; + u32 shift = 64 - x86_virt_bits(); return (u64)(((s64)ip << shift) >> shift); } diff -puN arch/x86/events/intel/pt.c~x86_virt_bits-func arch/x86/events/intel/pt.c --- a/arch/x86/events/intel/pt.c~x86_virt_bits-func 2024-02-22 10:08:51.528573793 -0800 +++ b/arch/x86/events/intel/pt.c 2024-02-22 10:08:51.536574107 -0800 @@ -1453,8 +1453,8 @@ static void pt_event_addr_filters_sync(s * canonical addresses does not affect the result of the * address filter. */ - msr_a = clamp_to_ge_canonical_addr(a, boot_cpu_data.x86_virt_bits); - msr_b = clamp_to_le_canonical_addr(b, boot_cpu_data.x86_virt_bits); + msr_a = clamp_to_ge_canonical_addr(a, x86_virt_bits()); + msr_b = clamp_to_le_canonical_addr(b, x86_virt_bits()); if (msr_b < msr_a) msr_a = msr_b = 0; } diff -puN arch/x86/include/asm/processor.h~x86_virt_bits-func arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~x86_virt_bits-func 2024-02-22 10:08:51.532573950 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:08:51.536574107 -0800 @@ -772,4 +772,9 @@ static inline u8 x86_phys_bits(void) return boot_cpu_data.x86_phys_bits; } +static inline u8 x86_virt_bits(void) +{ + return boot_cpu_data.x86_virt_bits; +} + #endif /* _ASM_X86_PROCESSOR_H */ diff -puN arch/x86/kernel/cpu/proc.c~x86_virt_bits-func arch/x86/kernel/cpu/proc.c --- a/arch/x86/kernel/cpu/proc.c~x86_virt_bits-func 2024-02-22 10:08:51.532573950 -0800 +++ b/arch/x86/kernel/cpu/proc.c 2024-02-22 10:08:51.536574107 -0800 @@ -133,7 +133,7 @@ static int show_cpuinfo(struct seq_file seq_printf(m, "clflush size\t: %u\n", c->x86_clflush_size); seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment); seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n", - x86_phys_bits(), c->x86_virt_bits); + x86_phys_bits(), x86_virt_bits()); seq_puts(m, "power management:"); for (i = 0; i < 32; i++) { diff -puN arch/x86/mm/maccess.c~x86_virt_bits-func arch/x86/mm/maccess.c --- a/arch/x86/mm/maccess.c~x86_virt_bits-func 2024-02-22 10:08:51.536574107 -0800 +++ b/arch/x86/mm/maccess.c 2024-02-22 10:08:51.536574107 -0800 @@ -20,10 +20,10 @@ bool copy_from_kernel_nofault_allowed(co * is initialized. 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Keeping it per-cpu is just silly. Introduce a system-wide helper for looking up the cacheline size and use it. This does one slightly odd looking thing, it stops setting c->x86_clflush_size on all but the boot CPU. This is functionally OK because all readers of the secondary CPU values also go away. It also makes it explicit that the 'boot_cpu_data' is the one true system-wide value. Signed-off-by: Dave Hansen Cc: Mikulas Patocka Cc: Mike Snitzer Cc: Daniel Vetter --- b/arch/x86/include/asm/processor.h | 5 +++++ b/arch/x86/kernel/cpu/centaur.c | 2 +- b/arch/x86/kernel/cpu/common.c | 9 +++++---- b/arch/x86/kernel/cpu/intel.c | 2 +- b/arch/x86/kernel/cpu/proc.c | 2 +- b/arch/x86/lib/usercopy_64.c | 7 +++---- b/arch/x86/mm/pat/set_memory.c | 2 +- b/arch/x86/pci/common.c | 2 +- b/drivers/gpu/drm/drm_cache.c | 4 ++-- b/drivers/gpu/drm/i915/i915_cmd_parser.c | 3 +-- b/drivers/gpu/drm/i915/i915_gem.c | 2 +- b/drivers/md/dm-writecache.c | 2 +- 12 files changed, 23 insertions(+), 19 deletions(-) diff -puN arch/x86/include/asm/processor.h~x86_clflush_size-func arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~x86_clflush_size-func 2024-02-22 10:08:52.112596720 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:08:52.132597505 -0800 @@ -777,4 +777,9 @@ static inline u8 x86_virt_bits(void) return boot_cpu_data.x86_virt_bits; } +static inline u8 x86_clflush_size(void) +{ + return boot_cpu_data.x86_clflush_size; +} + #endif /* _ASM_X86_PROCESSOR_H */ diff -puN arch/x86/kernel/cpu/centaur.c~x86_clflush_size-func arch/x86/kernel/cpu/centaur.c --- a/arch/x86/kernel/cpu/centaur.c~x86_clflush_size-func 2024-02-22 10:08:52.112596720 -0800 +++ b/arch/x86/kernel/cpu/centaur.c 2024-02-22 10:08:52.132597505 -0800 @@ -62,7 +62,7 @@ static void init_c3(struct cpuinfo_x86 * set_cpu_cap(c, X86_FEATURE_3DNOW); #endif if (c->x86 == 0x6 && c->x86_model >= 0xf) { - c->x86_cache_alignment = c->x86_clflush_size * 2; + c->x86_cache_alignment = x86_clflush_size() * 2; set_cpu_cap(c, X86_FEATURE_REP_GOOD); } diff -puN arch/x86/kernel/cpu/common.c~x86_clflush_size-func arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~x86_clflush_size-func 2024-02-22 10:08:52.112596720 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:08:52.132597505 -0800 @@ -954,8 +954,9 @@ void cpu_detect(struct cpuinfo_x86 *c) c->x86_stepping = x86_stepping(tfms); if (cap0 & (1<<19)) { - c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; - c->x86_cache_alignment = c->x86_clflush_size; + if (c == &boot_cpu_data) + c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; + c->x86_cache_alignment = x86_clflush_size(); } } } @@ -1123,7 +1124,7 @@ void get_cpu_address_sizes(struct cpuinf } } c->x86_cache_bits = c->x86_phys_bits; - c->x86_cache_alignment = c->x86_clflush_size; + c->x86_cache_alignment = x86_clflush_size(); } static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) @@ -1831,7 +1832,7 @@ static void identify_cpu(struct cpuinfo_ c->x86_phys_bits = 32; c->x86_virt_bits = 32; #endif - c->x86_cache_alignment = c->x86_clflush_size; + c->x86_cache_alignment = x86_clflush_size(); memset(&c->x86_capability, 0, sizeof(c->x86_capability)); #ifdef CONFIG_X86_VMX_FEATURE_NAMES memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); diff -puN arch/x86/kernel/cpu/intel.c~x86_clflush_size-func arch/x86/kernel/cpu/intel.c --- a/arch/x86/kernel/cpu/intel.c~x86_clflush_size-func 2024-02-22 10:08:52.116596877 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2024-02-22 10:08:52.132597505 -0800 @@ -653,7 +653,7 @@ static void init_intel(struct cpuinfo_x8 #ifdef CONFIG_X86_64 if (c->x86 == 15) - c->x86_cache_alignment = c->x86_clflush_size * 2; + c->x86_cache_alignment = x86_clflush_size() * 2; if (c->x86 == 6) set_cpu_cap(c, X86_FEATURE_REP_GOOD); #else diff -puN arch/x86/kernel/cpu/proc.c~x86_clflush_size-func arch/x86/kernel/cpu/proc.c --- a/arch/x86/kernel/cpu/proc.c~x86_clflush_size-func 2024-02-22 10:08:52.116596877 -0800 +++ b/arch/x86/kernel/cpu/proc.c 2024-02-22 10:08:52.132597505 -0800 @@ -130,7 +130,7 @@ static int show_cpuinfo(struct seq_file if (c->x86_tlbsize > 0) seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize); #endif - seq_printf(m, "clflush size\t: %u\n", c->x86_clflush_size); + seq_printf(m, "clflush size\t: %u\n", x86_clflush_size()); seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment); seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n", x86_phys_bits(), x86_virt_bits()); diff -puN arch/x86/lib/usercopy_64.c~x86_clflush_size-func arch/x86/lib/usercopy_64.c --- a/arch/x86/lib/usercopy_64.c~x86_clflush_size-func 2024-02-22 10:08:52.120597034 -0800 +++ b/arch/x86/lib/usercopy_64.c 2024-02-22 10:08:52.132597505 -0800 @@ -27,13 +27,12 @@ */ static void clean_cache_range(void *addr, size_t size) { - u16 x86_clflush_size = boot_cpu_data.x86_clflush_size; - unsigned long clflush_mask = x86_clflush_size - 1; + unsigned long clflush_mask = x86_clflush_size() - 1; void *vend = addr + size; void *p; for (p = (void *)((unsigned long)addr & ~clflush_mask); - p < vend; p += x86_clflush_size) + p < vend; p += x86_clflush_size()) clwb(p); } @@ -65,7 +64,7 @@ long __copy_user_flushcache(void *dst, c clean_cache_range(dst, size); } else { if (!IS_ALIGNED(dest, 8)) { - dest = ALIGN(dest, boot_cpu_data.x86_clflush_size); + dest = ALIGN(dest, x86_clflush_size()); clean_cache_range(dst, 1); } diff -puN arch/x86/mm/pat/set_memory.c~x86_clflush_size-func arch/x86/mm/pat/set_memory.c --- a/arch/x86/mm/pat/set_memory.c~x86_clflush_size-func 2024-02-22 10:08:52.120597034 -0800 +++ b/arch/x86/mm/pat/set_memory.c 2024-02-22 10:08:52.132597505 -0800 @@ -314,7 +314,7 @@ static unsigned long __cpa_addr(struct c static void clflush_cache_range_opt(void *vaddr, unsigned int size) { - const unsigned long clflush_size = boot_cpu_data.x86_clflush_size; + const unsigned long clflush_size = x86_clflush_size(); void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1)); void *vend = vaddr + size; diff -puN arch/x86/pci/common.c~x86_clflush_size-func arch/x86/pci/common.c --- a/arch/x86/pci/common.c~x86_clflush_size-func 2024-02-22 10:08:52.120597034 -0800 +++ b/arch/x86/pci/common.c 2024-02-22 10:08:52.132597505 -0800 @@ -480,7 +480,7 @@ void pcibios_scan_root(int busnum) void __init pcibios_set_cache_line_size(void) { - pci_dfl_cache_line_size = boot_cpu_data.x86_clflush_size >> 2; + pci_dfl_cache_line_size = x86_clflush_size() >> 2; printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n", pci_dfl_cache_line_size << 2); } diff -puN drivers/gpu/drm/drm_cache.c~x86_clflush_size-func drivers/gpu/drm/drm_cache.c --- a/drivers/gpu/drm/drm_cache.c~x86_clflush_size-func 2024-02-22 10:08:52.124597191 -0800 +++ b/drivers/gpu/drm/drm_cache.c 2024-02-22 10:08:52.132597505 -0800 @@ -52,7 +52,7 @@ drm_clflush_page(struct page *page) { uint8_t *page_virtual; unsigned int i; - const int size = boot_cpu_data.x86_clflush_size; + const int size = x86_clflush_size(); if (unlikely(page == NULL)) return; @@ -160,7 +160,7 @@ drm_clflush_virt_range(void *addr, unsig { #if defined(CONFIG_X86) if (static_cpu_has(X86_FEATURE_CLFLUSH)) { - const int size = boot_cpu_data.x86_clflush_size; + const int size = x86_clflush_size(); void *end = addr + length; addr = (void *)(((unsigned long)addr) & -size); diff -puN drivers/gpu/drm/i915/i915_cmd_parser.c~x86_clflush_size-func drivers/gpu/drm/i915/i915_cmd_parser.c --- a/drivers/gpu/drm/i915/i915_cmd_parser.c~x86_clflush_size-func 2024-02-22 10:08:52.124597191 -0800 +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c 2024-02-22 10:08:52.132597505 -0800 @@ -1203,8 +1203,7 @@ static u32 *copy_batch(struct drm_i915_g */ remain = length; if (dst_needs_clflush & CLFLUSH_BEFORE) - remain = round_up(remain, - boot_cpu_data.x86_clflush_size); + remain = round_up(remain, x86_clflush_size()); ptr = dst; x = offset_in_page(offset); diff -puN drivers/gpu/drm/i915/i915_gem.c~x86_clflush_size-func drivers/gpu/drm/i915/i915_gem.c --- a/drivers/gpu/drm/i915/i915_gem.c~x86_clflush_size-func 2024-02-22 10:08:52.124597191 -0800 +++ b/drivers/gpu/drm/i915/i915_gem.c 2024-02-22 10:08:52.132597505 -0800 @@ -696,7 +696,7 @@ i915_gem_shmem_pwrite(struct drm_i915_ge */ partial_cacheline_write = 0; if (needs_clflush & CLFLUSH_BEFORE) - partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; + partial_cacheline_write = x86_clflush_size() - 1; user_data = u64_to_user_ptr(args->data_ptr); remain = args->size; diff -puN drivers/md/dm-writecache.c~x86_clflush_size-func drivers/md/dm-writecache.c --- a/drivers/md/dm-writecache.c~x86_clflush_size-func 2024-02-22 10:08:52.128597348 -0800 +++ b/drivers/md/dm-writecache.c 2024-02-22 10:08:52.132597505 -0800 @@ -1229,7 +1229,7 @@ static void memcpy_flushcache_optimized( */ #ifdef CONFIG_X86 if (static_cpu_has(X86_FEATURE_CLFLUSHOPT) && - likely(boot_cpu_data.x86_clflush_size == 64) && + likely(x86_clflush_size() == 64) && likely(size >= 768)) { do { memcpy((void *)dest, (void *)source, 64); From patchwork Thu Feb 22 18:39:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205044 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp200189dyb; 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Random bits of the initialization code write random things to it, either blowing away state or tweaking it as they see fit. It's madness. Add some more structure to the process. Introduce an "address configuration" structure just for the boot CPU. This will be used to establish system-wide address space configuration. It is written while bringing up the boot CPU and then read *ONCE* to establish the configuration. Also introduce the first field: phys_addr_reduction_bits. This field will be used by memory encryption hardware that reduces the actual usable address bits beneath what the hardware enumerates. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 14 ++++++++++++++ b/arch/x86/kernel/cpu/common.c | 3 +++ b/arch/x86/kernel/setup.c | 2 ++ 3 files changed, 19 insertions(+) diff -puN arch/x86/include/asm/processor.h~bsp-addr-info arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~bsp-addr-info 2024-02-22 10:08:52.824624673 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:08:52.828624830 -0800 @@ -163,6 +163,19 @@ struct cpuinfo_x86 { unsigned initialized : 1; } __randomize_layout; +/* + * Must be written by the time ->c_bsp_init() completes. + * Consumed in get_cpu_address_sizes(). + */ +struct x86_addr_config { + /* + * How many bits of the expected or enumerated physical + * address space are unavailable? Typically set on + * platforms that use memory encryption. + */ + u8 phys_addr_reduction_bits; +}; + #define X86_VENDOR_INTEL 0 #define X86_VENDOR_CYRIX 1 #define X86_VENDOR_AMD 2 @@ -182,6 +195,7 @@ struct cpuinfo_x86 { */ extern struct cpuinfo_x86 boot_cpu_data; extern struct cpuinfo_x86 new_cpu_data; +extern struct x86_addr_config bsp_addr_config; extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; diff -puN arch/x86/kernel/cpu/common.c~bsp-addr-info arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~bsp-addr-info 2024-02-22 10:08:52.824624673 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:08:52.828624830 -0800 @@ -1125,6 +1125,9 @@ void get_cpu_address_sizes(struct cpuinf } c->x86_cache_bits = c->x86_phys_bits; c->x86_cache_alignment = x86_clflush_size(); + + /* Do this last to avoid affecting ->x86_cache_bits. */ + c->x86_phys_bits -= bsp_addr_config.phys_addr_reduction_bits; } static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) diff -puN arch/x86/kernel/setup.c~bsp-addr-info arch/x86/kernel/setup.c --- a/arch/x86/kernel/setup.c~bsp-addr-info 2024-02-22 10:08:52.824624673 -0800 +++ b/arch/x86/kernel/setup.c 2024-02-22 10:08:52.828624830 -0800 @@ -131,6 +131,8 @@ struct ist_info ist_info; struct cpuinfo_x86 boot_cpu_data __read_mostly; EXPORT_SYMBOL(boot_cpu_data); +struct x86_addr_config bsp_addr_config; + #if !defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64) __visible unsigned long mmu_cr4_features __ro_after_init; #else From patchwork Thu Feb 22 18:39:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205022 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp172384dyb; Thu, 22 Feb 2024 11:50:35 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUXPD+0uRYwbMSfxLft8EVGCWkxSne+oymt+GfrDYAIrocfuS5KTKR7wT3iK2ycTI5unndz/qsf1lM8vADBqGtuEOs5nw== X-Google-Smtp-Source: AGHT+IH4nzJ/2jv6SQYezn48vitFbNsMDJSXo6AT0N1lagEQTINrQ9FuI4Rz/ls+/hPEy8SoSqxJ X-Received: by 2002:a17:902:654c:b0:1dc:1c81:1b19 with SMTP id d12-20020a170902654c00b001dc1c811b19mr7308497pln.3.1708631435789; Thu, 22 Feb 2024 11:50:35 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708631435; cv=pass; d=google.com; s=arc-20160816; b=xiNkm24Yhonl2zXOG1Ff/IawVK2D5SqX6/p+3hI5S2EB6YEcnryCD1SDKNnQJSgHim PfCxifwB/ohrpQpTHSgrZO9E6OVVbKc7qFkqmkHoSaYtLFwc6VVpGVDT6UW56nWxiTvy pw7G3l250nFbCLBV6Nz/E9ACONz+eFJz7kWtAVzCo4gSANcqs1kNUBDmEHIrZ2wdCQws jX4QQt368eHIrh3vrnZoTu78jFHm8g1mM8Qx1VM6AexdSqMDJfCQred1u2zULrx79/0U zcUIw513HAQHw/y2tIYyXo6+YIagGDybJSy2mGK7L102pAeQ7uwrB4lL2/I4Wx0Jb2NC 5O8A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=obDj8eqK/ZYdMdzQOof2KYJRL+yChq1JoyHapq3K/N0=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=mx9cMXky3FAnsVQtYQJPjyXZcb0QaetFFN2MlJJYPe7aY0erv9ddFAu9gvxKB923MU 0r86GMyDK+VWDjEveaxAFjFDxfZEHWMOVRVZNARqtISnTM19luTzcosu6ItPxxNKjJVF H+sGbKzqIGou/MWIKrnpC8sGNkX2P3wmn9uOSxhBgl6/673QCdjDo6aha82f/POoXUha L4lU7j1HKSMwmLLo++tlFsH9QD519l6ZnS2ZHEjqBloeLy2Bl3B+KlyxJBQNKK9BJ5Ia CnJ+F0tdkAV4S9p8ZydY2U8Z1obg/SXjoPJ5k0wqxhcBmTiCvLuKio9hOBCI1ZslR59T 4nmQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=TK4MxH1A; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77164-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77164-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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This has led to all kinds of interesting ordering bugs at boot. Move it away from random fiddling and over to 'bsp_addr_config'. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/amd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff -puN arch/x86/kernel/cpu/amd.c~amd-phys_addr_reduction_bits arch/x86/kernel/cpu/amd.c --- a/arch/x86/kernel/cpu/amd.c~amd-phys_addr_reduction_bits 2024-02-22 10:08:53.340644930 -0800 +++ b/arch/x86/kernel/cpu/amd.c 2024-02-22 10:08:53.344645087 -0800 @@ -622,7 +622,8 @@ static void early_detect_mem_encrypt(str * will be a value above 32-bits this is still done for * CONFIG_X86_32 so that accurate values are reported. */ - c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; + bsp_addr_config.phys_addr_reduction_bits = + (cpuid_ebx(0x8000001f) >> 6) & 0x3f; if (IS_ENABLED(CONFIG_X86_32)) goto clear_all; From patchwork Thu Feb 22 18:39:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205142 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp280998dyb; Thu, 22 Feb 2024 15:31:52 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVqnnRVURJfmCDKPjedqtYYuH8HQkmjDMFaCNqgv8rBU+tfy0yokzCPaJkx7o/X8Les1xF05xso5GsJ7r2WHDcbruG0iA== X-Google-Smtp-Source: AGHT+IHIx7Z3g+9PVbZPbRkdD1lPTreKsNEQSL7KYjp6l+Bpi0giy0DHY0pXdTCxxl3tbCTp9KB5 X-Received: by 2002:a17:906:1c4b:b0:a3e:fd31:86cc with SMTP id l11-20020a1709061c4b00b00a3efd3186ccmr154314ejg.47.1708644711934; Thu, 22 Feb 2024 15:31:51 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708644711; cv=pass; d=google.com; s=arc-20160816; b=MNsiZsTzngMU2uNmGBVH6F0IxqoYOxfGDBuvgDqCiYjBwByK0FqnRuXdubAuKUJV2p ijcDy/Pe104IG/s5JejFmR49wi00WPUcJ6lf2162p9No+HWH5bRMfk3Ql3riikRweVaM kYZ2gujPln8I8eGkIjYolmbKZSV4s/8xcI0NLxQYOpPrXSQsBa5OjzP7RC2f6dd1F7yl dKm9GVHLlhUS/4DDmuyqtHrhF3DPrORmBTdQZK/zuI14Ab/ict44C54u2FUsQTGAoZJy +VgWDJEadeqbWPzY7z2sSAiupsonXwuyvG/PjBGkgvlwuRZKK0Wa0Kybu9Ob2NzijAng Po2g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=kyjegd26nBFTlzN9xDSHgU7irv0o8uKISl3Apocww9M=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=KmAgoShDvAoSsyKBBGHscy4RC6wcsiWzxz06nSQS9Ps2ldfPQelSpGOmBVwybsd7/2 YOlm+BXAodWe431r5KjewwxQkx6oq4G3qcci83Ez6+Tdd94fYbT2nqROrQ2pe/tm7E/m n1+3M7xgY0VD2xVmwwBXdlbjK64+tqlpUZ2Dh/3ks7SIj5uFIPAzxhMLyZAdPb9SLREM I9IRIDSSZgYLp3s7dub5oR8YPpEhRPDW5MTThPzMUePk8NXkhgYYU74Nc3jKEiG3TEiz nFDbbXdxzYMWtBwjm3jxGEKoWp8FC86UO1OlTcUsdKmtA/rtAtWrmIClVIRIve9BTbI/ xIZQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BqgdZSss; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77165-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77165-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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This is currently called for *each* CPU, but practically only done on the boot CPU because of 'mktme_status'. Move it from the "each CPU" ->c_init() function to ->c_bsp_init() where the whole thing only gets called once ever. This also necessitates moving detect_tme() and its entourage around in the file. Signed-off-by: Dave Hansen Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang --- b/arch/x86/kernel/cpu/intel.c | 174 +++++++++++++++++++++--------------------- 1 file changed, 87 insertions(+), 87 deletions(-) diff -puN arch/x86/kernel/cpu/intel.c~intel-move-TME-detection arch/x86/kernel/cpu/intel.c --- a/arch/x86/kernel/cpu/intel.c~intel-move-TME-detection 2024-02-22 10:08:53.820663775 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2024-02-22 10:08:53.824663932 -0800 @@ -324,9 +324,96 @@ static void early_init_intel(struct cpui detect_ht_early(c); } +#define MSR_IA32_TME_ACTIVATE 0x982 + +/* Helpers to access TME_ACTIVATE MSR */ +#define TME_ACTIVATE_LOCKED(x) (x & 0x1) +#define TME_ACTIVATE_ENABLED(x) (x & 0x2) + +#define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */ +#define TME_ACTIVATE_POLICY_AES_XTS_128 0 + +#define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ + +#define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */ +#define TME_ACTIVATE_CRYPTO_AES_XTS_128 1 + +/* Values for mktme_status (SW only construct) */ +#define MKTME_ENABLED 0 +#define MKTME_DISABLED 1 +#define MKTME_UNINITIALIZED 2 +static int mktme_status = MKTME_UNINITIALIZED; + +static void detect_tme(struct cpuinfo_x86 *c) +{ + u64 tme_activate, tme_policy, tme_crypto_algs; + int keyid_bits = 0, nr_keyids = 0; + static u64 tme_activate_cpu0 = 0; + + rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); + + if (mktme_status != MKTME_UNINITIALIZED) { + if (tme_activate != tme_activate_cpu0) { + /* Broken BIOS? */ + pr_err_once("x86/tme: configuration is inconsistent between CPUs\n"); + pr_err_once("x86/tme: MKTME is not usable\n"); + mktme_status = MKTME_DISABLED; + + /* Proceed. We may need to exclude bits from x86_phys_bits. */ + } + } else { + tme_activate_cpu0 = tme_activate; + } + + if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { + pr_info_once("x86/tme: not enabled by BIOS\n"); + mktme_status = MKTME_DISABLED; + return; + } + + if (mktme_status != MKTME_UNINITIALIZED) + goto detect_keyid_bits; + + pr_info("x86/tme: enabled by BIOS\n"); + + tme_policy = TME_ACTIVATE_POLICY(tme_activate); + if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128) + pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy); + + tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate); + if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) { + pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n", + tme_crypto_algs); + mktme_status = MKTME_DISABLED; + } +detect_keyid_bits: + keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); + nr_keyids = (1UL << keyid_bits) - 1; + if (nr_keyids) { + pr_info_once("x86/mktme: enabled by BIOS\n"); + pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids); + } else { + pr_info_once("x86/mktme: disabled by BIOS\n"); + } + + if (mktme_status == MKTME_UNINITIALIZED) { + /* MKTME is usable */ + mktme_status = MKTME_ENABLED; + } + + /* + * KeyID bits effectively lower the number of physical address + * bits. Update cpuinfo_x86::x86_phys_bits accordingly. + */ + c->x86_phys_bits -= keyid_bits; +} + static void bsp_init_intel(struct cpuinfo_x86 *c) { resctrl_cpu_detect(c); + + if (cpu_has(c, X86_FEATURE_TME)) + detect_tme(c); } #ifdef CONFIG_X86_32 @@ -482,90 +569,6 @@ static void srat_detect_node(struct cpui #endif } -#define MSR_IA32_TME_ACTIVATE 0x982 - -/* Helpers to access TME_ACTIVATE MSR */ -#define TME_ACTIVATE_LOCKED(x) (x & 0x1) -#define TME_ACTIVATE_ENABLED(x) (x & 0x2) - -#define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */ -#define TME_ACTIVATE_POLICY_AES_XTS_128 0 - -#define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ - -#define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */ -#define TME_ACTIVATE_CRYPTO_AES_XTS_128 1 - -/* Values for mktme_status (SW only construct) */ -#define MKTME_ENABLED 0 -#define MKTME_DISABLED 1 -#define MKTME_UNINITIALIZED 2 -static int mktme_status = MKTME_UNINITIALIZED; - -static void detect_tme(struct cpuinfo_x86 *c) -{ - u64 tme_activate, tme_policy, tme_crypto_algs; - int keyid_bits = 0, nr_keyids = 0; - static u64 tme_activate_cpu0 = 0; - - rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); - - if (mktme_status != MKTME_UNINITIALIZED) { - if (tme_activate != tme_activate_cpu0) { - /* Broken BIOS? */ - pr_err_once("x86/tme: configuration is inconsistent between CPUs\n"); - pr_err_once("x86/tme: MKTME is not usable\n"); - mktme_status = MKTME_DISABLED; - - /* Proceed. We may need to exclude bits from x86_phys_bits. */ - } - } else { - tme_activate_cpu0 = tme_activate; - } - - if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { - pr_info_once("x86/tme: not enabled by BIOS\n"); - mktme_status = MKTME_DISABLED; - return; - } - - if (mktme_status != MKTME_UNINITIALIZED) - goto detect_keyid_bits; - - pr_info("x86/tme: enabled by BIOS\n"); - - tme_policy = TME_ACTIVATE_POLICY(tme_activate); - if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128) - pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy); - - tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate); - if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) { - pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n", - tme_crypto_algs); - mktme_status = MKTME_DISABLED; - } -detect_keyid_bits: - keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); - nr_keyids = (1UL << keyid_bits) - 1; - if (nr_keyids) { - pr_info_once("x86/mktme: enabled by BIOS\n"); - pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids); - } else { - pr_info_once("x86/mktme: disabled by BIOS\n"); - } - - if (mktme_status == MKTME_UNINITIALIZED) { - /* MKTME is usable */ - mktme_status = MKTME_ENABLED; - } - - /* - * KeyID bits effectively lower the number of physical address - * bits. Update cpuinfo_x86::x86_phys_bits accordingly. - */ - c->x86_phys_bits -= keyid_bits; -} - static void init_cpuid_fault(struct cpuinfo_x86 *c) { u64 msr; @@ -702,9 +705,6 @@ static void init_intel(struct cpuinfo_x8 init_ia32_feat_ctl(c); - if (cpu_has(c, X86_FEATURE_TME)) - detect_tme(c); - init_intel_misc_features(c); split_lock_init(); From patchwork Thu Feb 22 18:39:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205141 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp280963dyb; Thu, 22 Feb 2024 15:31:46 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWqj7VjG/N5LOQSG5oQAJNPlw1uE2w7zgu5Fvxq3eGBTOtSUkIFN5ce3n0CExUuluvsJYgZZPH2vMiG9E3Vex2ih+/zVA== X-Google-Smtp-Source: AGHT+IHHvCm5XLQjzZeT2oUptSxmvDu+rUCd9BLljLEtXBX0GLL5Qc2sOc9gF9hz5LIuzrrdMBhM X-Received: by 2002:a17:907:1704:b0:a3f:3ed5:d6cf with SMTP id le4-20020a170907170400b00a3f3ed5d6cfmr150582ejc.70.1708644706606; Thu, 22 Feb 2024 15:31:46 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708644706; cv=pass; d=google.com; s=arc-20160816; b=h7/6XZ++yR7cW433AYV5zuWu0TIeD+lPJoh2gQhbwt4T+CoJDVtezqODkOKqQslBEk OfjbS4R7ln1OLc7xtv3FIJp54q6P0bn6E2VU4RJ+XKDA8lilH/ElUJnn3wlzjPFc6hAQ V+rcYc0UTnJmMsbj7gzImfghK5RJb9QE779Eqk0To+4imzcPU98EqKhK2C1fLhT20QsW J9cV1IbtoR6ZsUkhF5Z5DHLCvGKyBIZT0hIuGzF4XYwC+g6LfWGXoyXKsnpaXHN94nx4 U2AZlRX+m+YChclwAPKWbYHl5QzIJB3TCdOBE9k5mUZnUc5wUHUeQ3a6MaGRJztSdV4m bESQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=Omfco2XE1bingxHSv1DlDZNE+xYyk4VOqXBCKicVeL0=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=PMCCCn8kkdbC8V1+zMIO0rGnOdgk2m3NSmtTgvxjpqpo4b194HZf6N4McfxQIdeSTQ SsxD1j7qf9zbvkC39tjGCUwLgq1n404m8FjOXDbHSlGMPSDYDvBHF1gMRPP+0gMkiqbc 7v5ZMsJqD984PzhjtBegt2xPhC6jmis5NzaCozOalJ+38gnRWbVm5q2qWyk+TFgeyMos ecR8PXuSmVPTpOoVhPUmkZs7b6BXYpEn011NKBSEDXfzwL2aoYCq5LfISUS59P/P4Mym b70KkZVW0EoN9WQf/k5jZA2bva2tOH3bsd8g9vH/if6KElbCAdfcCBr5vLAVeoXwARr6 QTjQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=HAqOVzGt; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77166-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77166-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/intel.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff -puN arch/x86/kernel/cpu/intel.c~intel-addr-reduce arch/x86/kernel/cpu/intel.c --- a/arch/x86/kernel/cpu/intel.c~intel-addr-reduce 2024-02-22 10:08:54.296682462 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2024-02-22 10:08:54.296682462 -0800 @@ -401,11 +401,8 @@ detect_keyid_bits: mktme_status = MKTME_ENABLED; } - /* - * KeyID bits effectively lower the number of physical address - * bits. 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This one is an oldie but a goodie: af9c142de94e ("[PATCH] x86_64: Force correct address space size for MTRR on some 64bit Intel Xeons") Evidently, the CPUs in question "report 40bit, but only have 36bits of physical address space." Since there's now a handy way to reduce the amount of physical address bits, use that to reduce from 40->36. This means there are now two (Intel) users of the address bits reduction feature. There is no way a 2005-era CPU will ever have TME, but it is still nice to be more explicit about the possibility of a collision. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/intel.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff -puN arch/x86/kernel/cpu/intel.c~intel-phys-addr-errata arch/x86/kernel/cpu/intel.c --- a/arch/x86/kernel/cpu/intel.c~intel-phys-addr-errata 2024-02-22 10:08:54.772701150 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2024-02-22 10:08:54.776701306 -0800 @@ -242,11 +242,6 @@ static void early_init_intel(struct cpui c->x86_cache_alignment = 128; #endif - /* CPUID workaround for 0F33/0F34 CPU */ - if (c->x86 == 0xF && c->x86_model == 0x3 - && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) - c->x86_phys_bits = 36; - /* * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate * with P/T states and does not stop in deep C-states. @@ -344,7 +339,7 @@ static void early_init_intel(struct cpui #define MKTME_UNINITIALIZED 2 static int mktme_status = MKTME_UNINITIALIZED; -static void detect_tme(struct cpuinfo_x86 *c) +static int detect_tme(struct cpuinfo_x86 *c) { u64 tme_activate, tme_policy, tme_crypto_algs; int keyid_bits = 0, nr_keyids = 0; @@ -368,7 +363,7 @@ static void detect_tme(struct cpuinfo_x8 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { pr_info_once("x86/tme: not enabled by BIOS\n"); mktme_status = MKTME_DISABLED; - return; + return 0; } if (mktme_status != MKTME_UNINITIALIZED) @@ -401,16 +396,28 @@ detect_keyid_bits: mktme_status = MKTME_ENABLED; } - /* KeyID bits effectively lower the number of physical address bits */ - bsp_addr_config.phys_addr_reduction_bits = keyid_bits; + return keyid_bits; } static void bsp_init_intel(struct cpuinfo_x86 *c) { + int keyid_bits = 0; + resctrl_cpu_detect(c); if (cpu_has(c, X86_FEATURE_TME)) - detect_tme(c); + keyid_bits = detect_tme(c); + + /* KeyID bits effectively lower the number of physical address bits */ + bsp_addr_config.phys_addr_reduction_bits = keyid_bits; + + /* CPUID workaround for 0F33/0F34 CPU */ + if (c->x86 == 0xF && c->x86_model == 0x3 + && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) { + /* Warn if MKTME and this workaround collide: */ + WARN_ON_ONCE(keyid_bits); + bsp_addr_config.phys_addr_reduction_bits = 4; + } } #ifdef CONFIG_X86_32 From patchwork Thu Feb 22 18:39:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205132 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp278388dyb; Thu, 22 Feb 2024 15:25:07 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWRXqImyRMQRLpUztcYnuYXgvjCuH1WGnRbiib1qzVCB7LKv7UbOa+Cy2mMQ+RgSOF3Df/1AoFa1gzeYIzqkcdztZYg1g== X-Google-Smtp-Source: AGHT+IFQwEWChGaE01zqI9b74oesjFibORgPJgzphE2pwJh9bhYgNG0fvDNScT4+GmGvt13uPlr8 X-Received: by 2002:a17:903:41ca:b0:1db:d66e:cd15 with SMTP id u10-20020a17090341ca00b001dbd66ecd15mr417475ple.59.1708644307645; Thu, 22 Feb 2024 15:25:07 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708644307; cv=pass; d=google.com; s=arc-20160816; b=YqEsFtj/NwW8zwEH+1ajSH62wpBgWae6r3zbxiVOFSfXgHZPkFQkBSRjlNcS+eQ0gV ybSsMPObj6KKpdfsOFzSt1ws6yq+5/bFZ5hIHEZubVsHZH+ULZYaJuOMbXro4289v7T9 ysfKB0lwq+emE59lLqvzTbVTpgcPQ6DxIeokN1y3vU4ueLPGZJtigRQoxo52s8Vcv5eN T3Z67eFdi/DrNrb2+h/s9WBNO0DHLMtADlQBosEU7+/G+kTRrqpI3XFwue2NE9zz3HbQ CDQ0GlZgS1GUt5jazPcKlPWm9/IaKkBe88sae4XjXTeysrYsDT0d8rQKhbte1WzTuk3k IE5g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=u0z8UH8mt4jvSoCLr8BlEBk5fkbd0rQ9j6hyH+Pq1YM=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=vb5+Axsxh3J+5HnRB6NdDrXI2LgY12roXPjc8tlXc8wrDd0XQxvzRdylk+X1uQC1G1 HiPCzaRR/076q+XF+ZpOm3F5qYq3bBxIBWScfHM+1pc185qumQzWf5Z3hhcOz07TVCa0 f6mGNCkHutH+PY/8xL4o395N6FRSFqOdTX6qGjEs9zHTr66u6fAxvsIG+uImb4UiPoU0 z1Gi2bj//m9yrKOoNcmmq8wxi3bwiDlH7nf0BV5flLiNQF4PY1MRke9UBPtNxHLUaix4 WATcFzYrRPWaOX/PvLfDJ2buEpb5XdVR95pt5UcHO3w9CwGAzig+iC8bBCharrpAuvZx rhTQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=FcaNhyrb; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77168-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77168-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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The boot CPU values were also established long before reaching here. This can only serve to sow chaos. Remove the twiddling. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/common.c | 2 -- 1 file changed, 2 deletions(-) diff -puN arch/x86/kernel/cpu/common.c~no-default-bit-setting-phys arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~no-default-bit-setting-phys 2024-02-22 10:08:55.256720151 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:08:55.260720308 -0800 @@ -1827,12 +1827,10 @@ static void identify_cpu(struct cpuinfo_ c->topo.l2c_id = BAD_APICID; #ifdef CONFIG_X86_64 c->x86_clflush_size = 64; - c->x86_phys_bits = 36; c->x86_virt_bits = 48; #else c->cpuid_level = -1; /* CPUID not detected */ c->x86_clflush_size = 32; - c->x86_phys_bits = 32; c->x86_virt_bits = 32; #endif c->x86_cache_alignment = x86_clflush_size(); From patchwork Thu Feb 22 18:39:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 204997 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp139303dyb; Thu, 22 Feb 2024 10:46:58 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCV/9NtSL+X0pjWI4be0TBChWcS/+InotivF9eHzWW3/VJDm7Q/a6IMoRxq/++0m57zO5Bxo5Ho3vtN+ZZ2ChMadU835qg== X-Google-Smtp-Source: AGHT+IEpK7YH2TNVJUtjRJgeTdx+tsJZfpOBV2NQA5YLH0ltDDkB919mmSHX3IANibaVH5HsyUP2 X-Received: by 2002:a05:620a:34a:b0:785:ab77:fe6c with SMTP id t10-20020a05620a034a00b00785ab77fe6cmr21201455qkm.6.1708627618603; Thu, 22 Feb 2024 10:46:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708627618; cv=pass; d=google.com; s=arc-20160816; b=HU9iekBRu0bLtdjbj8EMqECM56Q/7kmoZS8sUiayVILcgMHuOxCYp2+zaldgDFU+S5 cq15FJtqdVEVbkmln+h9tN3BpshlwKlLt8gpr10hL7k3lecgOQfr8KkcOJMFEGGsfTY+ iobKxCakueiqv8gyLjvRsuIToY0fv5UplI+nvmQMN3sayAgiZY26PJRuvP2TJIWudM33 bgO9yOB1DLBkM9m8Pm81IxnRN1d0ArCnIDZ+J6Clwtvq7pgYdwUX6Hq0i/i2J7mqM/R8 VKltLLMMmSWrDVgptP75DP5L/mTw9hJsnAqHnRNO4TUHMAUvekQA4IEryOy7WygsoUtJ jUWw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=boncQHFCDeP953DR1zfMekeDxZk8HQLgMTTkGBGFyiI=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=kPWMGRPooCYD8omfW3l6qIQo48JAWYUJ4z9urVHUlnWKsfWPSXNYEhWD7dlPM6Q7zJ yBye1vqk/lUopJbvSwj/wOhoy34gRkIbOhhqhmBGvz6W8jBBSwHyXLbpxnpRXm+/nipj 1npjLtUG96yVEHnTU5F+X4AWdcAX9d8mNmCfMEZJ5X2jZuuyxucE3T3BlmyB+XJIMkdh 2GDyaL/5+fcpDvW2mBWx387ItMdb3ID90kcBiauUPsWE7ezfGeluJJQ3Q9IvxjVFZSH8 ywr9yBoDAj0Ij426vAoFYiEhxJ8pyNqjbiTd2L4Ee/mO7T0VQCPHtyHpO7UXrsV1YJLr DI3A==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=U++5FIQ9; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77169-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77169-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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It is useless now. Remove it. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/setup.c | 1 - 1 file changed, 1 deletion(-) diff -puN arch/x86/kernel/setup.c~no-early-max_phys_bits-assign arch/x86/kernel/setup.c --- a/arch/x86/kernel/setup.c~no-early-max_phys_bits-assign 2024-02-22 10:08:55.736738995 -0800 +++ b/arch/x86/kernel/setup.c 2024-02-22 10:08:55.740739152 -0800 @@ -752,7 +752,6 @@ void __init setup_arch(char **cmdline_p) __flush_tlb_all(); #else printk(KERN_INFO "Command line: %s\n", boot_command_line); - boot_cpu_data.x86_phys_bits = MAX_PHYSMEM_BITS; #endif /* From patchwork Thu Feb 22 18:39:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205046 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp201242dyb; Thu, 22 Feb 2024 12:48:33 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVWwshUpa586T8u9qXjUfyXR9R9gvFQ/buCBv2CyFCT1ZXxffvtFGb1qfKJCkCObX4/kDeIlBAQW8JNdDCYsZUuS8wniA== X-Google-Smtp-Source: AGHT+IEMkky8MoacS4A7UTCjqZmBHm02FlJCk/yrfsrSRZqFJLbHJHC77/vXaRWYMvepwDLiUNw5 X-Received: by 2002:a05:6a20:e605:b0:1a0:686b:afec with SMTP id my5-20020a056a20e60500b001a0686bafecmr19017732pzb.10.1708634913635; Thu, 22 Feb 2024 12:48:33 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708634913; cv=pass; d=google.com; s=arc-20160816; b=V2sFDh3uQHQuD93Nb42nmybf4KEVSJLTr/jXmuq+KTm4yUXZD6ubArDlC6KpQCWeP8 rIdEoKpMgxbIEXLmic1QtnQPkjVs9eSweWuY2YBMQIrBTVCVb0zNhSp3ZHzp6sZdsUvs 3S5WlPKQ6WYSHtBwkTy4egA4NAQVLRTiObX88ye5H8BBLAfQYzye0trgt2gbz5vIqYil 58UyO+xDHg5e5RuFgjQHxmN7sQsdV7iMuSmI8Exl6nu4ok0mhEW64mHpwvPV1Nl429x6 FnJROXrvLFwiyevAY5TTQa6Q/5IZK4pEBxlwJgfsdzrbmbFm31k4sr49MwZkEY2kvceP 1cCg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=DrQnbpKKxPi1i7oyl0M5Fi8VKe/pSLPplt8gUuBjEmg=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=hnFs+GxT2Y57AG1oo18H7X2kS5OJW8n7KOX434bGkxXELZfs4gZ1dZSDWH+18RlNDB Fom+QG93hzdDdLQCLSrNX9wcCuZRveS9ozjBRrPOO3ldVRVVH7cXCG3iNCS4iI/226e1 wAuRkCapbLBxi4S4l7A1TgOjnZD6/r5MOjDU4v+mvs9NFXjH0zxg6rBWCqftzHat2uBp CKFwIXg/k1mSgZ3ihFdZFo4eWeemzcF6c3D3F3gnf7cKxkPB1DqWYP2Bfpi9ibxqKms2 mOBoPAG+5+uZoeCbcqvX7XRTD4mVEumOkceDlLbzwjWjsaIXTRecuw4FK4ZTkws8rOlp U1SQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=YsxrWZa+; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77170-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77170-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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The only remaining references are to 'boot_cpu_data' via the x86_phys_bits() helper. This means the farce that x86_phys_bits is per-cpu data can end. Remove it from cpuinfo_x86 and add it to a new global data structure: 'x86_config'. (Better names welcome) Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 16 ++++++++++++++-- b/arch/x86/kernel/cpu/common.c | 12 ++++++------ b/arch/x86/kernel/setup.c | 1 + 3 files changed, 21 insertions(+), 8 deletions(-) diff -puN arch/x86/include/asm/processor.h~no-cpu-data-phys_bits arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~no-cpu-data-phys_bits 2024-02-22 10:08:56.220757996 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:08:56.228758310 -0800 @@ -118,7 +118,6 @@ struct cpuinfo_x86 { __u32 vmx_capability[NVMXINTS]; #endif __u8 x86_virt_bits; - __u8 x86_phys_bits; /* CPUID returned core id bits: */ __u8 x86_coreid_bits; /* Max extended CPUID function supported: */ @@ -176,6 +175,19 @@ struct x86_addr_config { u8 phys_addr_reduction_bits; }; +/* + * System-wide configuration that is shared by all processors. + * + * Built in early_cpu_init() on the boot CPU and and never + * modified after that. + */ +struct x86_sys_config { + /* Physical address bits supported by all processors */ + u8 phys_bits; +}; + +extern struct x86_sys_config x86_config; + #define X86_VENDOR_INTEL 0 #define X86_VENDOR_CYRIX 1 #define X86_VENDOR_AMD 2 @@ -783,7 +795,7 @@ static inline void weak_wrmsr_fence(void static inline u8 x86_phys_bits(void) { - return boot_cpu_data.x86_phys_bits; + return x86_config.phys_bits; } static inline u8 x86_virt_bits(void) diff -puN arch/x86/kernel/cpu/common.c~no-cpu-data-phys_bits arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~no-cpu-data-phys_bits 2024-02-22 10:08:56.224758153 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:08:56.228758310 -0800 @@ -1107,27 +1107,27 @@ void get_cpu_address_sizes(struct cpuinf cpuid(0x80000008, &eax, &ebx, &ecx, &edx); c->x86_virt_bits = (eax >> 8) & 0xff; - c->x86_phys_bits = eax & 0xff; + x86_config.phys_bits = eax & 0xff; } else { if (IS_ENABLED(CONFIG_X86_64)) { + x86_config.phys_bits = 36; c->x86_clflush_size = 64; - c->x86_phys_bits = 36; c->x86_virt_bits = 48; } else { + x86_config.phys_bits = 32; c->x86_clflush_size = 32; c->x86_virt_bits = 32; - c->x86_phys_bits = 32; if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) - c->x86_phys_bits = 36; + x86_config.phys_bits = 36; } } - c->x86_cache_bits = c->x86_phys_bits; + c->x86_cache_bits = x86_config.phys_bits; c->x86_cache_alignment = x86_clflush_size(); /* Do this last to avoid affecting ->x86_cache_bits. */ - c->x86_phys_bits -= bsp_addr_config.phys_addr_reduction_bits; + x86_config.phys_bits -= bsp_addr_config.phys_addr_reduction_bits; } static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) diff -puN arch/x86/kernel/setup.c~no-cpu-data-phys_bits arch/x86/kernel/setup.c --- a/arch/x86/kernel/setup.c~no-cpu-data-phys_bits 2024-02-22 10:08:56.224758153 -0800 +++ b/arch/x86/kernel/setup.c 2024-02-22 10:08:56.228758310 -0800 @@ -132,6 +132,7 @@ struct cpuinfo_x86 boot_cpu_data __read_ EXPORT_SYMBOL(boot_cpu_data); struct x86_addr_config bsp_addr_config; +struct x86_sys_config x86_config __read_mostly; #if !defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64) __visible unsigned long mmu_cr4_features __ro_after_init; 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The only remaining references are to 'boot_cpu_data' via the x86_virt_bits() helper. This means the farce that x86_virt_bits is per-cpu data can end. Remove it from cpuinfo_x86 and add it to 'x86_config'. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 6 +++--- b/arch/x86/kernel/cpu/common.c | 8 +++----- b/arch/x86/mm/maccess.c | 9 +++++---- 3 files changed, 11 insertions(+), 12 deletions(-) diff -puN arch/x86/include/asm/processor.h~no-cpu-data-virt_bits arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~no-cpu-data-virt_bits 2024-02-22 10:08:56.748778725 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:08:56.752778882 -0800 @@ -117,7 +117,6 @@ struct cpuinfo_x86 { #ifdef CONFIG_X86_VMX_FEATURE_NAMES __u32 vmx_capability[NVMXINTS]; #endif - __u8 x86_virt_bits; /* CPUID returned core id bits: */ __u8 x86_coreid_bits; /* Max extended CPUID function supported: */ @@ -182,8 +181,9 @@ struct x86_addr_config { * modified after that. */ struct x86_sys_config { - /* Physical address bits supported by all processors */ + /* Address bits supported by all processors */ u8 phys_bits; + u8 virt_bits; }; extern struct x86_sys_config x86_config; @@ -800,7 +800,7 @@ static inline u8 x86_phys_bits(void) static inline u8 x86_virt_bits(void) { - return boot_cpu_data.x86_virt_bits; + return x86_config.virt_bits; } static inline u8 x86_clflush_size(void) diff -puN arch/x86/kernel/cpu/common.c~no-cpu-data-virt_bits arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~no-cpu-data-virt_bits 2024-02-22 10:08:56.748778725 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:08:56.752778882 -0800 @@ -1106,17 +1106,17 @@ void get_cpu_address_sizes(struct cpuinf if (vp_bits_from_cpuid) { cpuid(0x80000008, &eax, &ebx, &ecx, &edx); - c->x86_virt_bits = (eax >> 8) & 0xff; + x86_config.virt_bits = (eax >> 8) & 0xff; x86_config.phys_bits = eax & 0xff; } else { if (IS_ENABLED(CONFIG_X86_64)) { x86_config.phys_bits = 36; + x86_config.virt_bits = 48; c->x86_clflush_size = 64; - c->x86_virt_bits = 48; } else { x86_config.phys_bits = 32; + x86_config.virt_bits = 32; c->x86_clflush_size = 32; - c->x86_virt_bits = 32; if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) @@ -1827,11 +1827,9 @@ static void identify_cpu(struct cpuinfo_ c->topo.l2c_id = BAD_APICID; #ifdef CONFIG_X86_64 c->x86_clflush_size = 64; - c->x86_virt_bits = 48; #else c->cpuid_level = -1; /* CPUID not detected */ c->x86_clflush_size = 32; - c->x86_virt_bits = 32; #endif c->x86_cache_alignment = x86_clflush_size(); memset(&c->x86_capability, 0, sizeof(c->x86_capability)); diff -puN arch/x86/mm/maccess.c~no-cpu-data-virt_bits arch/x86/mm/maccess.c --- a/arch/x86/mm/maccess.c~no-cpu-data-virt_bits 2024-02-22 10:08:56.752778882 -0800 +++ b/arch/x86/mm/maccess.c 2024-02-22 10:08:56.752778882 -0800 @@ -16,11 +16,12 @@ bool copy_from_kernel_nofault_allowed(co return false; /* - * Allow everything during early boot before 'x86_virt_bits' - * is initialized. Needed for instruction decoding in early - * exception handlers. + * Allow everything during early boot before 'virt_bits' is + * initialized. Needed for instruction decoding in early + * exception handlers. Avoid the helper because it may do + * error checking for being uninitiazed. */ - if (!x86_virt_bits()) + if (!x86_config.virt_bits) return true; return __is_canonical_address(vaddr, x86_virt_bits()); From patchwork Thu Feb 22 18:39:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205035 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp186578dyb; Thu, 22 Feb 2024 12:15:31 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVA56jklfh98UipMibtagDEYj5rb06Gz6bMiIjZv0KgYe2xmHnjJRI4g0+UxBhEfPBfRIu33wdLcnrlWJOxo+WebnJj7Q== X-Google-Smtp-Source: AGHT+IGJfFtEAsLPpwQ4bEX2+8lOPj6xJBGFgT2yj6X6wbfFnUWjePW+Dmqd94eQsc/r+v7WQS7A X-Received: by 2002:ac8:578d:0:b0:42e:5aca:cdd1 with SMTP id v13-20020ac8578d000000b0042e5acacdd1mr255629qta.12.1708632931156; Thu, 22 Feb 2024 12:15:31 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708632931; cv=pass; d=google.com; s=arc-20160816; b=gnVHgLglXdix/l8O8lVXx1IgJX3pYE1mByJ+XnbNFp1XEsOE5veBdW6qDQF4EUw5tb R+DAVt0AKl/VnJhZ3OJtokDfaEG6J/jaT0E6rLzoHL0f0iPELzhDe3sbVP/jyFgR9GcU OnkTUynkrQ8+bTtRQK+4bTpoe01qpdb9tFgPFMatiLGyoRSffkRzezzS+C43wsUIIUFd 2RDO18EO56GuyPUgflbwWohkXM0LI7ls9yhYKqMHNY1AcE/X8ryyIa72zkYbtwD6/ody SV6pwlaW/pJdd48NWJPeIF+suB3Ts86zlW2P2yvJ8sd9gk1ZkZcbHygqnwlDt5aEymx5 YLEw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=4TjDH1Log44PBm3k7sIleX37H9Ks6zq6qh155EmZvec=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=WCudXOh4juA+K4PdMKck4lMPUeenv6Opmy7N1nuolKrn1f42A8xqXNZ0eja5IVSl8z IuI7LaNpwGPe+3vfrxF8vIgfqzjSnc5ghdDk7pbFHL8anoufzckbLw/+0rrnxTPg9nJs rGjYk/+JJ8ZY0fvh/akRthU/WTWlRwkinbB6R1Ng27rCPweOSHizycLQ1AUXDjbbCPUp weGgnfAAqEJrhfBPwpHHa/BFpNaLgcvZuIK7KVG4ixITvpFAA1wevf/bmXgjaXO1uQJz jUzV2NiNThS9xda1MXNg4b4WfMdgfBIEIn0gEYzDiJWJN4V8MHru5w8QMufkOGxGtrKj JabA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=YZHNMckL; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77172-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77172-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Stop initializing it per-cpu on (some) Centaur CPUs and move it to a new BSP init function. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/centaur.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff -puN arch/x86/kernel/cpu/centaur.c~centaur-c_early_init arch/x86/kernel/cpu/centaur.c --- a/arch/x86/kernel/cpu/centaur.c~centaur-c_early_init 2024-02-22 10:08:57.268799139 -0800 +++ b/arch/x86/kernel/cpu/centaur.c 2024-02-22 10:08:57.268799139 -0800 @@ -61,12 +61,8 @@ static void init_c3(struct cpuinfo_x86 * if (c->x86_model >= 6 && c->x86_model < 9) set_cpu_cap(c, X86_FEATURE_3DNOW); #endif - if (c->x86 == 0x6 && c->x86_model >= 0xf) { - c->x86_cache_alignment = x86_clflush_size() * 2; - set_cpu_cap(c, X86_FEATURE_REP_GOOD); - } - - if (c->x86 >= 7) + if ((c->x86 == 0x6 && c->x86_model >= 0xf) || + (c->x86 >= 7)) set_cpu_cap(c, X86_FEATURE_REP_GOOD); } @@ -217,6 +213,12 @@ static void init_centaur(struct cpuinfo_ init_ia32_feat_ctl(c); } +static void bsp_init_centaur(struct cpuinfo_x86 *c) +{ + if (c->x86 == 0x6 && c->x86_model >= 0xf) + c->x86_cache_alignment = x86_clflush_size() * 2; +} + #ifdef CONFIG_X86_32 static unsigned int centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) @@ -241,6 +243,7 @@ static const struct cpu_dev centaur_cpu_ .c_vendor = "Centaur", .c_ident = { "CentaurHauls" }, .c_early_init = early_init_centaur, + .c_bsp_init = bsp_init_centaur, .c_init = init_centaur, #ifdef CONFIG_X86_32 .legacy_cache_size = centaur_size_cache, From patchwork Thu Feb 22 18:39:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205023 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp172696dyb; Thu, 22 Feb 2024 11:51:14 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWJbjUEA6Xy78cT0zBbUUm9D74RUbBlMMaml61aoV2D32bhy01Th68S/770VrLT+qErtU6Sxa1QN9l/26Jqmhvuy5i3+g== X-Google-Smtp-Source: AGHT+IH4tQgt+xG8+MCCdRtVYooVK4BcDjQ2bU4gAx3UUPAq5wIE4IS9VZLYu2sF/+3U3tALUs/D X-Received: by 2002:a05:6a20:c6ca:b0:19e:a1a2:60f6 with SMTP id gw10-20020a056a20c6ca00b0019ea1a260f6mr27491030pzb.57.1708631473761; Thu, 22 Feb 2024 11:51:13 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708631473; cv=pass; d=google.com; s=arc-20160816; b=A3aEb4LBGHWC/wVfFrsUVezVgAQQSogy+yIEr1ocJ/aippl+Ps33F0yRutLY1gR+0j 2ygCqnSVH+twIkLYu9ReFW5/SwYaWWTjR4T9oULrnF+6qs6QDba5BzfenoMOxMUiQUMb /1smyWv8znLzplpU/Cb1loONaUwxqLp+dil0ck4GLgRI7L892K8Xf4MVEIxS7gXY+xlW GzIeSFH5pv9cOsXk+0iHSIVyJ/M6neKTZgmUdFdhqs7CTZy7UftF6MXK4iE3pCLTt8KH qAh5imKV2x08D+Gq3ep8XfsXN34iXJ41Sr0JT6uDC1ohoot8Md4RUEE4fda0RjD/6FHY T+gA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=O8T88KUTsat+v60SwCJm+u5qeBncKT1mRDiD1St2Ld0=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=OPd8dx1eG+fq2p8+GszaOanwVmrXD79mdVLNUPmBTfyE0+d32h36Oh2xj8wIDBb+mE 9rcfwNNIWyFGEv95ksHSOHOs1UOJmIti3b3dHQd5XaDkG/d2cs/0tbg9lzQmHPiTBPV5 eyL17mHU/njGVj2j6k9J0K0lGe7SHI3BZEv/0KR0mBJ8gfg+ZMc/LqhICO8ATDdB+ylf DxMPVeHMEfEJq0Xsg1OSKxz+eJTTAwGWLhYQ+uSJcBk2djZpkYlShmsOg0cHxUNxgdPO 77BlpBBCenwQ8V2sZqZ+97o+HQIfF6FHntXczsmWkg70Y3zyBWDMXX2tJvtgYililf6D uzlQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=IVvH0HT5; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77173-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77173-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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But some weirdo CPUs like the Pentium 4 do some operations across two cachelines. Their CLFLUSH still works at 'x86_clflush_size' but they need some operations aligned to that double cacheline to work well, thus 'x86_cache_alignment'. Introduce and use a 'bsp_addr_config' field for these systems. Note that the Intel Family 15 code actually did this in two different sites, one for 32-bit and one for 64-bit. Unify them. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 7 +++++++ b/arch/x86/kernel/cpu/centaur.c | 2 +- b/arch/x86/kernel/cpu/common.c | 3 +++ b/arch/x86/kernel/cpu/intel.c | 10 ++++------ 4 files changed, 15 insertions(+), 7 deletions(-) diff -puN arch/x86/include/asm/processor.h~x86_cache_alignment_mult arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~x86_cache_alignment_mult 2024-02-22 10:08:57.732817356 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:08:57.740817669 -0800 @@ -172,6 +172,13 @@ struct x86_addr_config { * platforms that use memory encryption. */ u8 phys_addr_reduction_bits; + + /* + * "x86_clflush_size" is the size of an actual cacheline. + * Allow systems to specify a multiplier where alignment + * will take place at a more coarse granularity. + */ + u8 cache_align_mult; }; /* diff -puN arch/x86/kernel/cpu/centaur.c~x86_cache_alignment_mult arch/x86/kernel/cpu/centaur.c --- a/arch/x86/kernel/cpu/centaur.c~x86_cache_alignment_mult 2024-02-22 10:08:57.732817356 -0800 +++ b/arch/x86/kernel/cpu/centaur.c 2024-02-22 10:08:57.740817669 -0800 @@ -216,7 +216,7 @@ static void init_centaur(struct cpuinfo_ static void bsp_init_centaur(struct cpuinfo_x86 *c) { if (c->x86 == 0x6 && c->x86_model >= 0xf) - c->x86_cache_alignment = x86_clflush_size() * 2; + bsp_addr_config.cache_align_mult = 2; } #ifdef CONFIG_X86_32 diff -puN arch/x86/kernel/cpu/common.c~x86_cache_alignment_mult arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~x86_cache_alignment_mult 2024-02-22 10:08:57.736817513 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:08:57.740817669 -0800 @@ -1124,7 +1124,10 @@ void get_cpu_address_sizes(struct cpuinf } } c->x86_cache_bits = x86_config.phys_bits; + c->x86_cache_alignment = x86_clflush_size(); + if (bsp_addr_config.cache_align_mult) + c->x86_cache_alignment *= bsp_addr_config.cache_align_mult; /* Do this last to avoid affecting ->x86_cache_bits. */ x86_config.phys_bits -= bsp_addr_config.phys_addr_reduction_bits; diff -puN arch/x86/kernel/cpu/intel.c~x86_cache_alignment_mult arch/x86/kernel/cpu/intel.c --- a/arch/x86/kernel/cpu/intel.c~x86_cache_alignment_mult 2024-02-22 10:08:57.736817513 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2024-02-22 10:08:57.740817669 -0800 @@ -236,10 +236,6 @@ static void early_init_intel(struct cpui #ifdef CONFIG_X86_64 set_cpu_cap(c, X86_FEATURE_SYSENTER32); -#else - /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ - if (c->x86 == 15 && c->x86_cache_alignment == 64) - c->x86_cache_alignment = 128; #endif /* @@ -418,6 +414,10 @@ static void bsp_init_intel(struct cpuinf WARN_ON_ONCE(keyid_bits); bsp_addr_config.phys_addr_reduction_bits = 4; } + + /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ + if (c->x86 == 15) + bsp_addr_config.cache_align_mult = 2; } #ifdef CONFIG_X86_32 @@ -659,8 +659,6 @@ static void init_intel(struct cpuinfo_x8 set_cpu_bug(c, X86_BUG_MONITOR); #ifdef CONFIG_X86_64 - if (c->x86 == 15) - c->x86_cache_alignment = x86_clflush_size() * 2; if (c->x86 == 6) set_cpu_cap(c, X86_FEATURE_REP_GOOD); #else From patchwork Thu Feb 22 18:39:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205074 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp225100dyb; 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Remove them. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/common.c | 2 -- 1 file changed, 2 deletions(-) diff -puN arch/x86/kernel/cpu/common.c~dup-cache-alignment arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~dup-cache-alignment 2024-02-22 10:08:58.260838084 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:08:58.260838084 -0800 @@ -956,7 +956,6 @@ void cpu_detect(struct cpuinfo_x86 *c) if (cap0 & (1<<19)) { if (c == &boot_cpu_data) c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; - c->x86_cache_alignment = x86_clflush_size(); } } } @@ -1834,7 +1833,6 @@ static void identify_cpu(struct cpuinfo_ c->cpuid_level = -1; /* CPUID not detected */ c->x86_clflush_size = 32; #endif - c->x86_cache_alignment = x86_clflush_size(); memset(&c->x86_capability, 0, sizeof(c->x86_capability)); #ifdef CONFIG_X86_VMX_FEATURE_NAMES memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); From patchwork Thu Feb 22 18:39:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205014 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp168796dyb; Thu, 22 Feb 2024 11:42:26 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU1FZCL+Dp0SWQF9fl09VoofjAKPHxH04PVuUsJPyQtFxG31H7VcS/+4TbtWAiVEDBsjZEr82aC8FeNp/gk1ks5VN+PzQ== X-Google-Smtp-Source: AGHT+IH10UA9GYOviAkzPKiqRrr6HOLPf93kaZZkeVN2VUpg+wtjn5EZCb04N05I1vlNH9RWMZqi X-Received: by 2002:a17:906:f8ca:b0:a3e:ff8d:c6d9 with SMTP id lh10-20020a170906f8ca00b00a3eff8dc6d9mr5655654ejb.71.1708630945795; Thu, 22 Feb 2024 11:42:25 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708630945; cv=pass; d=google.com; s=arc-20160816; b=vU7unMquHPKiGae6gGPBj4g0axEEZXjU1q5Ju0k1pEUUitvtdeugDGK+rOWLirvYsq grO47gHDBovd4sgjaAq2uG6SsfKVIfbqwghnTfb3qq5AyaLUK8UFRZ4bCe4XAomcgvQ4 eDq4wavvxYbjkY5HasmpovMHIHgDNBFBJFNLkFvNt1x+vsRKNCMTytNsN+4Ii2LfCvrq NA7cZpYu63nnAvn0lQp9n5ZQTHrzQkQb6GUp8AL7v8kL6wvLHvykDeWa2AMsaqTHgpGb HwcZvsR7Pgo7Qqs6PjSNXShNBEvyO6YzSYVrziU3WRPxW/KdisZrPazxvwSVOPT2wEnu c3Xw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=V7Tt3E8FZI8GWpw2rG7tlfJSffk/MirrPljzDwtYrSs=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=Fi13bhyC4KhFm1ed+BLYqWOwOeLw/i+3oAqNLOBYNLrQWAqdvXWYo3fJuQAT8gOhNw 3kXHfZgWhhu2YmV4Vt8gW6qz6QngxBAjNDrhMu1ZEUTN6doxmY/yu6ZFWSHnCMVvQDz6 U1XXzhUo5JapJagJgQnYgHPnyRk7ieo35bTRy0a0IiJB0WGCAL8oTn2rdSWQMnoWTZ37 mdynH2bK4YsCsR7SZWZetiw/gNh/q3DeZ5q40LtkOI7HWo7EJeXE2krlUvjf4AHdUkhD vzdTpijPpplWmGlvA8KbwESzU9lfh5NZlOQvSwTUdlSan2jqZaWFUc6Ktb6QmWke5fZb ppyA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Oj0twNyG; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77175-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77175-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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To: linux-kernel@vger.kernel.org Cc: kirill.shutemov@linux.intel.com,pbonzini@redhat.com,tglx@linutronix.de,x86@kernel.org,bp@alien8.de,Dave Hansen From: Dave Hansen Date: Thu, 22 Feb 2024 10:39:54 -0800 References: <20240222183926.517AFCD2@davehans-spike.ostc.intel.com> In-Reply-To: <20240222183926.517AFCD2@davehans-spike.ostc.intel.com> Message-Id: <20240222183954.9A6E5428@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791629402451388577 X-GMAIL-MSGID: 1791629402451388577 From: Dave Hansen Right now, cpu_detect() establishes ->x86_clflush_size on each CPU that. supports CLFLUSH. As you might have guessed, that per-cpu value is no longer used. Move the setting to get_cpu_address_sizes() which is only called on the boot CPU. Consolidate all of the ->x86_clflush_size logic into a single helper. This removes the (cap0 & (1<<19) aka X86_FEATURE_CLFLUSH check before reading the CLFLUSH size out of CPUID[1]. Those bits are presumably either 0 or have actual data about CLFLUSH in them. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/common.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff -puN arch/x86/kernel/cpu/common.c~later-clflush_size-detect arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~later-clflush_size-detect 2024-02-22 10:08:58.728856457 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:08:58.732856614 -0800 @@ -935,6 +935,27 @@ static void get_cpu_vendor(struct cpuinf this_cpu = &default_cpu; } +static u16 detect_clflush_size(struct cpuinfo_x86 *c) +{ + u16 clflush_size = 0; + + if (c->cpuid_level >= 0x00000001) { + u32 eax, ebx, ecx, edx; + + cpuid(0x00000001, &eax, &ebx, &ecx, &edx); + + clflush_size = ((ebx >> 8) & 0xff) * 8; + } + + if (clflush_size) + return clflush_size; + + /* Return some mostly sane defaults: */ + if (IS_ENABLED(CONFIG_X86_64)) + return 64; + return 32; +} + void cpu_detect(struct cpuinfo_x86 *c) { /* Get vendor name */ @@ -952,11 +973,6 @@ void cpu_detect(struct cpuinfo_x86 *c) c->x86 = x86_family(tfms); c->x86_model = x86_model(tfms); c->x86_stepping = x86_stepping(tfms); - - if (cap0 & (1<<19)) { - if (c == &boot_cpu_data) - c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; - } } } @@ -1111,17 +1127,17 @@ void get_cpu_address_sizes(struct cpuinf if (IS_ENABLED(CONFIG_X86_64)) { x86_config.phys_bits = 36; x86_config.virt_bits = 48; - c->x86_clflush_size = 64; } else { x86_config.phys_bits = 32; x86_config.virt_bits = 32; - c->x86_clflush_size = 32; if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) x86_config.phys_bits = 36; } } + c->x86_clflush_size = detect_clflush_size(c); + c->x86_cache_bits = x86_config.phys_bits; c->x86_cache_alignment = x86_clflush_size(); @@ -1827,11 +1843,8 @@ static void identify_cpu(struct cpuinfo_ c->topo.cu_id = 0xff; c->topo.llc_id = BAD_APICID; c->topo.l2c_id = BAD_APICID; -#ifdef CONFIG_X86_64 - c->x86_clflush_size = 64; -#else +#ifndef CONFIG_X86_64 c->cpuid_level = -1; /* CPUID not detected */ - c->x86_clflush_size = 32; #endif memset(&c->x86_capability, 0, sizeof(c->x86_capability)); #ifdef CONFIG_X86_VMX_FEATURE_NAMES From patchwork Thu Feb 22 18:39:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205033 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp180649dyb; Thu, 22 Feb 2024 12:05:18 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVM1dtt3EDQ+rXuhIQSaTTlRZpEmBQ4yXhlQCHQG4mKqKJ8YgHXaI8oGML+OFuJao5XFM661qTtdpNCOEU4msf0SIdgdQ== X-Google-Smtp-Source: AGHT+IGrS2AbquYj+0/3B5N1gc4te0yvskjJ5kCE5GG1wrxgi+gJFw2/nKSnqVaJ14PR5XySF+C/ X-Received: by 2002:a05:620a:2b82:b0:787:6bfa:bdd with SMTP id dz2-20020a05620a2b8200b007876bfa0bddmr81159qkb.73.1708632318370; Thu, 22 Feb 2024 12:05:18 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708632318; cv=pass; d=google.com; s=arc-20160816; b=Kqcbb2PERtOpImzhFbE5/+JN4vbNT9X+/DX+Db2715zlraQqxEGhagizYe3PDElfIG rDmCVe2qnJkLtGHKM277wL9s4tBbqOGLCWnhwDMa3hmE9wR8szfrokbipl9H3Z6tFDbf bL56Ay51n2+z+yrtbLAveqKCFrDvX+6DeS77ELVHrztL6wvDEYqD6TTKfh8/oUsexUwI XuXfVfuof/k+GI9WfhUwP+OqzoM4LpNnzqg7VU0txBT29smDhnNCqIDbUElnAHgG4NP8 Kj84+osBdkM1lPXTclyEy/xIAKxVcUtQqJ7DaqWYfGgpdyH/57BiQt7S7k5nelqHfNdq 922Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=O6kdKw6GR9avh+q9fnChGnBk6Fh8HTG3b6aUiwotJ+E=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=C0oDXEkmuThxa7VxnhN7h70Aqw1wN8cUKVSKdHtLEoR9HwGeF+YTL7I7PvrvNvXRUl p5FOKN+s9Yo4JXO9SJ16cOiX5V6/EUZMfvHcniX22XVMwTX6F6DFQ/QZKVyJvtF5WVLW LC2+QqhVzUF+m2y8qC5/WvK+j43mqajGJA5FbAXi2+gfhjPCzKsHaKEpxIY22yHOIxVa PKyRg8wb9GsyIqdbx1QSt8/H5hmzEJI/S4K4Hz1y3FsAlYKJw/ACoVrZIq1Iu8GkYuJJ +rV/r6IrNdAzfKGU0VXjIqRnMsrRTsn+rDHBrIWEaItpBaXJFIzc+mnWK3xPAJlJxeQZ 7cYg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=KoBNdgtp; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77176-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77176-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Move it to 'x86_config'. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 4 ++-- b/arch/x86/kernel/cpu/common.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff -puN arch/x86/include/asm/processor.h~bsp-clflush_size arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~bsp-clflush_size 2024-02-22 10:08:59.208875301 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:08:59.212875458 -0800 @@ -148,7 +148,6 @@ struct cpuinfo_x86 { u64 ppin; /* cpuid returned max cores value: */ u16 x86_max_cores; - u16 x86_clflush_size; /* number of cores as seen by the OS: */ u16 booted_cores; /* Index into per_cpu list: */ @@ -191,6 +190,7 @@ struct x86_sys_config { /* Address bits supported by all processors */ u8 phys_bits; u8 virt_bits; + u16 clflush_size; }; extern struct x86_sys_config x86_config; @@ -812,7 +812,7 @@ static inline u8 x86_virt_bits(void) static inline u8 x86_clflush_size(void) { - return boot_cpu_data.x86_clflush_size; + return x86_config.clflush_size; } #endif /* _ASM_X86_PROCESSOR_H */ diff -puN arch/x86/kernel/cpu/common.c~bsp-clflush_size arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~bsp-clflush_size 2024-02-22 10:08:59.208875301 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:08:59.212875458 -0800 @@ -1136,7 +1136,7 @@ void get_cpu_address_sizes(struct cpuinf x86_config.phys_bits = 36; } } - c->x86_clflush_size = detect_clflush_size(c); + x86_config.clflush_size = detect_clflush_size(c); c->x86_cache_bits = x86_config.phys_bits; From patchwork Thu Feb 22 18:39:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205050 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp204287dyb; Thu, 22 Feb 2024 12:56:02 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVBrH71TCjhGXdoBk6P1HQqb4cWxAd2/uxq+O4bgsj0+D3/B16fqm9I8GqdIvFVOu/3Oy8TyaVsgJAxKwzEjsdR9zdMAA== X-Google-Smtp-Source: AGHT+IGqrqzT5bOvEAl9mYuAyfMuYCdXIyxBWmbAFOznbGNLzAonnU8GLrm/n83buoCHChTL9clg X-Received: by 2002:a05:6a20:9f08:b0:19f:c0d3:42c3 with SMTP id mk8-20020a056a209f0800b0019fc0d342c3mr216789pzb.4.1708635362429; Thu, 22 Feb 2024 12:56:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708635362; cv=pass; d=google.com; s=arc-20160816; b=c3XIjbHLaB8YJ1tMOpDBeZCpmt4q9d/ciWrWmZ9KYSLyiTeY5LTKv0iHzOvW5ZzdeS dwV2PBhKmwh67gtN65nIUMKBqP+isnmeUouSOBVXdYL15R2VTx4druVcKBWfKdL+SJBZ CYNgJghTmgTQpa26nNwVQz8Q1oZOvwds5i2lsJVfr6s2Y8OBjWrfIsY+i4nU9mbDqWRI tSDuNRsGBeE7Nl4sf4b1I9fzxKBg3/fnvjbh2514HCU01Dxa5PE/id6sqyaiPxWOUiaH r7sb/QgsSDZ7oHc+Md7cagQLy8V0ZF1uhzYBtyquJTn/vD8ZIB+7o4ssuZIOUniojzvf 0qRg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=WkbJckWx7dVwBSYO5vRi/0e9gWE97X7BvrxzTH/gCmk=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=j7RJOMTDmxon1AQnvI6bYaHrcY/IGwCFcsl5tLiwUym85kbcrNqUbP5Zb0oU40Pkp4 sFFLtpqHzjzcyx3TmpX5jh4zxV9Hba6zzNhBfgQ+CPK5o4f94ZKxjhTWW1NhDEIMaURY A11TTD07B5ojcGUr3tivnjasHgOp914R1e3sa5XPcNljQDbAkTIhIUe1+eTWg4cclOUx Gx7Z+3pBpFH1AhQFxz2ahbj9WPtLJTAXGlUP5tSVshIkyyun9lOAh5J24jJzCpLgBjHq h8d43XELpKAXxy1YfTtgnhX1zk3IsparGNC12TbAMjj62RVowTVI8dQjabrsWYwTXTdb ALHQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=eyjAmDxK; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77177-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77177-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Move it to the global configuration structure. The other values have received _new_ wrappers. But this one already had cache_line_size(). Just use that wrapper. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 4 ++-- b/arch/x86/kernel/cpu/common.c | 4 ++-- b/arch/x86/kernel/cpu/proc.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff -puN arch/x86/include/asm/processor.h~x86_config-x86_cache_alignment arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~x86_config-x86_cache_alignment 2024-02-22 10:08:59.700894617 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:08:59.708894931 -0800 @@ -137,7 +137,6 @@ struct cpuinfo_x86 { struct cpuinfo_topology topo; /* in KB - valid for CPUS which support this call: */ unsigned int x86_cache_size; - int x86_cache_alignment; /* In bytes */ /* Cache QoS architectural values, valid only on the BSP: */ int x86_cache_max_rmid; /* max index */ int x86_cache_occ_scale; /* scale to bytes */ @@ -191,6 +190,7 @@ struct x86_sys_config { u8 phys_bits; u8 virt_bits; u16 clflush_size; + int cache_alignment; /* in bytes */ }; extern struct x86_sys_config x86_config; @@ -229,7 +229,7 @@ DECLARE_PER_CPU_READ_MOSTLY(struct cpuin extern const struct seq_operations cpuinfo_op; -#define cache_line_size() (boot_cpu_data.x86_cache_alignment) +#define cache_line_size() (x86_config.cache_alignment) extern void cpu_detect(struct cpuinfo_x86 *c); diff -puN arch/x86/kernel/cpu/common.c~x86_config-x86_cache_alignment arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~x86_config-x86_cache_alignment 2024-02-22 10:08:59.704894774 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:08:59.708894931 -0800 @@ -1140,9 +1140,9 @@ void get_cpu_address_sizes(struct cpuinf c->x86_cache_bits = x86_config.phys_bits; - c->x86_cache_alignment = x86_clflush_size(); + x86_config.cache_alignment = x86_clflush_size(); if (bsp_addr_config.cache_align_mult) - c->x86_cache_alignment *= bsp_addr_config.cache_align_mult; + x86_config.cache_alignment *= bsp_addr_config.cache_align_mult; /* Do this last to avoid affecting ->x86_cache_bits. */ x86_config.phys_bits -= bsp_addr_config.phys_addr_reduction_bits; diff -puN arch/x86/kernel/cpu/proc.c~x86_config-x86_cache_alignment arch/x86/kernel/cpu/proc.c --- a/arch/x86/kernel/cpu/proc.c~x86_config-x86_cache_alignment 2024-02-22 10:08:59.704894774 -0800 +++ b/arch/x86/kernel/cpu/proc.c 2024-02-22 10:08:59.708894931 -0800 @@ -131,7 +131,7 @@ static int show_cpuinfo(struct seq_file seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize); #endif seq_printf(m, "clflush size\t: %u\n", x86_clflush_size()); - seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment); + seq_printf(m, "cache_alignment\t: %d\n", x86_config.cache_alignment); seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n", x86_phys_bits(), x86_virt_bits()); From patchwork Thu Feb 22 18:39:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205091 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp261246dyb; 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Code must establish their intent in 'x86_addr_config' and then later code will use that config information to establish the system-wide config. The L1TF wants to tweak x86_cache_bits. Let it do this, but move the code away from bugs.c so that ti can be easily called earlier en boot. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 6 +++++ b/arch/x86/kernel/cpu/bugs.c | 41 ------------------------------------- b/arch/x86/kernel/cpu/common.c | 2 + b/arch/x86/kernel/cpu/intel.c | 40 ++++++++++++++++++++++++++++++++++++ 4 files changed, 48 insertions(+), 41 deletions(-) diff -puN arch/x86/include/asm/processor.h~bsp-min_cache_bits arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~bsp-min_cache_bits 2024-02-22 10:09:00.220915031 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:09:00.224915188 -0800 @@ -177,6 +177,12 @@ struct x86_addr_config { * will take place at a more coarse granularity. */ u8 cache_align_mult; + + /* + * Specify a floor for the number of bits that the CPU + * caches comprehend. Used only for L1TF mitigation. + */ + u8 min_cache_bits; }; /* diff -puN arch/x86/kernel/cpu/bugs.c~bsp-min_cache_bits arch/x86/kernel/cpu/bugs.c --- a/arch/x86/kernel/cpu/bugs.c~bsp-min_cache_bits 2024-02-22 10:09:00.220915031 -0800 +++ b/arch/x86/kernel/cpu/bugs.c 2024-02-22 10:09:00.224915188 -0800 @@ -2237,45 +2237,6 @@ EXPORT_SYMBOL_GPL(l1tf_mitigation); enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); -/* - * These CPUs all support 44bits physical address space internally in the - * cache but CPUID can report a smaller number of physical address bits. - * - * The L1TF mitigation uses the top most address bit for the inversion of - * non present PTEs. When the installed memory reaches into the top most - * address bit due to memory holes, which has been observed on machines - * which report 36bits physical address bits and have 32G RAM installed, - * then the mitigation range check in l1tf_select_mitigation() triggers. - * This is a false positive because the mitigation is still possible due to - * the fact that the cache uses 44bit internally. Use the cache bits - * instead of the reported physical bits and adjust them on the affected - * machines to 44bit if the reported bits are less than 44. - */ -static void override_cache_bits(struct cpuinfo_x86 *c) -{ - if (c->x86 != 6) - return; - - switch (c->x86_model) { - case INTEL_FAM6_NEHALEM: - case INTEL_FAM6_WESTMERE: - case INTEL_FAM6_SANDYBRIDGE: - case INTEL_FAM6_IVYBRIDGE: - case INTEL_FAM6_HASWELL: - case INTEL_FAM6_HASWELL_L: - case INTEL_FAM6_HASWELL_G: - case INTEL_FAM6_BROADWELL: - case INTEL_FAM6_BROADWELL_G: - case INTEL_FAM6_SKYLAKE_L: - case INTEL_FAM6_SKYLAKE: - case INTEL_FAM6_KABYLAKE_L: - case INTEL_FAM6_KABYLAKE: - if (c->x86_cache_bits < 44) - c->x86_cache_bits = 44; - break; - } -} - static void __init l1tf_select_mitigation(void) { u64 half_pa; @@ -2288,8 +2249,6 @@ static void __init l1tf_select_mitigatio else if (cpu_mitigations_auto_nosmt()) l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; - override_cache_bits(&boot_cpu_data); - switch (l1tf_mitigation) { case L1TF_MITIGATION_OFF: case L1TF_MITIGATION_FLUSH_NOWARN: diff -puN arch/x86/kernel/cpu/common.c~bsp-min_cache_bits arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~bsp-min_cache_bits 2024-02-22 10:09:00.220915031 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:09:00.228915345 -0800 @@ -1139,6 +1139,8 @@ void get_cpu_address_sizes(struct cpuinf x86_config.clflush_size = detect_clflush_size(c); c->x86_cache_bits = x86_config.phys_bits; + if (c->x86_cache_bits < bsp_addr_config.min_cache_bits) + c->x86_cache_bits = bsp_addr_config.min_cache_bits; x86_config.cache_alignment = x86_clflush_size(); if (bsp_addr_config.cache_align_mult) diff -puN arch/x86/kernel/cpu/intel.c~bsp-min_cache_bits arch/x86/kernel/cpu/intel.c --- a/arch/x86/kernel/cpu/intel.c~bsp-min_cache_bits 2024-02-22 10:09:00.224915188 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2024-02-22 10:09:00.228915345 -0800 @@ -395,6 +395,44 @@ detect_keyid_bits: return keyid_bits; } +/* + * These CPUs all support 44bits physical address space internally in the + * cache but CPUID can report a smaller number of physical address bits. + * + * The L1TF mitigation uses the top most address bit for the inversion of + * non present PTEs. When the installed memory reaches into the top most + * address bit due to memory holes, which has been observed on machines + * which report 36bits physical address bits and have 32G RAM installed, + * then the mitigation range check in l1tf_select_mitigation() triggers. + * This is a false positive because the mitigation is still possible due to + * the fact that the cache uses 44bit internally. Use the cache bits + * instead of the reported physical bits and adjust them on the affected + * machines to 44bit if the reported bits are less than 44. + */ +static void set_min_cache_bits(struct cpuinfo_x86 *c) +{ + if (c->x86 != 6) + return; + + switch (c->x86_model) { + case INTEL_FAM6_NEHALEM: + case INTEL_FAM6_WESTMERE: + case INTEL_FAM6_SANDYBRIDGE: + case INTEL_FAM6_IVYBRIDGE: + case INTEL_FAM6_HASWELL: + case INTEL_FAM6_HASWELL_L: + case INTEL_FAM6_HASWELL_G: + case INTEL_FAM6_BROADWELL: + case INTEL_FAM6_BROADWELL_G: + case INTEL_FAM6_SKYLAKE_L: + case INTEL_FAM6_SKYLAKE: + case INTEL_FAM6_KABYLAKE_L: + case INTEL_FAM6_KABYLAKE: + bsp_addr_config.min_cache_bits = 44; + break; + } +} + static void bsp_init_intel(struct cpuinfo_x86 *c) { int keyid_bits = 0; @@ -418,6 +456,8 @@ static void bsp_init_intel(struct cpuinf /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ if (c->x86 == 15) bsp_addr_config.cache_align_mult = 2; + + set_min_cache_bits(c); } #ifdef CONFIG_X86_32 From patchwork Thu Feb 22 18:39:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205027 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp176567dyb; Thu, 22 Feb 2024 12:00:09 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVeZtEUUi4qhRwvdOcsUC3JmQQ6vIkSb8P80FB8M94rmuH9Iq1fylYaWmxLl5HmKdEjhnEDmSGrPMO0VFg5DlVqnCP7sA== X-Google-Smtp-Source: AGHT+IEIYs73vmMgTW9P1POz3YGOdFeTlo4Mfe18AzHAnt2cj/al6/sKYjayW4WYTrGVwJjWgB6X X-Received: by 2002:a05:6358:1093:b0:17b:6a36:912a with SMTP id j19-20020a056358109300b0017b6a36912amr5197316rwi.19.1708632008213; Thu, 22 Feb 2024 12:00:08 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708632008; cv=pass; d=google.com; s=arc-20160816; b=aJMN1BUG5pmvVUpqStlqTHMTA69mHAocRj965FwGOzzh3wjZNkXLIxyz2HZlEY2Up2 BasTMxwdjPb9+f0eCmW9BPgcYKcMiDaTSPcsd1ryFx+jcl/iyhga0V3N/e40GTz95rvc idDeccac/57PwoZi7p1a1pYYhwi/Es6h4hfLkyHvMls/KR4YkI375+/s50tlLq/rqV0r TJ49xm+HplTliXLBgMzYEBT6NRQIRRuA92rdCr9yj/jwWNqbAaec6uVtYlyhxbPAypg9 WBpLYB90FlTPhICQBYVFIAj4XTEa5Etq/dz1aRhts2zvx9evLbh/7k/2hDanE091EC3R Ywtw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=oNRStthIz3P7CT4cQ8MfQ7RCEn1FKb73BhiBDGhxTEU=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=HGWmhsf5iuzRQ+j7pjdojZAvzL829Qlacb1rkVz/w/45QC91HQQ4/HWSRmlMwqvhwf S9IA/utupQcRLr6luuU8GU1hnocZk/dK2fE3bl8YY66sl+oQpXpJ1nboRjWS9LZlNC7A ivmfg8y3sD3Rhw4L8YS5VlfDo+ZYAPQLeQNklFp/qN6RkxrXme9BJMMI7MxrMUjRe8hi Gf6OpIQbAxyaQwrOS5Z8XA0LUL5YiS6KK8vbVAXueMywtNT9SLv0UJAEBDbfrRr7s6b6 dvdRZDyiMhLNzCManeHNc2R2KeoR5LvZT6KjTHKrjnnsGR4ZC2qxJ0NPbqz4gYyMYmvB AqKA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=P+0laI0Z; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77179-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77179-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Move it from 'struct cpuinfo_x86' to 'x86_config' and give it a helper. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 10 +++++++--- b/arch/x86/kernel/cpu/common.c | 8 ++++---- b/arch/x86/kvm/mmu/spte.c | 6 +++--- 3 files changed, 14 insertions(+), 10 deletions(-) diff -puN arch/x86/include/asm/processor.h~config-cache_bits arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~config-cache_bits 2024-02-22 10:09:00.768936544 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:09:00.772936701 -0800 @@ -154,8 +154,6 @@ struct cpuinfo_x86 { /* Is SMT active on this core? */ bool smt_active; u32 microcode; - /* Address space bits used by the cache internally */ - u8 x86_cache_bits; unsigned initialized : 1; } __randomize_layout; @@ -195,6 +193,7 @@ struct x86_sys_config { /* Address bits supported by all processors */ u8 phys_bits; u8 virt_bits; + u8 cache_bits; u16 clflush_size; int cache_alignment; /* in bytes */ }; @@ -241,7 +240,7 @@ extern void cpu_detect(struct cpuinfo_x8 static inline unsigned long long l1tf_pfn_limit(void) { - return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); + return BIT_ULL(x86_config.cache_bits - 1 - PAGE_SHIFT); } extern void early_cpu_init(void); @@ -816,6 +815,11 @@ static inline u8 x86_virt_bits(void) return x86_config.virt_bits; } +static inline u8 x86_cache_bits(void) +{ + return x86_config.cache_bits; +} + static inline u8 x86_clflush_size(void) { return x86_config.clflush_size; diff -puN arch/x86/kernel/cpu/common.c~config-cache_bits arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~config-cache_bits 2024-02-22 10:09:00.768936544 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:09:00.772936701 -0800 @@ -1138,15 +1138,15 @@ void get_cpu_address_sizes(struct cpuinf } x86_config.clflush_size = detect_clflush_size(c); - c->x86_cache_bits = x86_config.phys_bits; - if (c->x86_cache_bits < bsp_addr_config.min_cache_bits) - c->x86_cache_bits = bsp_addr_config.min_cache_bits; + x86_config.cache_bits = x86_config.phys_bits; + if (x86_config.cache_bits < bsp_addr_config.min_cache_bits) + x86_config.cache_bits = bsp_addr_config.min_cache_bits; x86_config.cache_alignment = x86_clflush_size(); if (bsp_addr_config.cache_align_mult) x86_config.cache_alignment *= bsp_addr_config.cache_align_mult; - /* Do this last to avoid affecting ->x86_cache_bits. */ + /* Do this last to avoid affecting '.cache_bits'. */ x86_config.phys_bits -= bsp_addr_config.phys_addr_reduction_bits; } diff -puN arch/x86/kvm/mmu/spte.c~config-cache_bits arch/x86/kvm/mmu/spte.c --- a/arch/x86/kvm/mmu/spte.c~config-cache_bits 2024-02-22 10:09:00.772936701 -0800 +++ b/arch/x86/kvm/mmu/spte.c 2024-02-22 10:09:00.772936701 -0800 @@ -470,12 +470,12 @@ void kvm_mmu_reset_all_pte_masks(void) shadow_nonpresent_or_rsvd_mask = 0; low_phys_bits = x86_phys_bits(); if (boot_cpu_has_bug(X86_BUG_L1TF) && - !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >= + !WARN_ON_ONCE(x86_cache_bits() >= 52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) { - low_phys_bits = boot_cpu_data.x86_cache_bits + low_phys_bits = x86_cache_bits() - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; shadow_nonpresent_or_rsvd_mask = - rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1); 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There is no need to call get_cpu_address_sizes() again. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/common.c | 2 -- 1 file changed, 2 deletions(-) diff -puN arch/x86/kernel/cpu/common.c~zap-extra-get_cpu_address_sizes arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~zap-extra-get_cpu_address_sizes 2024-02-22 10:09:01.292957116 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:09:01.296957273 -0800 @@ -1770,8 +1770,6 @@ static void generic_identify(struct cpui get_cpu_cap(c); - get_cpu_address_sizes(c); - if (c->cpuid_level >= 0x00000001) { c->topo.initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; #ifdef CONFIG_X86_32 From patchwork Thu Feb 22 18:40:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 204998 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp140825dyb; Thu, 22 Feb 2024 10:49:59 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVFTh1vDM2CQD1khVfpvjy4Mxjs9sC/15TejNra2a0XLgwI0QbBjQO97Dfd8hlDvH2s+xZO7a2lr6PbGQZD/44IhFwBog== X-Google-Smtp-Source: AGHT+IE8psUT5guuoCHErdGciVPjazuXyDUbmi+WDojfSHEds1QVLe8RW6kYCnunJy1zuws0PXZA X-Received: by 2002:a05:620a:810:b0:787:28cb:5ab8 with SMTP id s16-20020a05620a081000b0078728cb5ab8mr22898802qks.41.1708627799375; Thu, 22 Feb 2024 10:49:59 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708627799; cv=pass; d=google.com; s=arc-20160816; b=zDCpbHaNT5TtORPYUz03Cu6WSu8uTyqpjP2Y1NIBfs/WMQoFKeU7pKP/YdH9qpbKAo ikBrgkfZ/jOZSOvgvWR0dFsLa/ULtHS0l7lsPSPC8XBf0GvD3BNkpeGUop36VHtHPHrb i6jrEc2SK89JQrFFNtcRiYmDwiBJpevvA1ZrogsIsLVY1dAo2eZLcTxDb8orUwS7wkFA Y22cg8G5upXuNJj+Hfe0n6FguZx/Mc1n+9vcfWXVtgAzLQSNJQazYb6Js1R3fixcmyK1 MHjDcWXQ3uGQ3/0Y5QPKU+IQbjkZyazc3DPsiJng5L5wzjB7SbcMHbxZDbhk5b8SKnqT efig== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=4XujMKl2J9PFheAQoH/cxpotEIXJtUUEjpwUzMemFuo=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=BtZKLB1rhw8x16Youyg3lba16VKIldXSn4nRjzHAwPJN+F1liWaKIyAtJp2Pr1HqBb Z03oiw8z/zUlAJHMy3tprelIBvBz/PRpgMA5gSyOfrVaJuW6lmIVnpwrJfm5SrUoyYiI SapB6jUM+GnDD6uIN0DpfarqElyggNmhZ9VDSvC215AKrjOmYK2zM7fQo9UKxxqGgS3m D+eWruAym7bD4H15O2WeHoxogugp6m4i3PYJ6qnaHQcq57JYbpXahcHPe/v7qlpZfA2K KszO/ngXkPJlGaU9rbzBTVFZILxxN7G9kGTSIskapsu1G4icG3wYztomT2wL1gbb9Zkc HoOg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nYTRWxUA; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77181-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77181-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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It was (and is) just a free-for-all. Establish that 'x86_config' has two phases of its lifetime: an C_INITIALIZING phase where it can be written and a later C_FINALIZED stage where it can only be read. It is simple to audit the fact that this state transition happens just where the comment says it should be. Check that the config is C_FINALIZED in each of the wrappers that read a 'x86_config' value. If something reads too early, stash some information to the caller so that it can spit out a warning later. This goofy stash-then-warn construct is necessary here because any hapless readers are likely to be in a spot where they can not easily WARN() themselves, like the early Xen PV boot that's caused so many problems. This also moves one x86_clflush_size() reference over to the more direct x86_config.cache_alignment because otherwise it would trip the !C_FINALIZED check. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 22 ++++++++++++++++++++++ b/arch/x86/kernel/cpu/common.c | 5 ++++- b/arch/x86/kernel/setup.c | 7 +++++++ 3 files changed, 33 insertions(+), 1 deletion(-) diff -puN arch/x86/include/asm/processor.h~x86_config-finalize arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~x86_config-finalize 2024-02-22 10:09:01.772975960 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:09:01.780976274 -0800 @@ -183,6 +183,11 @@ struct x86_addr_config { u8 min_cache_bits; }; +enum x86_sys_config_state { + C_INITIALIZING, + C_FINALIZED +}; + /* * System-wide configuration that is shared by all processors. * @@ -190,6 +195,9 @@ struct x86_addr_config { * modified after that. */ struct x86_sys_config { + enum x86_sys_config_state conf_state; + void *early_reader; + /* Address bits supported by all processors */ u8 phys_bits; u8 virt_bits; @@ -805,23 +813,37 @@ static inline void weak_wrmsr_fence(void alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); } +static inline void read_x86_config(void) +{ + if (x86_config.conf_state == C_FINALIZED) + return; + + /* Only record the first one: */ + if (!x86_config.early_reader) + x86_config.early_reader = __builtin_return_address(0); +} + static inline u8 x86_phys_bits(void) { + read_x86_config(); return x86_config.phys_bits; } static inline u8 x86_virt_bits(void) { + read_x86_config(); return x86_config.virt_bits; } static inline u8 x86_cache_bits(void) { + read_x86_config(); return x86_config.cache_bits; } static inline u8 x86_clflush_size(void) { + read_x86_config(); return x86_config.clflush_size; } diff -puN arch/x86/kernel/cpu/common.c~x86_config-finalize arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~x86_config-finalize 2024-02-22 10:09:01.776976117 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:09:01.780976274 -0800 @@ -1114,6 +1114,9 @@ void get_cpu_address_sizes(struct cpuinf u32 eax, ebx, ecx, edx; bool vp_bits_from_cpuid = true; + WARN_ON_ONCE(x86_config.conf_state > C_INITIALIZING); + x86_config.conf_state = C_INITIALIZING; + if (!cpu_has(c, X86_FEATURE_CPUID) || (c->extended_cpuid_level < 0x80000008)) vp_bits_from_cpuid = false; @@ -1142,7 +1145,7 @@ void get_cpu_address_sizes(struct cpuinf if (x86_config.cache_bits < bsp_addr_config.min_cache_bits) x86_config.cache_bits = bsp_addr_config.min_cache_bits; - x86_config.cache_alignment = x86_clflush_size(); + x86_config.cache_alignment = x86_config.clflush_size; if (bsp_addr_config.cache_align_mult) x86_config.cache_alignment *= bsp_addr_config.cache_align_mult; diff -puN arch/x86/kernel/setup.c~x86_config-finalize arch/x86/kernel/setup.c --- a/arch/x86/kernel/setup.c~x86_config-finalize 2024-02-22 10:09:01.776976117 -0800 +++ b/arch/x86/kernel/setup.c 2024-02-22 10:09:01.780976274 -0800 @@ -762,7 +762,14 @@ void __init setup_arch(char **cmdline_p) olpc_ofw_detect(); idt_setup_early_traps(); + early_cpu_init(); + + /* Ensure no readers snuck in before the config was finished: */ + WARN_ONCE(x86_config.early_reader, "x86_config.early_reader: %pS\n", + x86_config.early_reader); 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Those values often cause the user to crash before they can get a nice message out to the console. Provide some mostly random but unlikely-to-crash-the-caller values. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff -puN arch/x86/include/asm/processor.h~x86_config-defaults arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~x86_config-defaults 2024-02-22 10:09:02.280995903 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:09:02.280995903 -0800 @@ -813,37 +813,57 @@ static inline void weak_wrmsr_fence(void alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); } -static inline void read_x86_config(void) +static inline int read_x86_config(void) { if (x86_config.conf_state == C_FINALIZED) - return; + return 0; /* Only record the first one: */ if (!x86_config.early_reader) x86_config.early_reader = __builtin_return_address(0); + + return -EINVAL; } +/* + * These _should_ not be called until x86_config is C_FINALIZED. + * In the case that they are, two things will happen: + * 1. The first caller will get the call site recorded in + * 'early_reader' which will trigger a warning later in + * boot. + * 2. A moderately sane hard-coded default value will be provided. + * The entire intent of this value is to let things limp along + * until the warning can spit out. + */ static inline u8 x86_phys_bits(void) { - read_x86_config(); + if (read_x86_config()) + return 52; + return x86_config.phys_bits; } static inline u8 x86_virt_bits(void) { - read_x86_config(); + if (read_x86_config()) + return IS_ENABLED(CONFIG_X86_64) ? 57 : 32; + return x86_config.virt_bits; } static inline u8 x86_cache_bits(void) { - read_x86_config(); + if (read_x86_config()) + return 52; + return x86_config.cache_bits; } static inline u8 x86_clflush_size(void) { - read_x86_config(); + if (read_x86_config()) + return 64; + return x86_config.clflush_size; } From patchwork Thu Feb 22 18:40:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205018 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp169356dyb; Thu, 22 Feb 2024 11:43:46 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVx9sI9j5+X4kcTuPiI2DsRMIhdONUc85dAmCNrYljN7Ux11y+QbkePfeLyIroGTfnUI6zi09YgByukTWOahNkR//BWEQ== X-Google-Smtp-Source: AGHT+IF102WC8l6Bj8vC7GQaL/0ErKBGZIDD0514fmYuDYH4iFYZJrC1ZWmW/lttUcKDzt9v39Rx X-Received: by 2002:a17:902:7847:b0:1db:5213:222 with SMTP id e7-20020a170902784700b001db52130222mr16877423pln.5.1708631025788; Thu, 22 Feb 2024 11:43:45 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708631025; cv=pass; d=google.com; s=arc-20160816; b=h/jOoXyX5XTEpPc8vsaNqmt/vKK7GHyeiLMc/jZiai9cjyD6UyrSIFKaHPE6FHR3t6 Xstsad/yuk9WecJA4QFvfSgwZr7Ha+OhmZtx4xNrHGcLxhO/TRFfkeRYTuZiVrN3kHR9 SwbjURbrWn9ZjeuFa+fTQdkzBnep9SLEGFGMzA42kQtKbE6MbP2ZS09DxBufOn/z8ypH 1ygDndR0BT6hTtyquO/mgZ1jK1kc2UsfIiY0fBYUNj9S0EJIkAeNwU2S83oTBQmSdk/v Z2UVpg7u9ibrQhUCAumoX6sY3HYxlX7Cp48+SF+yCeva2Jcz/+sfuHzGix3p6SlpScyr Y0wg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=LgQ0NG89NcwonskSzs9LFmvvjI0Tt3qTAeOmvlqdMSQ=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=XtRXuwfw9k3giX1adQ/RSiM42vCTGAb8krDJrwIZFAXTftLFXOIrUUYhQ+BUxVAoJ3 Zr6iwTkc+U/WO3dPl0mLukq8A7DwDBjh7IiQ4htkdI+4Ssd2OyCx3lfITpYORdSC0lP7 MyvmiuPqx+MZ2unD0CYwr1+dE2m6rr2H9kHZh4TkJ5OKGvZGtZNe1OEBWytY2ngXL3Po mBYHrxsLgferkPDIjpsHDeWF1hRKK7S5kwe0LqUaYL04Sv3EcH86W1i5V0Z5+Pj4NGPn 9SSoXFQ+ZcUb62XVSbpRKwbfwbqcEM06kL4sTVN/c1zoDhmCfQEOiNI7M8rLj5me7Eix Z89g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=mQHvS9Xa; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77182-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77182-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Even if something was missed, it should now get sane values *and* be able to survive long enough to get a warning out later in boot. Remove the belt-and-suspenders call to get_cpu_address_sizes(). Signed-off-by: Dave Hansen --- b/arch/x86/xen/enlighten_pv.c | 3 --- 1 file changed, 3 deletions(-) diff -puN arch/x86/xen/enlighten_pv.c~xen-remove-early-addr_size-fun arch/x86/xen/enlighten_pv.c --- a/arch/x86/xen/enlighten_pv.c~xen-remove-early-addr_size-fun 2024-02-22 10:09:02.753014433 -0800 +++ b/arch/x86/xen/enlighten_pv.c 2024-02-22 10:09:02.757014590 -0800 @@ -1386,9 +1386,6 @@ asmlinkage __visible void __init xen_sta */ xen_setup_gdt(0); - /* Determine virtual and physical address sizes */ - get_cpu_address_sizes(&boot_cpu_data); - /* Let's presume PV guests always boot on vCPU with id 0. */ per_cpu(xen_vcpu_id, 0) = 0; From patchwork Thu Feb 22 18:40:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205146 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp283976dyb; Thu, 22 Feb 2024 15:40:17 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUPnvkqa5dX6kJ7J14czEN/JoBfnYVlFe0gSw711QU6CJYi+DThRyQw5UdNJThNXp/8thHYyuTkuL5yRVFewibPd4Ck9w== X-Google-Smtp-Source: AGHT+IGnrJn+qU8+Yy+vgxSilW2eEHAW+eh09x7pJlPLFC+JbDdRoVezAA8vOYfvUGgFHNmn4m/0 X-Received: by 2002:a17:90a:d718:b0:299:3c18:9c71 with SMTP id y24-20020a17090ad71800b002993c189c71mr263802pju.37.1708645217153; Thu, 22 Feb 2024 15:40:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708645217; cv=pass; d=google.com; s=arc-20160816; b=mk0Tm5foMfN++wTnlBn7VF8l57JCjRf2mfSz75FLvhmp3c1p7LG4DfVs/GAS6bY1QQ sIDTHJg9gQGl4a3izHzY6+XdVQ+LQkEZQu17giu9LOkh4jVq0khFi5bkjudWTUhuxwGe 9YzIC4L/uswFEEPslRdP/j6CtFiWh0cS1WXPnpQ18yCPuH7ZpiZJCvREIHsMpzAnts5Z wxgR/IpLO3EbeLowyClAQW8QI13fjnD1O5GgTe2NNMzUaD1JcKKhoVH9jh2bplwrPxlf 3mB0YHSLfmwmbZAXlC4ruWkPAvQgaQEBSFuGkcK2FDjHmHVvKyDWVoXXE71Dqto52S7L mfJA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=LzgwEmA/MvRRFEKxFpbrCCTAutaYImNnaql+dAei5tY=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=QOpY89EhaaGeELcBCCSczoG7v4LujKgAyWuQHcMJVLgEKsr2Tm/JOz2XPL7WyZEy7O WZzVmNoYwyYgPlYa0LlHzUHOmJoVTwmLXXJGsmp3wqZTV59dLJLBVZe0XxgnZhQocGAo XbOqXE3uBDrrLCt5fPKZJ58+nONSGEoYDE4LoDb/Xzs748YaKG1Q2aZv2Dt2HQFc7SsO cyA6WIJQgYymySeNwztyYEl+FX5vcv9A8lGnWlZC6HirL4+brdvYg+hP0va//Cwxgw6B tC+OADLo9BG78amo0gqHmjQhwxJP/Nid+QWNyjdh/bNjV0TNNSnJ55yr4UcSmJpNRVOd 4bhw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Y02G1hto; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77184-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77184-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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This prevents a warning once 'bsp_addr_config' gets marked __init. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/centaur.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff -puN arch/x86/kernel/cpu/centaur.c~bsp_init_centaur-__init arch/x86/kernel/cpu/centaur.c --- a/arch/x86/kernel/cpu/centaur.c~bsp_init_centaur-__init 2024-02-22 10:09:03.237033434 -0800 +++ b/arch/x86/kernel/cpu/centaur.c 2024-02-22 10:09:03.237033434 -0800 @@ -213,7 +213,7 @@ static void init_centaur(struct cpuinfo_ init_ia32_feat_ctl(c); } -static void bsp_init_centaur(struct cpuinfo_x86 *c) +static void __init bsp_init_centaur(struct cpuinfo_x86 *c) { if (c->x86 == 0x6 && c->x86_model >= 0xf) bsp_addr_config.cache_align_mult = 2; From patchwork Thu Feb 22 18:40:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205088 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp253312dyb; Thu, 22 Feb 2024 14:27:52 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWplYtKAujj224abz7seUSuzkAlKEf23Bmj6fo2d63jwBLjYwHENPAm8hXz69HIwjY8jHlyGicjVzN8IWiK2P7hj1EJMA== X-Google-Smtp-Source: AGHT+IHK9j+/xT/lcQnt/h1O3pJuoEHzLM/3ecnO/QrMmjE9qCDlu1/YeYu4QL9J4x9Z1Jws8j3N X-Received: by 2002:a05:6a20:960a:b0:1a0:ccf2:8f44 with SMTP id jl10-20020a056a20960a00b001a0ccf28f44mr174393pzb.21.1708640872029; Thu, 22 Feb 2024 14:27:52 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708640872; cv=pass; d=google.com; s=arc-20160816; b=yaJGfkyIZ3CqijmrW+mYrQTUpbqgrMvDCnxL4/Ris4vc840JcxJx2oHEy51aIUsrTh GBiR+rv/UIksux0AgeU9NnDor9AmKTixEomurMSkvnAe7Zr6uParH0ezEXChdePuzDcu D4tAoAUL0pzDTJwn9Bw8zTzQnO9siazroEtUMJK3kAl4UsGRcblbIxwQpB2B6DiyEV0Q sSehXfbQph1DQmceOI8Q2gpUhUvL04Ytv+E6qg5TCApG00DzoqIxpytTK/FRE0sWBglu cV/FCHm575krtVtCw7nh+5zVMEvlhLb2pHZ15g8/DJ49xnbhlWo5mTGH9syUs56xA3vo I6PQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=+IHAIWTqNs06mBN4o+YaG/GOzqsAPGk99vROAkcViQA=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=DpvALq0qHe/Cv9tgtxW5vONsap+umCiPiPWtIdcFrrrdt8S4362J7KlmknIgWx/plw Hb2wk7DoJWAqejgt+XLjjg9r0/wNv0wmmKdBa/tkKn8ehhZQPzfraoKwrqUciwS8rRv+ QohShAGjvHdxaQDnN4pQwIlIug5VqVnYdxGvaHNTfTaTcjQXBu6x7c+ABvhOAfwuwiAp 7KRkrMlzDKhjVpgWOvjbefJetI+mM7JhpAy7IzzSxZrRsAQquTM/WSsrgZCPIGxXvt11 EWpDGtwGQaImV7A3uY9PrjaZKbveXYzsLWOWmJEUNV3OJIb9P9eeny4/6j2MIuSRvgrz KzpQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=HfjcCjsp; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77185-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77185-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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This prevents a warning once 'bsp_addr_config' gets marked __init. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff -puN arch/x86/kernel/cpu/intel.c~bsp_init_intel-__init arch/x86/kernel/cpu/intel.c --- a/arch/x86/kernel/cpu/intel.c~bsp_init_intel-__init 2024-02-22 10:09:03.721052435 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2024-02-22 10:09:03.725052592 -0800 @@ -433,7 +433,7 @@ static void set_min_cache_bits(struct cp } } -static void bsp_init_intel(struct cpuinfo_x86 *c) +static void __init bsp_init_intel(struct cpuinfo_x86 *c) { int keyid_bits = 0; From patchwork Thu Feb 22 18:40:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205057 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp210852dyb; Thu, 22 Feb 2024 13:08:16 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXgmTz3ZT602KLlcGHX2EifyBScNW1LIJzF9cbYQgL32hpqY7GMhiHpsxQe9iuYpWr5AqVP7NrS34XNofO2n4+JStFuYQ== X-Google-Smtp-Source: AGHT+IFiy6qToZNjvTXTehc9YbnhUJlLkDxr5TRu7YkXhWwC31ML6fFogFNpvDqcZnxbIOzHo5cT X-Received: by 2002:a17:90a:10d0:b0:299:bade:ed0b with SMTP id b16-20020a17090a10d000b00299badeed0bmr10085234pje.45.1708636095829; Thu, 22 Feb 2024 13:08:15 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708636095; cv=pass; d=google.com; s=arc-20160816; b=lXFtG1VGWUD3y+QDYMuZwndMu9oBJ6KiTr8LfUINloUkCI+ubxEDc7Jva1lJIJQSI/ CGvHIrz/fw3tHz9OwbjljkLG2O7+LbypPpVY+Ha4bloWc6tBSNJSTrctY0zJ2JpLeVRz ZLZiS+cT4ITc0ZvEq5V6LOeIkM1BWUvSAQb17WlEjDhglshaCEGn6TvE+gVnG6tpSMRS hFZw6SobxdXz8WqLZ5QT9+f3dLri9WhLdnkcOiyQvGPWzWrNoCfL/Oj7Y7IUM6YWYaw5 kzpo4+tFJQDuvXv+nhlntN14dIgFapVy2uZsVNEiWZyDL4oW/7uJ0z3DBN9VaSiSVsne AWzA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=RiOMwzDVB5XueSOQcopQilsy6LvuTvv5pucUR0w6WHU=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=s7YF5yFvuKVAVF4rvZoSCZCNcizbcOwilX8H3wyxD9vstwsqH95MX0C9wABZRBxpTx NLKLg941XWDGmOnasZQS3jFUccSAPixTqC4dsjRZtIIfCBMhKfCV9txuq5zLYw+ra67G jDVL58ie3RVZAaSGoEmQ7gQY2Aa2sLJldGSSug0OMYFHAd0B99xjeG/DDlSIvuW7AXIb /XZPO3Zijd31XTfodEgil11paDaKqrfE/VfbexKI/dnEQ9zNvCgplnPekb7UF2D5zuKf 7J/SQ+PaDO5o5+93sSD1pxo/lUf1qw9wAoyscyPfs7+1/sdFp8hvfhXs86qwVeysDetT cMqg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=AaisjB1w; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77186-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77186-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Move it to bsp_init_amd() where it belongs and change its name to match. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/amd.c | 110 ++++++++++++++++++++++---------------------- 1 file changed, 55 insertions(+), 55 deletions(-) diff -puN arch/x86/kernel/cpu/amd.c~early_init_amd-__init arch/x86/kernel/cpu/amd.c --- a/arch/x86/kernel/cpu/amd.c~early_init_amd-__init 2024-02-22 10:09:04.201071279 -0800 +++ b/arch/x86/kernel/cpu/amd.c 2024-02-22 10:09:04.201071279 -0800 @@ -468,8 +468,62 @@ static void early_init_amd_mc(struct cpu #endif } -static void bsp_init_amd(struct cpuinfo_x86 *c) +static void bsp_detect_mem_encrypt(struct cpuinfo_x86 *c) { + u64 msr; + + /* + * BIOS support is required for SME and SEV. + * For SME: If BIOS has enabled SME then adjust x86_phys_bits by + * the SME physical address space reduction value. + * If BIOS has not enabled SME then don't advertise the + * SME feature (set in scattered.c). + * If the kernel has not enabled SME via any means then + * don't advertise the SME feature. + * For SEV: If BIOS has not enabled SEV then don't advertise the + * SEV and SEV_ES feature (set in scattered.c). + * + * In all cases, since support for SME and SEV requires long mode, + * don't advertise the feature under CONFIG_X86_32. + */ + if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { + /* Check if memory encryption is enabled */ + rdmsrl(MSR_AMD64_SYSCFG, msr); + if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) + goto clear_all; + + /* + * Always adjust physical address bits. Even though this + * will be a value above 32-bits this is still done for + * CONFIG_X86_32 so that accurate values are reported. + */ + bsp_addr_config.phys_addr_reduction_bits = + (cpuid_ebx(0x8000001f) >> 6) & 0x3f; + + if (IS_ENABLED(CONFIG_X86_32)) + goto clear_all; + + if (!sme_me_mask) + setup_clear_cpu_cap(X86_FEATURE_SME); + + rdmsrl(MSR_K7_HWCR, msr); + if (!(msr & MSR_K7_HWCR_SMMLOCK)) + goto clear_sev; + + return; + +clear_all: + setup_clear_cpu_cap(X86_FEATURE_SME); +clear_sev: + setup_clear_cpu_cap(X86_FEATURE_SEV); + setup_clear_cpu_cap(X86_FEATURE_SEV_ES); + } +} + +static void __init bsp_init_amd(struct cpuinfo_x86 *c) +{ + bsp_detect_mem_encrypt(c); + if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { if (c->x86 > 0x10 || @@ -593,58 +647,6 @@ warn: WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model); } -static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) -{ - u64 msr; - - /* - * BIOS support is required for SME and SEV. - * For SME: If BIOS has enabled SME then adjust x86_phys_bits by - * the SME physical address space reduction value. - * If BIOS has not enabled SME then don't advertise the - * SME feature (set in scattered.c). - * If the kernel has not enabled SME via any means then - * don't advertise the SME feature. - * For SEV: If BIOS has not enabled SEV then don't advertise the - * SEV and SEV_ES feature (set in scattered.c). - * - * In all cases, since support for SME and SEV requires long mode, - * don't advertise the feature under CONFIG_X86_32. - */ - if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { - /* Check if memory encryption is enabled */ - rdmsrl(MSR_AMD64_SYSCFG, msr); - if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) - goto clear_all; - - /* - * Always adjust physical address bits. Even though this - * will be a value above 32-bits this is still done for - * CONFIG_X86_32 so that accurate values are reported. - */ - bsp_addr_config.phys_addr_reduction_bits = - (cpuid_ebx(0x8000001f) >> 6) & 0x3f; - - if (IS_ENABLED(CONFIG_X86_32)) - goto clear_all; - - if (!sme_me_mask) - setup_clear_cpu_cap(X86_FEATURE_SME); - - rdmsrl(MSR_K7_HWCR, msr); - if (!(msr & MSR_K7_HWCR_SMMLOCK)) - goto clear_sev; - - return; - -clear_all: - setup_clear_cpu_cap(X86_FEATURE_SME); -clear_sev: - setup_clear_cpu_cap(X86_FEATURE_SEV); - setup_clear_cpu_cap(X86_FEATURE_SEV_ES); - } -} - static void early_init_amd(struct cpuinfo_x86 *c) { u64 value; @@ -715,8 +717,6 @@ static void early_init_amd(struct cpuinf if (c->x86 == 0x16 && c->x86_model <= 0xf) msr_set_bit(MSR_AMD64_LS_CFG, 15); - early_detect_mem_encrypt(c); - /* Re-enable TopologyExtensions if switched off by BIOS */ if (c->x86 == 0x15 && (c->x86_model >= 0x10 && c->x86_model <= 0x6f) && From patchwork Thu Feb 22 18:40:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205092 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp261608dyb; Thu, 22 Feb 2024 14:46:36 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUm3hVMiWAegUO2pDIQAk3UPxHFuMlT3UvXAK5UlXeZ50+1heJGRsmS4sF837BlkxrZPITMq+HLPRAndgyd/e7OFQpE1w== X-Google-Smtp-Source: AGHT+IGdBjSC5z6wc5DRND2dhioxJTA6ciiLXQ5oNI4i2gN1EOv4yIHQjygwMauuMKv4SeVkyHAR X-Received: by 2002:a05:6402:1ca7:b0:565:6bbc:3839 with SMTP id cz7-20020a0564021ca700b005656bbc3839mr45798edb.40.1708641996387; Thu, 22 Feb 2024 14:46:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708641996; cv=pass; d=google.com; s=arc-20160816; b=azwiOp1k6Pi/7ra5XutOX9dD4dcbwn+qV5MnwLjeblmjHMRuBaTl0rO1+CO70YeP9e jl8FWoATYYJkErl1uqa64UR3mdzTXHvh6psvxEQE3I6iYWhDYkrKnE/2l2uuZsNWOt84 bFE35plC8CDKEivwgjphTHUHxkJHGE0mbRjB8mC5DYOFhMLTpKpiilm07OAZ6+vAjQbZ RvjVR6EUbf2CPfE/7CTioYQWZRY8FcsJDznYjGbzNWLVQuHloi+mQPrZ69qZqkozF90P h3+1mn+jTBfnowxDlBeMH88/xU0l6VzXn3SsXLDRio4Vkhv+ci9vQxKjjZ01YQaMk/xV 6vyw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=Rq9q6dwn2/VV36tj2I68jekJsPoOwuAeDxs6zIp+KGQ=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=GTNmB9tszHvQ+PMW8mcZ2m+OtTQ+8xfTcWPXwPnfipJd44DetoXIYsbK531Qxb9lT/ a7PMsZ6KXqyYiYzlt68pgO15Kafz26dTXrCh7P9J2Yr5WweVsNhiaKr0bXexIiDvw0TA xsh5R9CfDQsMfWlL7mH8L026YkrBEAVpde2UWOeoHMN+A/ebZv3BCw9rotSjvX24cwk5 Wnj2hKfHc8f26fwq6yBNHvq5xRPxxV+qb+H39ypsHoNLR2i8jo76qwQCyQ3RlVnjs3WS c4Rk1HdslUmg6Ihl2GyCCbtXNs5xN6iDZTInd7qaZmMIWmEzFVsrsQ8OTKXi5tn9XfK7 gQuQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XMmQWUkS; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77187-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77187-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/common.c | 2 +- b/arch/x86/kernel/cpu/cpu.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff -puN arch/x86/kernel/cpu/common.c~get_cpu_address_sizes-__init arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~get_cpu_address_sizes-__init 2024-02-22 10:09:04.677089966 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:09:04.681090123 -0800 @@ -1109,7 +1109,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) apply_forced_caps(c); } -void get_cpu_address_sizes(struct cpuinfo_x86 *c) +static void __init get_cpu_address_sizes(struct cpuinfo_x86 *c) { u32 eax, ebx, ecx, edx; bool vp_bits_from_cpuid = true; diff -puN arch/x86/kernel/cpu/cpu.h~get_cpu_address_sizes-__init arch/x86/kernel/cpu/cpu.h --- a/arch/x86/kernel/cpu/cpu.h~get_cpu_address_sizes-__init 2024-02-22 10:09:04.677089966 -0800 +++ b/arch/x86/kernel/cpu/cpu.h 2024-02-22 10:09:04.681090123 -0800 @@ -64,7 +64,6 @@ static inline void tsx_ap_init(void) { } extern void init_spectral_chicken(struct cpuinfo_x86 *c); extern void get_cpu_cap(struct cpuinfo_x86 *c); -extern void get_cpu_address_sizes(struct cpuinfo_x86 *c); extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c); extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); extern void init_intel_cacheinfo(struct cpuinfo_x86 *c); From patchwork Thu Feb 22 18:40:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Hansen X-Patchwork-Id: 205011 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp167969dyb; Thu, 22 Feb 2024 11:40:39 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU4Rv7TflS62ec4ORLQ4Un3JdvvI+E98wSzGOncW4xj25VLPeVBz+tTbRez9Oy/dWAHI8JZQVNfoD9prZNPvoVNKryjHQ== X-Google-Smtp-Source: AGHT+IGIYve8Io+XHpp0wlbaSTlVCiOGjAKekXzL9rpZ2cQusyqy+FVa1ndh/0Lfg2zY5YJ+sYGQ X-Received: by 2002:a05:620a:9d2:b0:787:6b73:b53c with SMTP id y18-20020a05620a09d200b007876b73b53cmr1248qky.65.1708630838977; Thu, 22 Feb 2024 11:40:38 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708630838; cv=pass; d=google.com; s=arc-20160816; b=pZjFeo/FkEWx1rwxIbQZza3AJSXyECzFRaqlAmSQYHQmHyLHJ8eoGV5b/cCTtNFtpB xMiD1Zinj9LSLbsS+9vTcPs12GfoYGsujer+t+Zrw7oH3OH0x1gJL4CGmdemxjItCslV EPsRASSNdI4eIHrTPGdAbuAq0DybTmBjjOitbQBvH7UjtBjOghgJRy4eOKs7P7WGrij9 IXGveqGE5oJLTSSwt9T3vGwK2jZ7orid6OxIUiWxNN7gBnvJdoDtM2lxLJhquPdqoZ6M YWWWgkxg1W6Z+P3pgeJSFWq7qExqbrX5in3aSVrax0n+QsW1Zam8b1XB6ABxxIyKFxlK xUCg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:message-id :in-reply-to:references:date:from:cc:to:subject:dkim-signature; bh=mNh2djYRdJM+tniBegM28IZIeAmp29AH0SQY98zsjaE=; fh=HUgOPOMLUPcroonsK10/uEWpbBCP57e0QFUoVmMwghQ=; b=h8VNgd4Hkin63d7hGiTMJqmp/EVr1+kWmPGIBbxENSeETMOkj+Nz7z9ywDagvTv89P aR7Tco367DONVeHOymPcg0uG4muWKG+TH8ZkTowp1AiC++aFWu/1Ipjz32qX6xYoKRDd Vj/tYOdxgMqZIp8UDAZHAu+5akmTF2qrk/OX8DL9+Uh2LEjjJZzxkSszk5MIo1FfpmKu sS9bdYjPYWRYZOp36VLLgHw4tMh5t6V1aGFWu0FIpvQTAJSvjVzWG4N4DrDLsyEL82Kx y3QpibaJYu5H2hnFsERYFJR2W9ISd5/nDVS7Kp+YUCc+5BdhsFQpVmU3vHkZU7a2JCm0 aWtg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=PbJzUVpr; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-77188-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-77188-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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'bsp_addr_config' is only used in early boot by the BSP. 2. 'x86_config' is only written once by the BSP and can be used read-only during normal system operation Mark 'bsp_addr_config' so it goes away after boot *and* non-init references to it can be detected and warned about. Mark 'x86_config' as __ro_after_init so it does not turn into the same mess that 'boot_cpu_data' is. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/setup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff -puN arch/x86/kernel/setup.c~mark-new-structs arch/x86/kernel/setup.c --- a/arch/x86/kernel/setup.c~mark-new-structs 2024-02-22 10:09:05.173109438 -0800 +++ b/arch/x86/kernel/setup.c 2024-02-22 10:09:05.177109595 -0800 @@ -131,8 +131,8 @@ struct ist_info ist_info; struct cpuinfo_x86 boot_cpu_data __read_mostly; EXPORT_SYMBOL(boot_cpu_data); -struct x86_addr_config bsp_addr_config; -struct x86_sys_config x86_config __read_mostly; +struct x86_addr_config bsp_addr_config __initdata; +struct x86_sys_config x86_config __ro_after_init; #if !defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64) __visible unsigned long mmu_cr4_features __ro_after_init;