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Wed, 21 Feb 2024 14:04:12 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3wanvkycfg-1; Wed, 21 Feb 2024 14:04:12 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 41LE4Cei013266; Wed, 21 Feb 2024 14:04:12 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 41LE4CA8013260; Wed, 21 Feb 2024 14:04:12 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 0) id 44F4139B8; Wed, 21 Feb 2024 19:34:11 +0530 (+0530) From: root To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, conor+dt@kernel.org, quic_nitegupt@quicinc.com Cc: quic_shazhuss@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Mrinmay Sarkar , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/3] dt-bindings: PCI: qcom: Add global irq support for SA8775p Date: Wed, 21 Feb 2024 19:34:02 +0530 Message-Id: <20240221140405.28532-2-root@hu-msarkar-hyd.qualcomm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240221140405.28532-1-root@hu-msarkar-hyd.qualcomm.com> References: <20240221140405.28532-1-root@hu-msarkar-hyd.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: n3PIdNzPqXevbg6Z9UZMsPFp0XnuC4o2 X-Proofpoint-GUID: n3PIdNzPqXevbg6Z9UZMsPFp0XnuC4o2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 impostorscore=0 mlxscore=0 suspectscore=0 phishscore=0 clxscore=1034 lowpriorityscore=0 mlxlogscore=977 malwarescore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402210109 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791518850022481525 X-GMAIL-MSGID: 1791518850022481525 From: Mrinmay Sarkar Add global interrupt support in dt-bindings for SA8775p RC platform. Signed-off-by: Mrinmay Sarkar --- .../devicetree/bindings/pci/qcom,pcie.yaml | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a93ab3b54066..d86fb63a2d2c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -63,7 +63,7 @@ properties: interrupt-names: minItems: 1 - maxItems: 8 + maxItems: 9 iommu-map: minItems: 1 @@ -873,8 +873,30 @@ allOf: compatible: contains: enum: - - qcom,pcie-msm8996 - qcom,pcie-sa8775p + then: + oneOf: + - properties: + interrupts: + minItems: 9 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: global + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-msm8996 - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sdm845 From patchwork Wed Feb 21 14:04:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: root X-Patchwork-Id: 204226 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp1055506dyc; Wed, 21 Feb 2024 06:06:02 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCV/HUgipLIxFAbFV797Uch2IaXiFbnQAWDgGyIguxG97I1XenyRv/rOaC5SMyoKNnc6xfTmJy/pw01lhbqsb/y1Up4waw== X-Google-Smtp-Source: AGHT+IEJtoFhYuKNHGt5RkrsoEswhQFJ0EmB5hNwa2ASdyVkX3aaLUliAVV4bIvoNAfTG+UEvxux X-Received: by 2002:a6b:6d16:0:b0:7c7:22c3:12a0 with SMTP id a22-20020a6b6d16000000b007c722c312a0mr8268191iod.13.1708524361751; Wed, 21 Feb 2024 06:06:01 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708524361; cv=pass; d=google.com; s=arc-20160816; b=L+2B0Zbcg5T2lEG+GLmECUgIvoD0kLdhm0uRi2UKJKIULqJQTSEkH14eoS10cq/dXx UhzBoVAhfK8R7sg2a4cMGv2/jFRBHegRPsvfty/mJxtJRWOBQZrhhxGOxGBEjoJQgZtC QDrtCN/3V8dtHHXqxXhFo9cyCPZPtUzI4fLGds/CpmTmPG7ZxRKGV45IilXqUHKb70TF mhG+pGWXO3ROIyjZfb0n/1w9+eD+v9oTk7LY53xGGt+V8Wf0w9vwA4LR01qMUWxcWQ8A jTP+KmfoN549Eqy/VUdPxrq8cs3qlT4Nd1M7FlFWu0gaJ9H0Za0K++VVmuwBjKI8/R/S 1OXQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=LopbBaJMkUd7zsUQmDUm/ztdJn+MZ4GTTnsFnoD6hMs=; fh=lEpjFHfZZvDrFHrG/SnE+6N3J7csRUHM97BX7+qUiB8=; b=u+TELiQgow+9GO09nNDPXOvcU4QsdI8Slk4bZA6x3jBnvNcXPYBkSyo2lbyg7zMdfE UubVJtO8dFhte3tuV49r+XF1E5BGFnGIisokONcJ7t3eLBGmO8zLR2a4rmQEdffF+bJU UzRSAYcYpnLJHEIn9EVVxOqxOtMvXm1AiZxXdBMzNlZajDRWEhzgZhrgtsw+8WqbnXD+ jXkgaa1EaBIevU+5IcEsSDj74k4wzGhqzeDUTYwIhFjBfTG6LvJlB0xIYn7BO7a5B2rA VgpO/y6j/X1mlMCbaKvnrOV6jBMZSCyN2Vl/sQrocPRTZGRm4lttzpFClZRBhy1S9xyP FZhg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@qualcomm.com header.s=qcppdkim1 header.b=goVEGZZ2; arc=pass (i=1 spf=pass spfdomain=qualcomm.com dkim=pass dkdomain=qualcomm.com dmarc=pass fromdomain=hu-msarkar-hyd.qualcomm.com); spf=pass (google.com: domain of linux-kernel+bounces-74849-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-74849-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=qualcomm.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Wed, 21 Feb 2024 14:04:13 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3wanvkycg2-1; Wed, 21 Feb 2024 14:04:13 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 41LE4Dsk013291; Wed, 21 Feb 2024 14:04:13 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 41LE4Dn1013288; Wed, 21 Feb 2024 14:04:13 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 0) id 2F78339C4; Wed, 21 Feb 2024 19:34:12 +0530 (+0530) From: root To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, conor+dt@kernel.org, quic_nitegupt@quicinc.com Cc: quic_shazhuss@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Mrinmay Sarkar , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/3] arm64: dts: qcom: sa8775p: Enable global irq support for SA8775p Date: Wed, 21 Feb 2024 19:34:03 +0530 Message-Id: <20240221140405.28532-3-root@hu-msarkar-hyd.qualcomm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240221140405.28532-1-root@hu-msarkar-hyd.qualcomm.com> References: <20240221140405.28532-1-root@hu-msarkar-hyd.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4wALU_qVqBbKAMtbv--65L8fdB7rohgw X-Proofpoint-GUID: 4wALU_qVqBbKAMtbv--65L8fdB7rohgw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 spamscore=0 mlxscore=0 adultscore=0 mlxlogscore=734 bulkscore=0 clxscore=1034 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402210109 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791517641297904969 X-GMAIL-MSGID: 1791517641297904969 From: Mrinmay Sarkar Global irq needed for PCIe controller related error reporting. So adding change to add global irq support for SA8775p RC platform. Signed-off-by: Mrinmay Sarkar --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 73c52f465f87..68efccba50b0 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3552,9 +3552,11 @@ pcie0: pcie@1c00000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, @@ -3652,9 +3654,11 @@ pcie1: pcie@1c10000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, From patchwork Wed Feb 21 14:04:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: root X-Patchwork-Id: 204227 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp1055745dyc; Wed, 21 Feb 2024 06:06:17 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUp4dU5YkIMyH+MJI72wkVAvycuIBRV3ante1tAcZ8/FzTiOVtPXvHUJoEpp54kXxuv6RI1fi+bSSKtJz9fNozjEhbk7w== X-Google-Smtp-Source: AGHT+IENhKnW4DhtT0JxwLkgTeHJryD/4+Wxt1uN6ZTqilhiqmjhy4eXXnkYecBvOzePS+ql8z+1 X-Received: by 2002:a05:6e02:330e:b0:365:2390:9313 with SMTP id bm14-20020a056e02330e00b0036523909313mr15466630ilb.12.1708524377698; Wed, 21 Feb 2024 06:06:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708524377; cv=pass; d=google.com; s=arc-20160816; b=Y0bdMF2B+4/NXGFrk8eTJeEbmLwEAtPDFjKYYRp4x8fP2m3gfm3vWbE3qwSfXyQTNh TGnoITdQuX8SwLpzm+AbQtGHksJmDQYfoPHp9UNhA/1Z15V86scsp0yg/scW/kvP201N 9oHoS4XTYbD/YgofQqLiLynjfNqWjc5fdCi3m7Jf4eeD0W+B5RiwpSQnY9iMSa0obaXU 5D9Cz9JGCyuGPN4AA/e2knbxT1Ts8AzuOVqp6/yVzHL+O+31TDUrbLBb5KYVWZIxsE84 q3ajx8tW4RmeZ4MHlndcrbSi4VW7BiTVtVt2eRRqMpVeUIr9g8EEFfI8m6XaFCL2hHIn NhWA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Tpx8bfMfXMy6EkMR2lV7rJQi8Jwr4iKQdbtQyqtKqiQ=; fh=WOLlm9y/TNb5NbD0cZX4+IP+O8XHshjsYHBUad16518=; b=e4jfJro6Hy62qjMqEWuCLbPHUxEpxwRZ3Bdqaia2yvmj+Txqcsk23bu51Vtvnd1RDY Z5BcJH3RNR4nHhR4eGYD9/0nfisr7soeJkPpNKKtkGD6ZVtg8aTYleF+2lH+bfGbF6lk JC/5InZUQSULaPmXuyvVWXZk5s0m9uOAeHXi3+1Axe3CfpM9RfF6s5qPOQUMPFM/Roci DcKT/AHVPVqjjzxKjzurxo1PY+dudGQv2bTv2rkuemGOnK5zxX25YzxlURRtKRR586tx c3RTRUMmXLtJCivnZZgA/YQmVjHnG9WCQpAr5+H/2sbJF8DO1ifK8Eg0sIsRvPIgPqfC vY5A==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@qualcomm.com header.s=qcppdkim1 header.b=JzIjTMzG; arc=pass (i=1 spf=pass spfdomain=qualcomm.com dkim=pass dkdomain=qualcomm.com dmarc=pass fromdomain=hu-msarkar-hyd.qualcomm.com); spf=pass (google.com: domain of linux-kernel+bounces-74851-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-74851-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=qualcomm.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Wed, 21 Feb 2024 14:04:14 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3wanvkycgp-1; Wed, 21 Feb 2024 14:04:14 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 41LE4E4Q013318; Wed, 21 Feb 2024 14:04:14 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 41LE4EhK013315; Wed, 21 Feb 2024 14:04:14 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 0) id 3430C39B8; Wed, 21 Feb 2024 19:34:13 +0530 (+0530) From: root To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, conor+dt@kernel.org, quic_nitegupt@quicinc.com Cc: quic_shazhuss@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Nitesh Gupta , Mrinmay Sarkar , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/3] PCI: qcom: Add support for detecting controller level PCIe errors Date: Wed, 21 Feb 2024 19:34:04 +0530 Message-Id: <20240221140405.28532-4-root@hu-msarkar-hyd.qualcomm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240221140405.28532-1-root@hu-msarkar-hyd.qualcomm.com> References: <20240221140405.28532-1-root@hu-msarkar-hyd.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WPYgCo4vdFuwidjhMFipRSqHelEtk5Gb X-Proofpoint-ORIG-GUID: WPYgCo4vdFuwidjhMFipRSqHelEtk5Gb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 phishscore=0 suspectscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402210109 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791517658239196385 X-GMAIL-MSGID: 1791517658239196385 From: Nitesh Gupta Synopsys Controllers provide capabilities to detect various controller level errors. These can range from controller interface error to random PCIe configuration errors. This patch intends to add support to detect these errors and report it to userspace entity via sysfs, which can take appropriate actions to mitigate the errors. Signed-off-by: Nitesh Gupta Signed-off-by: Mrinmay Sarkar --- drivers/pci/controller/dwc/pcie-designware.h | 26 ++ drivers/pci/controller/dwc/pcie-qcom.c | 350 +++++++++++++++++++ 2 files changed, 376 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 26dae4837462..cd45f9a2f9bc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -223,6 +223,32 @@ #define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc + +/* + * Error Reporting DBI register + */ +#define DBI_DEVICE_CONTROL_DEVICE_STATUS 0x78 +#define DBI_ROOT_CONTROL_ROOT_CAPABILITIES_REG 0x8c +#define DBI_INTERFACE_TIMER_STATUS 0x938 +#define DBI_SAFETY_MASK_OFF 0x960 +#define DBI_SAFETY_STATUS 0x964 + +#define DBI_ADV_ERR_CAP_CTRL_OFF 0x18 +#define DBI_ROOT_ERR_CMD_OFF 0x2c + +/* + * RAS-DP register + */ +#define PCIE_RASDP_ERROR_MODE_EN_REG 0x28 +#define RASDP_ERROR_MODE_EN BIT(0) + +/* + * Interface Timer register + */ +#define PCIE_INTERFACE_TIMER_CONTROL 0x930 +#define INTERFACE_TIMER_EN BIT(0) +#define INTERFACE_TIMER_AER_EN BIT(1) + /* * The default address offset between dbi_base and atu_base. Root controller * drivers are not required to initialize atu_base if the offset matches this diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 10f2d0bb86be..138e3b08d4b9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -68,6 +69,73 @@ #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 +/* Error Reporting Parf Registers */ +#define PARF_INT_ALL_STATUS 0x224 +#define PARF_INT_ALL_CLEAR 0x228 +#define PARF_INT_CLEAR 0x21c +#define PARF_INT_STATUS 0x220 +#define PARF_INT_ALL_MASK 0x22c +#define PARF_INT_ALL_2_CLEAR 0x504 +#define PARF_INT_ALL_2_STATUS 0x500 +#define PARF_INT_ALL_3_CLEAR 0x2e14 +#define PARF_INT_ALL_3_STATUS 0x2e10 +#define PARF_INT_ALL_4_CLEAR 0x2dd8 +#define PARF_INT_ALL_4_STATUS 0x2dd0 +#define PARF_INT_ALL_5_CLEAR 0x2ddc +#define PARF_INT_ALL_5_STATUS 0x2dd4 +#define PARF_CFG_SAFETY_INT_MASK_CTRL 0x2c60 + + +#define PCIE_AER_EXT_CAP_ID 0x01 +#define PCI_EXT_CAP_RASDP_ID 0x0b + +/* Interrupt Masks */ +#define CFGPCIE_INT_ALL_STATUS_MASK 0x3ff3e +#define CFGPCIE_PARF_INT_STATUS_MASK 0x1b +#define CFGPCIE_INTERFACE_TIMER_STATUS_MASK 0xe7b +#define CFGPCIE_INT_ALL_2_STATUS_MASK GENMASK(24, 0) +#define CFGPCIE_INT_ALL_3_STATUS_MASK GENMASK(31, 0) +#define CFGPCIE_INT_ALL_4_STATUS_MASK GENMASK(31, 0) +#define CFGPCIE_INT_ALL_5_STATUS_MASK GENMASK(31, 0) + +/* PCI_INTERRUPT_LINE register field */ +#define SERR_EN BIT(17) + +/* DBI_ROOT_CONTROL_ROOT_CAPABILITIES_REG register fields */ +#define PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN BIT(0) +#define PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN BIT(1) +#define PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN BIT(2) + +/* DBI_DEVICE_CONTROL_DEVICE_STATUS register fields */ +#define PCIE_CAP_UNSUPPORT_REQ_REP_EN BIT(3) +#define PCIE_CAP_FATAL_ERR_REPORT_EN BIT(2) +#define PCIE_CAP_NON_FATAL_ERR_REPORT_EN BIT(1) +#define PCIE_CAP_CORR_ERR_REPORT_EN BIT(0) + +/* PARF_CFG_SAFETY_INT_MASK_CTRL register fields */ +#define CFG_SAFETY_UNCORR_INT_MASK BIT(0) +#define CFG_SAFETY_CORR_INT_MASK BIT(1) + +/* DBI_ADV_ERR_CAP_CTRL_OFF register fields */ +#define ECRC_GEN_EN BIT(6) +#define ECRC_CHECK_EN BIT(8) + +/* DBI_ROOT_ERR_CMD_OFF register fields */ +#define CORR_ERR_REPORTING_EN BIT(0) +#define NON_FATAL_ERR_REPORTING_EN BIT(1) +#define FATAL_ERR_REPORTING_EN BIT(2) + +/* DBI_SAFETY_MASK_OFF register fields */ +#define SAFETY_INT_MASK GENMASK(5, 0) + +/* DBI_SAFETY_STATUS register fields */ +#define PCIE_RASDP_UNCORR_ERR BIT(0) +#define PCIE_IFACE_TMR_ERR BIT(1) +#define PCIE_CDM_CHK_ERR BIT(2) +#define PCIE_AER_UNCORR_ERR BIT(3) +#define PCIE_AER_CORR_ERR BIT(4) +#define PCIE_RASDP_CORR_ERR BIT(5) + /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) #define MST_WAKEUP_EN BIT(13) @@ -231,6 +299,24 @@ struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; }; +enum qcom_pcie_fault_code { + RASDP_UNCORR_ERROR, /* RASDP uncorrectable error */ + RASDP_CORR_ERROR, /* RASDP correctable error */ + CDM_REG_CHK_ERROR, /* CDM register check error */ + INTERFACE_TIMER_ERROR, /* PCIe local bus interface timer error */ + PCIE_SPURIOUS_INT, /* Spurious Interrupt received */ + MAX_PCIE_SAFETY_FAULT /* Maximum PCIe fault source code supported */ +}; + +static const char * const pcie_fault_string[] = { + "RASDP_Uncorr_Error", + "RASDP_Corr_Error", + "CDM_Reg_Chk_Error", + "Interface_Timer_Error", + "PCIe_Spurious_Interrupt", + "TOTAL_PCIE_FAULTS", +}; + struct qcom_pcie { struct dw_pcie *pci; void __iomem *parf; /* DT parf */ @@ -243,6 +329,10 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; + int global_irq; + spinlock_t safety_lock; + u32 pcie_fault[MAX_PCIE_SAFETY_FAULT]; + u32 pcie_fault_total; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -959,9 +1049,94 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } +static void qcom_pcie_enable_error_reporting_2_7_0(struct qcom_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + u32 val, offset; + + /* Clear all the interrupts before we enable it */ + writel(0, pci->dbi_base + DBI_SAFETY_STATUS); + writel(0, pci->dbi_base + DBI_INTERFACE_TIMER_STATUS); + + /* Enable interrupts which are aggregated using GLOBAL_INT */ + writel(CFGPCIE_INT_ALL_STATUS_MASK, pcie->parf + PARF_INT_ALL_CLEAR); + writel(CFGPCIE_PARF_INT_STATUS_MASK, pcie->parf + PARF_INT_CLEAR); + writel(CFGPCIE_INT_ALL_2_STATUS_MASK, pcie->parf + PARF_INT_ALL_2_CLEAR); + writel(CFGPCIE_INT_ALL_3_STATUS_MASK, pcie->parf + PARF_INT_ALL_3_CLEAR); + writel(CFGPCIE_INT_ALL_4_STATUS_MASK, pcie->parf + PARF_INT_ALL_4_CLEAR); + writel(CFGPCIE_INT_ALL_5_STATUS_MASK, pcie->parf + PARF_INT_ALL_5_CLEAR); + + dw_pcie_dbi_ro_wr_en(pci); + + val = readl(pci->dbi_base + PCI_INTERRUPT_LINE); + val |= SERR_EN; + writel(val, pci->dbi_base + PCI_INTERRUPT_LINE); + + val = readl(pci->dbi_base + DBI_DEVICE_CONTROL_DEVICE_STATUS); + val |= (PCIE_CAP_CORR_ERR_REPORT_EN | PCIE_CAP_NON_FATAL_ERR_REPORT_EN | + PCIE_CAP_FATAL_ERR_REPORT_EN | PCIE_CAP_UNSUPPORT_REQ_REP_EN); + writel(val, pci->dbi_base + DBI_DEVICE_CONTROL_DEVICE_STATUS); + + val = readl(pci->dbi_base + DBI_ROOT_CONTROL_ROOT_CAPABILITIES_REG); + val |= (PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN | PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN | + PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN); + writel(val, pci->dbi_base + DBI_ROOT_CONTROL_ROOT_CAPABILITIES_REG); + + dw_pcie_dbi_ro_wr_dis(pci); + + /* Enable RAS-DP Interrupts */ + offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_RASDP_ID); + val = readl(pci->dbi_base + offset + PCIE_RASDP_ERROR_MODE_EN_REG); + val |= RASDP_ERROR_MODE_EN; + writel(val, pci->dbi_base + PCIE_RASDP_ERROR_MODE_EN_REG); + + /* Enable CDM Check */ + val = readl(pci->dbi_base + PCIE_PL_CHK_REG_CONTROL_STATUS); + /* Enable continuous CMD register check mode */ + val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS; + /* Start the CDM register check */ + val |= PCIE_PL_CHK_REG_CHK_REG_START; + /* Enable comparison CDM register check mode */ + val |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR; + /* Enable logic CDM register check mode */ + val |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR; + writel(val, pci->dbi_base + PCIE_PL_CHK_REG_CONTROL_STATUS); + + /* Interface Timer Enable */ + val = readl(pci->dbi_base + PCIE_INTERFACE_TIMER_CONTROL); + val |= (INTERFACE_TIMER_EN | INTERFACE_TIMER_AER_EN); + writel(val, pci->dbi_base + PCIE_INTERFACE_TIMER_CONTROL); + + /* Enable safety correctable and uncorrectable error reporting */ + val = readl(pcie->parf + PARF_CFG_SAFETY_INT_MASK_CTRL); + val |= (CFG_SAFETY_UNCORR_INT_MASK | CFG_SAFETY_CORR_INT_MASK); + writel(val, pcie->parf + PARF_CFG_SAFETY_INT_MASK_CTRL); + + /* Enable CRC check and generation */ + offset = dw_pcie_find_ext_capability(pci, PCIE_AER_EXT_CAP_ID); + val = readl(pci->dbi_base + offset + DBI_ADV_ERR_CAP_CTRL_OFF); + val |= (ECRC_GEN_EN | ECRC_CHECK_EN); + writel(val, pci->dbi_base + offset + DBI_ADV_ERR_CAP_CTRL_OFF); + + /* Enable AER */ + val = readl(pci->dbi_base + offset + DBI_ROOT_ERR_CMD_OFF); + val |= (CORR_ERR_REPORTING_EN | NON_FATAL_ERR_REPORTING_EN + | FATAL_ERR_REPORTING_EN); + writel(val, pci->dbi_base + offset + DBI_ROOT_ERR_CMD_OFF); + + /* Enable interrupts */ + val = readl(pci->dbi_base + DBI_SAFETY_MASK_OFF); + val &= ~(SAFETY_INT_MASK); + writel(val, pci->dbi_base + DBI_SAFETY_MASK_OFF); + + /* Disable Legacy Interrupts */ + writel(0, pcie->parf + PARF_INT_ALL_MASK); +} + static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) { qcom_pcie_clear_hpc(pcie->pci); + qcom_pcie_enable_error_reporting_2_7_0(pcie); return 0; } @@ -1416,6 +1591,130 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) } } +static void qcom_pcie_check_spurious_int(struct qcom_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + u32 *pcie_fault = pcie->pcie_fault; + struct device *dev = pci->dev; + struct kobject *kobj_ref = &dev->kobj; + u32 val; + + val = readl(pci->dbi_base + DBI_INTERFACE_TIMER_STATUS); + if (val & CFGPCIE_INTERFACE_TIMER_STATUS_MASK) + return; + + val = readl(pcie->parf + PARF_INT_ALL_STATUS); + if (val & CFGPCIE_INT_ALL_STATUS_MASK) + return; + + val = readl(pcie->parf + PARF_INT_STATUS); + if (val & CFGPCIE_PARF_INT_STATUS_MASK) + return; + + val = readl(pcie->parf + PARF_INT_ALL_2_STATUS); + if (val & CFGPCIE_INT_ALL_2_STATUS_MASK) + return; + + val = readl(pcie->parf + PARF_INT_ALL_3_STATUS); + if (val & CFGPCIE_INT_ALL_3_STATUS_MASK) + return; + + val = readl(pcie->parf + PARF_INT_ALL_4_STATUS); + if (val & CFGPCIE_INT_ALL_4_STATUS_MASK) + return; + + val = readl(pcie->parf + PARF_INT_ALL_5_STATUS); + if (val & CFGPCIE_INT_ALL_5_STATUS_MASK) + return; + + dev_err(pci->dev, "PCIe Spurious Interrupt"); + pcie_fault[PCIE_SPURIOUS_INT]++; + pcie->pcie_fault_total++; + sysfs_notify(kobj_ref, NULL, "qcom_pcie_error_report"); +} + +static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) +{ + struct qcom_pcie *pcie = data; + struct dw_pcie *pci = pcie->pci; + u32 *pcie_fault = pcie->pcie_fault; + struct device *dev = pci->dev; + struct kobject *kobj_ref = &dev->kobj; + unsigned long irqsave_flags; + u32 val, int_status; + + spin_lock_irqsave(&pcie->safety_lock, irqsave_flags); + + int_status = readl(pci->dbi_base + DBI_SAFETY_STATUS); + writel(0, pci->dbi_base + DBI_SAFETY_STATUS); + + if (int_status) { + dev_err(pci->dev, "global interrupt fired status: %u", int_status); + + if (int_status & PCIE_RASDP_UNCORR_ERR) { + dev_err(pci->dev, "RASDP uncorrectable error triggered"); + pcie_fault[RASDP_UNCORR_ERROR]++; + pcie->pcie_fault_total++; + sysfs_notify(kobj_ref, NULL, "qcom_pcie_error_report"); + + /* + * rasdp_uncorr_err ends up triggering a + * pcie_uncorr error continuously. So masking + * pcie_uncorr interrupts . + */ + val = readl(pci->dbi_base + DBI_SAFETY_MASK_OFF); + val |= PCIE_AER_UNCORR_ERR; + writel(val, pci->dbi_base + DBI_SAFETY_MASK_OFF); + } + + if (int_status & PCIE_CDM_CHK_ERR) { + dev_err(pci->dev, "CDM error triggered"); + val = readl(pci->dbi_base + PCIE_PL_CHK_REG_CONTROL_STATUS); + + if (val & PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR) { + pcie_fault[CDM_REG_CHK_ERROR]++; + pcie->pcie_fault_total++; + sysfs_notify(kobj_ref, NULL, "qcom_pcie_error_report"); + + /* + * cdm_chk_err injection results in a continuous + * interrupt storm on certain targets, so masking it. + */ + val = readl(pci->dbi_base + DBI_SAFETY_MASK_OFF); + val |= (PCIE_CDM_CHK_ERR | PCIE_AER_UNCORR_ERR); + writel(val, pci->dbi_base + DBI_SAFETY_MASK_OFF); + } + } + + if (int_status & PCIE_IFACE_TMR_ERR) { + dev_err(pci->dev, "Iface Timeout error triggered"); + pcie_fault[INTERFACE_TIMER_ERROR]++; + pcie->pcie_fault_total++; + sysfs_notify(kobj_ref, NULL, "qcom_pcie_error_report"); + + /* + * interface_timer_err injection results in a continuous + * interrupt storm on certain targets, so masking it. + */ + val = readl(pci->dbi_base + DBI_SAFETY_MASK_OFF); + val |= (PCIE_IFACE_TMR_ERR | PCIE_AER_UNCORR_ERR); + writel(val, pci->dbi_base + DBI_SAFETY_MASK_OFF); + } + + if (int_status & PCIE_RASDP_CORR_ERR) { + dev_err(pci->dev, "RASDP correctable error triggered"); + pcie_fault[RASDP_CORR_ERROR]++; + pcie->pcie_fault_total++; + sysfs_notify(kobj_ref, NULL, "qcom_pcie_error_report"); + } + } else { + qcom_pcie_check_spurious_int(pcie); + } + + spin_unlock_irqrestore(&pcie->safety_lock, irqsave_flags); + return IRQ_HANDLED; +} + static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) { struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); @@ -1438,6 +1737,40 @@ static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) return 0; } +static ssize_t qcom_pcie_error_report_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned int i; + struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(dev); + u32 *pcie_fault = pcie->pcie_fault; + size_t len = 0; + + for (i = 0; i < MAX_PCIE_SAFETY_FAULT; i++) { + if (pcie_fault_string[i]) + len += sysfs_emit_at(buf, len, "%s: %lu\n", + pcie_fault_string[i], + pcie_fault[i]); + } + + len += sysfs_emit_at(buf, len, "%s: %lu\n", + pcie_fault_string[i], + pcie->pcie_fault_total); + + return len; +} +static DEVICE_ATTR_RO(qcom_pcie_error_report); + +static struct attribute *qcom_pcie_attrs[] = { + &dev_attr_qcom_pcie_error_report.attr, + NULL, +}; + +static const struct attribute_group qcom_pcie_attribute_group = { + .attrs = qcom_pcie_attrs, + .name = "qcom_pcie" +}; + static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; @@ -1496,6 +1829,21 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + pcie->global_irq = platform_get_irq_byname(pdev, "global"); + if (pcie->global_irq < 0) { + ret = pcie->global_irq; + goto err_pm_runtime_put; + } + + ret = devm_request_threaded_irq(dev, pcie->global_irq, NULL, + qcom_pcie_global_irq_thread, + IRQF_ONESHOT, + "global_irq", pcie); + if (ret) { + dev_err(dev, "Failed to request Global IRQ\n"); + goto err_pm_runtime_put; + } + pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); if (IS_ERR(pcie->parf)) { ret = PTR_ERR(pcie->parf); @@ -1551,6 +1899,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) if (pcie->mhi) qcom_pcie_init_debugfs(pcie); + sysfs_create_group(&pdev->dev.kobj, &qcom_pcie_attribute_group); + return 0; err_phy_exit: