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Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 07ba709ca35f..27ce382cb594 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1372,6 +1372,82 @@ mmss_noc: interconnect@1780000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,sm8550-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", "qref"; + clocks = <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + + power-domains = <&gcc UFS_MEM_PHY_GDSC>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d80400 { + reg = <0x0 0x01d81000 0x0 0x134>, + <0x0 0x01d81200 0x0 0x3d8>, + <0x0 0x01d80400 0x0 0x258>, + <0x0 0x01d81800 0x0 0x134>, + <0x0 0x01d81a00 0x0 0x3d8>; + #phy-cells = <0>; + }; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm8550-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0x60 0x0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; + + interconnect-names = "ufs-ddr", "cpu-ufs"; + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From patchwork Wed Nov 16 12:51:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 21048 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp123656wru; Wed, 16 Nov 2022 04:58:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf4V74diq7WYmW5W1OMSrnLiU6V+c245iYWcOfo3+f4F5K2V2hVREjSkzIE87brnwfkafmhH X-Received: by 2002:a17:906:950d:b0:78d:9b4f:44ee with SMTP id u13-20020a170906950d00b0078d9b4f44eemr17345768ejx.679.1668603538502; Wed, 16 Nov 2022 04:58:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668603538; cv=none; d=google.com; s=arc-20160816; b=iAKFP37y3daCyM48Yy70vxQ2Hvxq0TMMM6mDsrVdvsOGLK01j0YZ9r5Uwy8YnFZDf6 PkyVycpowJfPCEWRdzh2V7m62qYLWnK/Lc069ZFeZVnq0QxD5Y5ke7Mfvm3cQHOcyyuw H3mtAz+3WhA+dlrdd2pcJ8DsEXUaZDnv3zQ3RlPrvnatUd9x7p0+thb/zFE6bmVmaYUF 4Eyz+hcBBCv3XVNDE9zORmeaHsuXijlRRZD9jqa1CqlSz/zWdtk5T6RP8BKDabfTUO0D lhebK6PNBAe0djNQ1EumNmsHDQ0lKaQIZrJdlBay3bDk0NoV3se+OA+10Bl9fVErsFyH 9V2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=H2H1d5sAZJ+t9NwoF1iOHgYCETQzv/jXX7CIaFm3b3E=; b=IL+zoaNIb3Ja6xoYqRW/LnOnYvATUcCRK4IfBMwuZo5GtOVKc5yZlsRwuvvxSFjepc onNQOd7hr8DEV+UdITbS2JowGQMSSq1QdOl+g900Os7lhMICtd5FJxZMDKhEz62wN1JW 8znMPR8YZS0bnFVWKZSCz4nz6E7e5sVj0CcgJ13qfs8xTs1jaMuLKayyUpCVYFNAxbIR 0YuUTcOpLBsHDBrrV5Jo+6/KzNpGqlzyGqWLKI/fB6LJafE6CawIu1RsdEv9SBLoCv/i AghSWCXxdSLuoyO0tuQJcv0Zxv6aRxe5jUgV1EW5dYq14Wm+gYD0nC2qdGz35lN3Kurd N7fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gGxjSUZp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index d4c8d5b2497e..fef7793a7dec 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -417,3 +417,25 @@ data-pins { &uart7 { status = "okay"; }; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vccq2-supply = <&vreg_l3g_1p2>; + vccq2-max-microamp = <100>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-phy-max-microamp = <188000>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-pll-max-microamp = <18300>; +};