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Tue, 20 Feb 2024 17:55:54 +0000 (GMT) Message-ID: <6044dc7e-7068-488c-8451-1541582fc2de@linux.ibm.com> Date: Tue, 20 Feb 2024 09:55:53 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 01/11] rs6000, Fix __builtin_vsx_cmple* args and documentation, builtins Content-Language: en-US To: gcc-patches@gcc.gnu.org, "bergner@linux.ibm.com" , Segher Boessenkool , "Kewen.Lin" References: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> From: Carl Love In-Reply-To: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 6wC5BGeDk-ziAK51wcvDB3FINcM-7Sat X-Proofpoint-GUID: 6wC5BGeDk-ziAK51wcvDB3FINcM-7Sat X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 mlxlogscore=998 spamscore=0 clxscore=1015 adultscore=0 priorityscore=1501 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402200128 X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791441594925771793 X-GMAIL-MSGID: 1791441594925771793 GCC maintainers: This patch fixes the arguments and return type for the various __builtin_vsx_cmple* built-ins. They were defined as signed but should have been defined as unsigned. The patch has been tested on Power 10 with no regressions. Please let me know if this patch is acceptable for mainline. Thanks. Carl ----------------------------------------------------- rs6000, Fix __builtin_vsx_cmple* args and documentation, builtins The built-ins __builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u2di, __builtin_vsx_cmple_u4si and __builtin_vsx_cmple_u8hi should take unsigned arguments and return an unsigned result. This patch changes the arguments and return type from signed to unsigned. The documentation for the signed and unsigned versions of __builtin_vsx_cmple is missing from extend.texi. This patch adds the missing documentation. Test cases are added for each of the signed and unsigned built-ins. gcc/ChangeLog: * config/rs6000/rs6000-builtins.def (__builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u2di, __builtin_vsx_cmple_u4si): Change arguments and return from signed to unsigned. * doc/extend.texi (__builtin_vsx_cmple_16qi, __builtin_vsx_cmple_8hi, __builtin_vsx_cmple_4si, __builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u8hi, __builtin_vsx_cmple_u4si): Add documentation. gcc/testsuite/ChangeLog: * gcc.target/powerpc/vsx-cmple.c: New test file. --- gcc/config/rs6000/rs6000-builtins.def | 10 +- gcc/doc/extend.texi | 23 ++++ gcc/testsuite/gcc.target/powerpc/vsx-cmple.c | 127 +++++++++++++++++++ 3 files changed, 155 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-cmple.c diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 3bc7fed6956..d66a53a0fab 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -1349,16 +1349,16 @@ const vss __builtin_vsx_cmple_8hi (vss, vss); CMPLE_8HI vector_ngtv8hi {} - const vsc __builtin_vsx_cmple_u16qi (vsc, vsc); + const vuc __builtin_vsx_cmple_u16qi (vuc, vuc); CMPLE_U16QI vector_ngtuv16qi {} - const vsll __builtin_vsx_cmple_u2di (vsll, vsll); + const vull __builtin_vsx_cmple_u2di (vull, vull); CMPLE_U2DI vector_ngtuv2di {} - const vsi __builtin_vsx_cmple_u4si (vsi, vsi); + const vui __builtin_vsx_cmple_u4si (vui, vui); CMPLE_U4SI vector_ngtuv4si {} - const vss __builtin_vsx_cmple_u8hi (vss, vss); + const vus __builtin_vsx_cmple_u8hi (vus, vus); CMPLE_U8HI vector_ngtuv8hi {} const vd __builtin_vsx_concat_2df (double, double); @@ -1769,7 +1769,7 @@ const vf __builtin_vsx_xvcvuxdsp (vull); XVCVUXDSP vsx_xvcvuxdsp {} - const vd __builtin_vsx_xvcvuxwdp (vsi); + const vd __builtin_vsx_xvcvuxwdp (vui); XVCVUXWDP vsx_xvcvuxwdp {} const vf __builtin_vsx_xvcvuxwsp (vsi); diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 2b8ba1949bf..4d8610f6aa8 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -22522,6 +22522,29 @@ if the VSX instruction set is available. The @samp{vec_vsx_ld} and @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X}, @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. + +@smallexample +vector signed char __builtin_vsx_cmple_16qi (vector signed char, + vector signed char); +vector signed short __builtin_vsx_cmple_8hi (vector signed short, + vector signed short); +vector signed int __builtin_vsx_cmple_4si (vector signed int, + vector signed int); +vector unsigned char __builtin_vsx_cmple_u16qi (vector unsigned char, + vector unsigned char); +vector unsigned short __builtin_vsx_cmple_u8hi (vector unsigned short, + vector unsigned short); +vector unsigned int __builtin_vsx_cmple_u4si (vector unsigned int, + vector unsigned int); +@end smallexample + +The builti-ins @code{__builtin_vsx_cmple_16qi}, @code{__builtin_vsx_cmple_8hi}, +@code{__builtin_vsx_cmple_4si}, @code{__builtin_vsx_cmple_u16qi}, +@code{__builtin_vsx_cmple_u8hi} and @code{__builtin_vsx_cmple_u4si} compare +vectors of their defined type. The corresponding result element is set to +all ones if the two argument elements are less than or equal and all zeros +otherwise. + @node PowerPC AltiVec Built-in Functions Available on ISA 2.07 @subsubsection PowerPC AltiVec Built-in Functions Available on ISA 2.07 diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c b/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c new file mode 100644 index 00000000000..081817b4ba3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c @@ -0,0 +1,127 @@ +/* { dg-do run } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -save-temps" } */ + +#define DEBUG 0 + +#include + +#if DEBUG +#include +#include +#endif + +void abort (void); + +#if DEBUG + #define ACTION(NAME, TYPE_NAME) \ + printf ("test_vsx_cmple_%s: result_%s[%d] = 0x%x, expected_result_%s[%d] = 0x%x\n", \ + #NAME, #TYPE_NAME, i, result_##TYPE_NAME[i], \ + #TYPE_NAME, i, (int)expected_result_##TYPE_NAME[i]); +#else + #define ACTION(NAME, TYPE_NAME) \ + abort(); +#endif + +#define TEST(NAME, TYPE, TYPE_NAME) \ +void test_vsx_cmple_##NAME (vector TYPE arg1_##TYPE_NAME, \ + vector TYPE arg2_##TYPE_NAME, \ + vector TYPE expected_result_##TYPE_NAME) \ +{ \ + vector TYPE result_##TYPE_NAME; \ + int i, len = 16/sizeof(TYPE); \ + \ + result_##TYPE_NAME = __builtin_vsx_cmple_##NAME (arg1_##TYPE_NAME, \ + arg2_##TYPE_NAME); \ + for (i = 0; i < len; i++) \ + if (result_##TYPE_NAME[i] != expected_result_##TYPE_NAME[i]) \ + ACTION(TYPE, TYPE_NAME) \ +} + +int main () +{ + + vector signed char vsc_arg1, vsc_arg2, vsc_expected_result; + vector signed short vsh_arg1, vsh_arg2, vsh_expected_result; + vector signed int vsi_arg1, vsi_arg2, vsi_expected_result; + vector signed long long vsll_arg1, vsll_arg2, vsll_expected_result; + vector unsigned char vuc_arg1, vuc_arg2, vuc_expected_result; + vector unsigned short vuh_arg1, vuh_arg2, vuh_expected_result; + vector unsigned int vui_arg1, vui_arg2, vui_expected_result; + vector unsigned long long vull_arg1, vull_arg2, vull_expected_result; + + vsc_arg1 = (vector signed char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, + 14, 15, 16}; + vsc_arg2 = (vector signed char) {11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26}; + vsc_expected_result = (vector signed char) {0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}; + /* Test for __builtin_vsx_cmple_16qi */ + TEST (16qi, signed char, vsc) + test_vsx_cmple_16qi (vsc_arg1, vsc_arg2, vsc_expected_result); + + vsh_arg1 = (vector signed short) {1, 2, 3, 4, 5, 6, 7, 8}; + vsh_arg2 = (vector signed short) {11, 12, 13, 14, 15, 16, 17, 18}; + vsh_expected_result = (vector signed short) {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF}; + /* Test for __builtin_vsx_cmple_8hi */ + TEST (8hi, signed short, vsh) + test_vsx_cmple_8hi (vsh_arg1, vsh_arg2, vsh_expected_result); + + vsi_arg1 = (vector signed int) {1, 2, 3, 4}; + vsi_arg2 = (vector signed int) {11, 12, 13, 14}; + vsi_expected_result = (vector signed int) {0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF}; + /* Test for __builtin_vsx_cmple_4si */ + TEST (4si, signed int, vsi) + test_vsx_cmple_4si (vsi_arg1, vsi_arg2, vsi_expected_result); + + vsll_arg1 = (vector signed long long) {1, 2}; + vsll_arg2 = (vector signed long long) {11, 12}; + vsll_expected_result = (vector signed long long) {0xFFFFFFFFFFFFFFFF, + 0xFFFFFFFFFFFFFFFF}; + /* Test for __builtin_vsx_cmple_2di */ + TEST (2di, signed long long, vsll) + test_vsx_cmple_2di (vsll_arg1, vsll_arg2, vsll_expected_result); + + vuc_arg1 = (vector unsigned char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, + 14, 15, 16}; + vuc_arg2 = (vector unsigned char) {11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26}; + vuc_expected_result = (vector unsigned char) {0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}; + /* Test for __builtin_vsx_cmple_u16qi */ + TEST (u16qi, unsigned char, vuc) + test_vsx_cmple_u16qi (vuc_arg1, vuc_arg2, vuc_expected_result); + + vuh_arg1 = (vector unsigned short) {1, 2, 3, 4, 5, 6, 7, 8}; + vuh_arg2 = (vector unsigned short) {11, 12, 13, 14, 15, 16, 17, 18}; + vuh_expected_result = (vector unsigned short) {0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF}; + /* Test for __builtin_vsx_cmple_u8hi */ + TEST (u8hi, unsigned short, vuh) + test_vsx_cmple_u8hi (vuh_arg1, vuh_arg2, vuh_expected_result); + + vui_arg1 = (vector unsigned int) {1, 2, 3, 4}; + vui_arg2 = (vector unsigned int) {11, 12, 13, 14}; + vui_expected_result = (vector unsigned int) {0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF}; + /* Test for __builtin_vsx_cmple_u4si */ + TEST (u4si, unsigned int, vui) + test_vsx_cmple_u4si (vui_arg1, vui_arg2, vui_expected_result); + + vull_arg1 = (vector unsigned long long) {1, 2}; + vull_arg2 = (vector unsigned long long) {11, 12}; + vull_expected_result = (vector unsigned long long) {0xFFFFFFFFFFFFFFFF, + 0xFFFFFFFFFFFFFFFF}; + /* Test for __builtin_vsx_cmple_u2di */ + TEST (u2di, unsigned long long, vull) + test_vsx_cmple_u2di (vull_arg1, vull_arg2, vull_expected_result); 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Tue, 20 Feb 2024 17:56:08 +0000 (GMT) Message-ID: Date: Tue, 20 Feb 2024 09:56:08 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 02/11] rs6000, fix arguments, add documentation for vector, element conversions Content-Language: en-US To: gcc-patches@gcc.gnu.org, "bergner@linux.ibm.com" , Segher Boessenkool , "Kewen.Lin" References: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> From: Carl Love In-Reply-To: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: mEzPbdx6tnVU7IfKhAMd6gdcMxr03kwf X-Proofpoint-GUID: mEzPbdx6tnVU7IfKhAMd6gdcMxr03kwf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 adultscore=0 priorityscore=1501 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402200128 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791441613489476804 X-GMAIL-MSGID: 1791441613489476804 GCC maintainers: This patch fixes the return type for the __builtin_vsx_xvcvdpuxws and __builtin_vsx_xvcvspuxds built-ins. They were defined as signed but should have been defined as unsigned. The patch has been tested on Power 10 with no regressions. Please let me know if this patch is acceptable for mainline. Thanks. Carl ----------------------------------------------------- rs6000, fix arguments, add documentation for vector element conversions The return type for the __builtin_vsx_xvcvdpuxws, __builtin_vsx_xvcvspuxds, __builtin_vsx_xvcvspuxws built-ins should be unsigned. This patch changes the return values from signed to unsigned. The documentation for the vector element conversion built-ins: __builtin_vsx_xvcvspsxws __builtin_vsx_xvcvspsxds __builtin_vsx_xvcvspuxds __builtin_vsx_xvcvdpsxws __builtin_vsx_xvcvdpuxws __builtin_vsx_xvcvdpuxds_uns __builtin_vsx_xvcvspdp __builtin_vsx_xvcvdpsp __builtin_vsx_xvcvspuxws __builtin_vsx_xvcvsxwdp __builtin_vsx_xvcvuxddp_uns __builtin_vsx_xvcvuxwdp is missing from extend.texi. This patch adds the missing documentation. This patch also adds runnable test cases for each of the built-ins. gcc/ChangeLog: * config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvdpuxws, __builtin_vsx_xvcvspuxds, __builtin_vsx_xvcvspuxws): Change return type from signed to unsigned. * doc/extend.texi (__builtin_vsx_xvcvspsxws, __builtin_vsx_xvcvspsxds, __builtin_vsx_xvcvspuxds, __builtin_vsx_xvcvdpsxws, __builtin_vsx_xvcvdpuxws, __builtin_vsx_xvcvdpuxds_uns, __builtin_vsx_xvcvspdp, __builtin_vsx_xvcvdpsp, __builtin_vsx_xvcvspuxws, __builtin_vsx_xvcvsxwdp, __builtin_vsx_xvcvuxddp_uns, __builtin_vsx_xvcvuxwdp): Add documentation for builtins. gcc/testsuite/ChangeLog: * gcc.target/powerpc/vsx-builtin-runnable-1.c: New test file. --- gcc/config/rs6000/rs6000-builtins.def | 6 +- gcc/doc/extend.texi | 135 ++++++++++ .../powerpc/vsx-builtin-runnable-1.c | 233 ++++++++++++++++++ 3 files changed, 371 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index d66a53a0fab..fd316f629e5 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -1724,7 +1724,7 @@ const vull __builtin_vsx_xvcvdpuxds_uns (vd); XVCVDPUXDS_UNS vsx_fixuns_truncv2dfv2di2 {} - const vsi __builtin_vsx_xvcvdpuxws (vd); + const vui __builtin_vsx_xvcvdpuxws (vd); XVCVDPUXWS vsx_xvcvdpuxws {} const vd __builtin_vsx_xvcvspdp (vf); @@ -1736,10 +1736,10 @@ const vsi __builtin_vsx_xvcvspsxws (vf); XVCVSPSXWS vsx_fix_truncv4sfv4si2 {} - const vsll __builtin_vsx_xvcvspuxds (vf); + const vull __builtin_vsx_xvcvspuxds (vf); XVCVSPUXDS vsx_xvcvspuxds {} - const vsi __builtin_vsx_xvcvspuxws (vf); + const vui __builtin_vsx_xvcvspuxws (vf); XVCVSPUXWS vsx_fixuns_truncv4sfv4si2 {} const vd __builtin_vsx_xvcvsxddp (vsll); diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 4d8610f6aa8..583b1d890bf 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21360,6 +21360,141 @@ __float128 __builtin_sqrtf128 (__float128); __float128 __builtin_fmaf128 (__float128, __float128, __float128); @end smallexample +@smallexample +vector int __builtin_vsx_xvcvspsxws (vector float); +@end smallexample + +The @code{__builtin_vsx_xvcvspsxws} converts the single precision floating +point vector element i to a signed single-precision integer value using +round to zero storing the result in element i. If the source element is NaN +the result is set to 0x80000000 and VXCI is set to 1. If the source +element is SNaN then VXSNAN is also set to 1. If the rounded value is greater +than 2^31 - 1 the result is 0x7FFFFFFF and VXCVI is set to 1. If the +rounded value is less than -2^31, the result is set to 0x80000000 and +VXCVI is set to 1. If the rounded result is inexact then XX is set to 1. + +@smallexample +vector signed long long int __builtin_vsx_xvcvspsxds (vector float); +@end smallexample + +The @code{__builtin_vsx_xvcvspsxds} converts the single precision floating +point vector element to a double precision signed integer value using the +round to zero rounding mode. If the source element is NaN the result +is set to 0x8000000000000000 and VXCI is set to 1. If the source element is +SNaN then VXSNAN is also set to 1. If the rounded value is greater than +2^63 - 1 the result is 0x7FFFFFFFFFFFFFFF and VXCVI is set to 1. If the +rounded value is less than zero, the result is set to 0x8000000000000000 and +VXCVI is set to 1. If the rounded result is inexact then XX is set to 1. + +@smallexample +vector unsigned long long __builtin_vsx_xvcvspuxds (vector float); +@end smallexample + +The @code{__builtin_vsx_xvcvspuxds} converts the single precision floating +point vector element 2*i to an unsigned double-precision integer value using +round to zero storing the result in element i. If the source element is NaN +the result is set to 0x0000000000000000 and VXCI is set to 1. If the source +element is SNaN then VXSNAN is also set to 1. If the rounded value is greater +than 2^63 - 1 the result is 0xFFFFFFFFFFFFFFFF and VXCVI is set to 1. If the +rounded value is less than -2^63, the result is set to 0x0000000000000000 and +VXCVI is set to 1. If the rounded result is inexact then XX is set to 1. + +@smallexample +vector signed int __builtin_vsx_xvcvdpsxws (vector double); +@end smallexample + +The @code{__builtin_vsx_xvcvdpsxws} converts the ith double precision floating +point vector element to a single-precision integer value using the round to +zero rounding mode. The single precision integer value is placed into vector +elements j and j+1 where j = i*2. If the source element is NaN the result +is set to 0x80000000 and VXCI is set to 1. If the source element is SNaN then +VXSNAN is also set to 1. If the rounded value is greater than 2^31 - 1 the +result is 0x7FFFFFFF and VXCVI is set to 1. If the rounded value is less than +-2^31, the result is set to 0x80000000 and VXCVI is set to 1. If the rounded +result is inexact then XX is set to 1. + +@smallexample +vector unsigned int __builtin_vsx_xvcvdpuxws (vector double); +@end smallexample + +The @code{__builtin_vsx_xvcvdpuxws} converts the ith double precision floating +point vector element to a unsigned single-precision integer value using the +round to zero rounding mode. The single precision integer value is placed into +vector elements j and j+1 where j = i*2. If the source element is NaN the +result is set to 0x00000000 and VXCI is set to 1. If the source element is +SNaN then VXSNAN is also set to 1. If the rounded value is greater than +2^31 - 1 the result is 0xFFFFFFFF and VXCVI is set to 1. If the rounded value +is less than zero, the result is set to 0x00000000 and VXCVI is set to 1. If +the rounded result is inexact then XX is set to 1. + +@smallexample +vector unsigned long long int __builtin_vsx_xvcvdpuxds_uns (vector double); +@end smallexample + +The @code{__builtin_vsx_xvcvdpuxds_uns} converts the double precision floating +point vector element to a double precision unsigned integer value using the +round to zero rounding mode. If the source element is NaN the result is set +to 0x0000000000000000 and VXCI is set to 1. If the source element is SNaN +then VXSNAN is also set to 1. If the rounded value is greater than 2^63 - 1 +the result is 0xFFFFFFFFFFFFFFFF and VXCVI is set to 1. If the rounded value +is less than zero, the result is set to 0x0000000000000000 and VXCVI is set to +1. If the rounded result is inexact then XX is set to 1. + +@smallexample +vector double __builtin_vsx_xvcvspdp (vector float); +@end smallexample + +The @code{__builtin_vsx_xvcvspdp} converts single precision floating +point vector element to a double precision floating point value. Input element +at index 2*i is stored in the destination element i. + +@smallexample +vector float __builtin_vsx_xvcvdpsp (vector double); +@end smallexample + +The @code{__builtin_vsx_xvcvdpsp} converts the ith double precision floating +point vector element to a single-precision floating point value using the +rounding mode specified by RN. The single precision value is placed into +vector elements j and j+1 where j = i*2. The rounding mode, RN, is specified +by bits [62:63] of the FPSCR. + +@smallexample +vector unsigned int __builtin_vsx_xvcvspuxws (vector float); +@end smallexample + +The @code{__builtin_vsx_xvcvspuxws} converts the single precision floating +point vector element i to an unsigned single-precision integer value using +round to zero storing the result in element i. If the source element is NaN +the result is set to 0x00000000 and VXCI is set to 1. If the source element +is SNaN then VXSNAN is also set to 1. If the rounded value is greater than +2^31 - 1 the result is 0xFFFFFFFF and VXCVI is set to 1. If the rounded +value is less than -2^31, the result is set to 0x00000000 and VXCVI is set +to 1. If the rounded result is inexact then XX is set to 1. + +@smallexample +vector double __builtin_vsx_xvcvsxwdp (vector signed int); +@end smallexample + +The @code{__builtin_vsx_xvcvsxwdp} converts single precision integer value +to a double precision floating point value. Input element at index 2*i is +stored in the destination element i. + +@smallexample +vector double __builtin_vsx_xvcvuxddp_uns (vector unsigned long long); +@end smallexample + +The @code{__builtin_vsx_xvcvuxddp_uns} converts unsigned double-precision +integer value to a double precision floating point value. Input element +at index i is stored in the destination element i. + +@smallexample +vector double __builtin_vsx_xvcvuxwdp (vector unsigned int); +@end smallexample + +The @code{__builtin_vsx_xvcvuxwdp} converts single precision unsigned integer +value to a double precision floating point value. Input element at index 2*i +is stored in the destination element i. + @node Basic PowerPC Built-in Functions Available on ISA 2.07 @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07 diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c new file mode 100644 index 00000000000..91d16c3ba72 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c @@ -0,0 +1,233 @@ +/* { dg-do run { target { lp64 } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power7" } */ + +#define DEBUG 0 + +#if DEBUG +#include +#include +#endif + +void abort (void); + +int main () +{ + int i; + vector double vd_arg1, vd_result, vd_expected_result; + vector float vf_arg1, vf_result, vf_expected_result; + vector int vsi_arg1; + vector unsigned int vui_arg1; + vector int vsi_result, vsi_expected_result; + vector unsigned int vui_result, vui_expected_result; + vector signed long long int vsll_result, vsll_expected_result; + vector unsigned long long int vull_arg1; + vector unsigned long long int vull_result, vull_expected_result; + + /* VSX Vector Convert with round to zero Single-Precision floating point to + Single-Precision signed integer format using the round to zero mode. */ + + vf_arg1 = (vector float) {12345.98, 7654.321, -2.1234, + 9999999999956789012345678.9}; + vsi_result = __builtin_vsx_xvcvspsxws (vf_arg1); + vsi_expected_result = (vector signed int) {12345, 7654, -2, 0x7fffffff}; + + for (i = 0; i < 4; i++) + if (vsi_result[i] != vsi_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvspsxws: vsi_result[%d] = 0x%x, vsi_expected_result[%d] = 0x%x\n", + i, vsi_result[i], i, vsi_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert with round Single-Precision floating point to + Double-Precision signed integer format using the round to zero mode. */ + + vf_arg1 = (vector float) {12345.98, 7654.321, -2.1234, + 9999999999956789012345678.9}; + vsll_result = __builtin_vsx_xvcvspsxds (vf_arg1); + vsll_expected_result = (vector signed long long) {7654, 0x7fffffffffffffff}; + + for (i = 0; i < 2; i++) + if (vsll_result[i] != vsll_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvspsxds: vsll_result[%d] = 0x%llx, vsll_expected_result[%d] = 0x%llx\n", + i, vsll_result[i], i, vsll_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert with round Single-Precision floating point to + Double-Precision unsigned integer format using the round to zero mode. */ + + vf_arg1 = (vector float) {12345.98, 764.321, -2.1234, + 9999999999956789012345678.9}; + vull_result = __builtin_vsx_xvcvspuxds (vf_arg1); + vull_expected_result = (vector unsigned long long) {764, 0xffffffffffffffff}; + + for (i = 0; i < 2; i++) + if (vull_result[i] != vull_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvspuxds: vull_result[%d] = 0x%llx, vull_expected_result[%d] = 0x%llx\n", + i, vull_result[i], i, vull_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert with round Double-Precision floating point to + signed Single-Precision integer format using the round to zero mode. */ + + vd_arg1 = (vector double) {12345.987654321, -2.1234567890123456789}; + /* Each double-precision value, i, is converted to single precision integer + and placed in vector elements j and j+1 where j = i*2. The round to + zero rounding mode is used. */ + vsi_result = __builtin_vsx_xvcvdpsxws (vd_arg1); + vsi_expected_result = (vector int) {12345, 12345, -2, -2}; + + for (i = 0; i < 4; i++) + if (vsi_result[i] != vsi_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvdpsxws: vsi_result[%d] = %d, vsi_expected_result[%d] = %d\n", + i, vsi_result[i], i, vsi_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert with round Double-Precision floating point to + unsigned Single-Precision integer format using the round to zero mode. */ + + vd_arg1 = (vector double) {12345.987654321, -2.1234567890123456789}; + /* Each double-precision value, i, is converted to single precision integer + and placed in vector elements j and j+1 where j = i*2. The round to + zero rounding mode is used. */ + vui_result = __builtin_vsx_xvcvdpuxws (vd_arg1); + vui_expected_result = (vector unsigned int) {12345, 12345, 0, 0}; + + for (i = 0; i < 4; i++) + if (vui_result[i] != vui_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvdpuxws: vui_result[%d] = %d, vui_expected_result[%d] = %d\n", + i, vui_result[i], i, vui_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert with round Double-Precision floating point to + Double-Precision unsigned integer format using the round to zero mode. */ + + vd_arg1 = (vector double) {12345.987654321, -2.1234567890123456789}; + vull_result = __builtin_vsx_xvcvdpuxds_uns (vd_arg1); + vull_expected_result = (vector unsigned long long) {12345, 0}; + + for (i = 0; i < 2; i++) + if (vull_result[i] != vull_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvdpuxds_uns: vull_result[%d] = %lld, vull_expected_result[%d] = %lld\n", + i, vull_result[i], i, vull_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert Single-Precision floating point to Double-Precision + floating point */ + + vf_arg1 = (vector float) {12345.98, -2.0, 31.11, -55.5}; + vd_result = __builtin_vsx_xvcvspdp (vf_arg1); + vd_expected_result = (vector double) {-2.0, -55.5}; + + for (i = 0; i < 2; i++) + if (vd_result[i] != vd_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvspdp: vd_result[%d] = %f, vf_expected_result[%d] = %f\n", + i, vd_result[i], i, vd_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert with round Double-Precision float point format to + Single-Precision floating point format using the rounding mode specified + by the RN field of the FPSCR. */ + + vd_arg1 = (vector double) {12345.12345, -0.1234567890123456789}; + /* Each double-precision value, i, is converted to single precision and + placed in vector elements j and j+1 where j = i*2. */ + vf_result = __builtin_vsx_xvcvdpsp (vd_arg1); + vf_expected_result = (vector float) {12345.12345, 12345.12345, + -0.1234567890, -0.1234567890}; + + for (i = 0; i < 4; i++) + if (vf_result[i] != vf_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvdpsp: vf_result[%d] = %f, vf_expected_result[%d] = %f\n", + i, vf_result[i], i, vf_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert with round Single-Precision floating point to + Single-Precision unsigned integer format using the round to zero mode. */ + + vf_arg1 = (vector float) {12345.98, 7654.321, -2.1234, + 9999999999956789012345678.9}; + vui_result = __builtin_vsx_xvcvspuxws (vf_arg1); + vui_expected_result = (vector unsigned int) {12345, 7654, 0x0, 0xffffffff}; + + for (i = 0; i < 4; i++) + if (vui_result[i] != vui_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvspuxws: vui_result[%d] = 0x%x, vui_expected_result[%d] = 0x%x\n", + i, vui_result[i], i, vui_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert Signed integer word to Double-Precision floating point + format. */ + + vsi_arg1 = (vector int) {2345, 98, -2, -55}; + vd_result = __builtin_vsx_xvcvsxwdp (vsi_arg1); + vd_expected_result = (vector double) {98.0, -55.0}; + + for (i = 0; i < 2; i++) + if (vd_result[i] != vd_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvsxwdp: vd_result[%d] = %f, vd_expected_result[%d] = %f\n", + i, vd_result[i], i, vd_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert with round unsigned Double-Word integer to + Double-Precision floating point format. */ + + vull_arg1 = (vector unsigned long long) {12398, 22255}; + vd_result = __builtin_vsx_xvcvuxddp_uns (vull_arg1); + vd_expected_result = (vector double) {12398.0, 22255.0}; + + for (i = 0; i < 2; i++) + if (vd_result[i] != vd_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvuxddp_uns: vd_result[%d] = %f, vd_expected_result[%d] = %f\n", + i, vd_result[i], i, vd_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Convert unsigned Single-Precision integer to Double-Precision + floating point format. */ + + vui_arg1 = (vector unsigned int) {12398, 22255, 345, 87}; + vd_result = __builtin_vsx_xvcvuxwdp (vui_arg1); + vd_expected_result = (vector double) {22255.0, 87.0}; + + for (i = 0; i < 2; i++) + if (vd_result[i] != vd_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcvuxwdp: vd_result[%d] = %f, vd_expected_result[%d] = %f\n", + i, vd_result[i], i, vd_expected_result[i]); +#else + abort(); +#endif + return 0; +} From patchwork Tue Feb 20 17:56:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carl Love X-Patchwork-Id: 203732 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp573782dyc; Tue, 20 Feb 2024 10:04:02 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUKy4WquTlrZUSYv6fkp28wyALDHKCSzX1EHedBP3FmYTSepBujZ5h+1uS/JoEIi/4ISuKu7rtxLuymxw27wjZjoP0alg== X-Google-Smtp-Source: AGHT+IGZqtEsKwzghgAmOVFsMiJ7V0P/5UDs4HZzgaPHPYMLDekV9WLtdrTc8NEdxJK64xmBj8Ff X-Received: by 2002:ad4:5f0a:0:b0:68c:933c:e7f9 with SMTP id fo10-20020ad45f0a000000b0068c933ce7f9mr23897199qvb.17.1708452221408; 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Tue, 20 Feb 2024 17:56:28 +0000 (GMT) Message-ID: Date: Tue, 20 Feb 2024 09:56:28 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 03/11] rs6000, remove duplicated built-ins Content-Language: en-US To: gcc-patches@gcc.gnu.org, "bergner@linux.ibm.com" , Segher Boessenkool , "Kewen.Lin" References: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> From: Carl Love In-Reply-To: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: gJfYeVNvGDseRXsTMCvFwIimlIhVMpmF X-Proofpoint-ORIG-GUID: gJfYeVNvGDseRXsTMCvFwIimlIhVMpmF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 spamscore=0 suspectscore=0 mlxscore=0 adultscore=0 phishscore=0 bulkscore=0 malwarescore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402200128 X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791441996300130285 X-GMAIL-MSGID: 1791441996300130285 GCC maintainers: There are a number of undocumented built-ins that are duplicates of other documented built-ins. This patch removes the duplicates so users will only use the documented built-in. The patch has been tested on Power 10 with no regressions. Please let me know if this patch is acceptable for mainline. Thanks. Carl ----------------------------------------------------- rs6000, remove duplicated built-ins The following undocumented built-ins are same as existing documented overloaded builtins. const vf __builtin_vsx_xxmrghw (vf, vf); same as vf __builtin_vec_mergeh (vf, vf); (overloaded vec_mergeh) const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi); same as vsi __builtin_vec_mergeh (vsi, vsi); (overloaded vec_mergeh) const vf __builtin_vsx_xxmrglw (vf, vf); same as vf __builtin_vec_mergel (vf, vf); (overloaded vec_mergel) const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi); same as vsi __builtin_vec_mergel (vsi, vsi); (overloaded vec_mergel) const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc); same as vsc __builtin_vec_sel (vsc, vsc, vuc); (overloaded vec_sel) const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc); same as vuc __builtin_vec_sel (vuc, vuc, vuc); (overloaded vec_sel) const vd __builtin_vsx_xxsel_2df (vd, vd, vd); same as vd __builtin_vec_sel (vd, vd, vull); (overloaded vec_sel) const vsll __builtin_vsx_xxsel_2di (vsll, vsll, vsll); same as vsll __builtin_vec_sel (vsll, vsll, vsll); (overloaded vec_sel) const vull __builtin_vsx_xxsel_2di_uns (vull, vull, vull); same as vull __builtin_vec_sel (vull, vull, vsll); (overloaded vec_sel) const vf __builtin_vsx_xxsel_4sf (vf, vf, vf); same as vf __builtin_vec_sel (vf, vf, vsi) (overloaded vec_sel) const vsi __builtin_vsx_xxsel_4si (vsi, vsi, vsi); same as vsi __builtin_vec_sel (vsi, vsi, vbi); (overloaded vec_sel) const vui __builtin_vsx_xxsel_4si_uns (vui, vui, vui); same as vui __builtin_vec_sel (vui, vui, vui); (overloaded vec_sel) const vss __builtin_vsx_xxsel_8hi (vss, vss, vss); same as vss __builtin_vec_sel (vss, vss, vbs); (overloaded vec_sel) const vus __builtin_vsx_xxsel_8hi_uns (vus, vus, vus); same as vus __builtin_vec_sel (vus, vus, vus); (overloaded vec_sel) This patch removed the duplicate built-in definitions so only the documented built-ins will be available for use. The case statements in rs6000_gimple_fold_builtin that ar no longer needed are also removed. gcc/ChangeLog: * config/rs6000/rs6000-builtins.def (__builtin_vsx_xxmrghw, __builtin_vsx_xxmrghw_4si, __builtin_vsx_xxmrglw, __builtin_vsx_xxmrglw_4si, __builtin_vsx_xxsel_16qi, __builtin_vsx_xxsel_16qi_uns, __builtin_vsx_xxsel_2df, __builtin_vsx_xxsel_2di, __builtin_vsx_xxsel_2di_uns, __builtin_vsx_xxsel_4sf, __builtin_vsx_xxsel_4si, __builtin_vsx_xxsel_4si_uns, __builtin_vsx_xxsel_8hi, __builtin_vsx_xxsel_8hi_uns): Removed built-in definition. * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): remove case entries RS6000_BIF_XXMRGLW_4SI, RS6000_BIF_XXMRGLW_4SF, RS6000_BIF_XXMRGHW_4SI, RS6000_BIF_XXMRGHW_4SF. gcc/testsuite/ChangeLog: * gcc.target/powerpc/vsx-builtin-3.c (__builtin_vsx_xxsel_4si, __builtin_vsx_xxsel_8hi, __builtin_vsx_xxsel_16qi, __builtin_vsx_xxsel_4sf, __builtin_vsx_xxsel_2df): Remove test cases for removed built-ins. --- gcc/config/rs6000/rs6000-builtin.cc | 4 -- gcc/config/rs6000/rs6000-builtins.def | 42 ------------------- .../gcc.target/powerpc/vsx-builtin-3.c | 6 --- 3 files changed, 52 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 6698274031b..e436cbe4935 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -2110,20 +2110,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) /* vec_mergel (integrals). */ case RS6000_BIF_VMRGLH: case RS6000_BIF_VMRGLW: - case RS6000_BIF_XXMRGLW_4SI: case RS6000_BIF_VMRGLB: case RS6000_BIF_VEC_MERGEL_V2DI: - case RS6000_BIF_XXMRGLW_4SF: case RS6000_BIF_VEC_MERGEL_V2DF: fold_mergehl_helper (gsi, stmt, 1); return true; /* vec_mergeh (integrals). */ case RS6000_BIF_VMRGHH: case RS6000_BIF_VMRGHW: - case RS6000_BIF_XXMRGHW_4SI: case RS6000_BIF_VMRGHB: case RS6000_BIF_VEC_MERGEH_V2DI: - case RS6000_BIF_XXMRGHW_4SF: case RS6000_BIF_VEC_MERGEH_V2DF: fold_mergehl_helper (gsi, stmt, 0); return true; diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index fd316f629e5..96d095da2cb 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -1925,18 +1925,6 @@ const signed int __builtin_vsx_xvtsqrtsp_fg (vf); XVTSQRTSP_FG vsx_tsqrtv4sf2_fg {} - const vf __builtin_vsx_xxmrghw (vf, vf); - XXMRGHW_4SF vsx_xxmrghw_v4sf {} - - const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi); - XXMRGHW_4SI vsx_xxmrghw_v4si {} - - const vf __builtin_vsx_xxmrglw (vf, vf); - XXMRGLW_4SF vsx_xxmrglw_v4sf {} - - const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi); - XXMRGLW_4SI vsx_xxmrglw_v4si {} - const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<2>); XXPERMDI_16QI vsx_xxpermdi_v16qi {} @@ -1958,42 +1946,12 @@ const vss __builtin_vsx_xxpermdi_8hi (vss, vss, const int<2>); XXPERMDI_8HI vsx_xxpermdi_v8hi {} - const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc); - XXSEL_16QI vector_select_v16qi {} - - const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc); - XXSEL_16QI_UNS vector_select_v16qi_uns {} - const vsq __builtin_vsx_xxsel_1ti (vsq, vsq, vsq); XXSEL_1TI vector_select_v1ti {} const vsq __builtin_vsx_xxsel_1ti_uns (vsq, vsq, vsq); XXSEL_1TI_UNS vector_select_v1ti_uns {} - const vd __builtin_vsx_xxsel_2df (vd, vd, vd); - XXSEL_2DF vector_select_v2df {} - - const vsll __builtin_vsx_xxsel_2di (vsll, vsll, vsll); - XXSEL_2DI vector_select_v2di {} - - const vull __builtin_vsx_xxsel_2di_uns (vull, vull, vull); - XXSEL_2DI_UNS vector_select_v2di_uns {} - - const vf __builtin_vsx_xxsel_4sf (vf, vf, vf); - XXSEL_4SF vector_select_v4sf {} - - const vsi __builtin_vsx_xxsel_4si (vsi, vsi, vsi); - XXSEL_4SI vector_select_v4si {} - - const vui __builtin_vsx_xxsel_4si_uns (vui, vui, vui); - XXSEL_4SI_UNS vector_select_v4si_uns {} - - const vss __builtin_vsx_xxsel_8hi (vss, vss, vss); - XXSEL_8HI vector_select_v8hi {} - - const vus __builtin_vsx_xxsel_8hi_uns (vus, vus, vus); - XXSEL_8HI_UNS vector_select_v8hi_uns {} - const vsc __builtin_vsx_xxsldwi_16qi (vsc, vsc, const int<2>); XXSLDWI_16QI vsx_xxsldwi_v16qi {} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c index ff875c55304..10bf39b89ed 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c @@ -61,12 +61,6 @@ int do_sel(void) { int i = 0; - si[i][0] = __builtin_vsx_xxsel_4si (si[i][1], si[i][2], si[i][3]); i++; - ss[i][0] = __builtin_vsx_xxsel_8hi (ss[i][1], ss[i][2], ss[i][3]); i++; - sc[i][0] = __builtin_vsx_xxsel_16qi (sc[i][1], sc[i][2], sc[i][3]); i++; - f[i][0] = __builtin_vsx_xxsel_4sf (f[i][1], f[i][2], f[i][3]); i++; - d[i][0] = __builtin_vsx_xxsel_2df (d[i][1], d[i][2], d[i][3]); i++; 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Content-Language: en-US To: gcc-patches@gcc.gnu.org, "bergner@linux.ibm.com" , Segher Boessenkool , "Kewen.Lin" References: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> From: Carl Love In-Reply-To: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: KewKT0F8h8it-ngqsEy0F1cJxWGSPULD X-Proofpoint-GUID: KewKT0F8h8it-ngqsEy0F1cJxWGSPULD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 adultscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 malwarescore=0 impostorscore=0 mlxlogscore=657 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402200129 X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791441814927967842 X-GMAIL-MSGID: 1791441814927967842 GCC maintainers: The patch expands an existing comment to document that the duplicates are covered by an overloaded built-in. I am wondering if we should just go ahead and remove the duplicates? The patch has been tested on Power 10 with no regressions. Please let me know if this patch is acceptable for mainline. Thanks. Carl ----------------------------------------------------- rs6000, Update comment for the __builtin_vsx_vper* built-ins. There is a comment about the __builtin_vsx_vper* built-ins being duplicates of the __builtin_altivec_* built-ins. The note says we should consider deprecation/removeal of the __builtin_vsx_vper*. Add a note that the _builtin_vsx_vper* built-ins are covered by the overloaded vec_perm built-ins which use the __builtin_altivec_* built-in definitions. gcc/ChangeLog: * config/rs6000/rs6000-builtins.def ( __builtin_vsx_vperm_*): Add comment to existing comment about the built-ins. --- gcc/config/rs6000/rs6000-builtins.def | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 96d095da2cb..4c95429f137 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -1556,6 +1556,14 @@ ; These are duplicates of __builtin_altivec_* counterparts, and are being ; kept for backwards compatibility. The reason for their existence is ; unclear. TODO: Consider deprecation/removal at some point. +; Note, __builtin_vsx_vperm_16qi, __builtin_vsx_vperm_16qi_uns, +; __builtin_vsx_vperm_1ti, __builtin_vsx_vperm_v1ti_uns, +; __builtin_vsx_vperm_2df, __builtin_vsx_vperm_2di, __builtin_vsx_vperm_2di, +; __builtin_vsx_vperm_2di_uns, __builtin_vsx_vperm_4sf, +; __builtin_vsx_vperm_4si, __builtin_vsx_vperm_4si_uns, +; __builtin_vsx_vperm_8hi, __builtin_altivec_vperm_8hi_uns +; are all covered by the overloaded vec_perm built-in which uses the +; __builtin_altivec_* built-in definitions. const vsc __builtin_vsx_vperm_16qi (vsc, vsc, vuc); VPERM_16QI_X altivec_vperm_v16qi {} From patchwork Tue Feb 20 17:56:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carl Love X-Patchwork-Id: 203719 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp568494dyc; Tue, 20 Feb 2024 09:58:28 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXfTyJbKgOa1WN9RR+680fWeXETf7xBiLT7q8rhp3bMv0pVjQAUNwX0qsHtl4ze4Xj2kFpHsweWPrjLg1+oqNaAma+W9A== X-Google-Smtp-Source: AGHT+IGLFq6e7GCU1vYcRsfggz9A0wF58W3AjT4I1vDxJZekG/suGJeVtMukGp0NKNEOCQNZ+QaB X-Received: by 2002:a05:6808:1296:b0:3c0:3ce5:a505 with SMTP id a22-20020a056808129600b003c03ce5a505mr20121640oiw.40.1708451907978; Tue, 20 Feb 2024 09:58:27 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708451907; cv=pass; d=google.com; s=arc-20160816; b=tHwnwqs71d1K9LQ9aZGPJz2DRoYbBCEVGNrsHrNe1lVvDX+2EB2lerNPF2zU7gK5zQ sXtuJkmWe6X2O4NMW5wMBjzo0QXo/kQGNSvYMUcc6O2HHKU/gIP+e/OqX+YTOejD1Tsi XoP3tfcVrUuAihVa50fr1G5Ot5b4n0V5zgukRVeqloPfxiUj6Dcl/xOcoeGpso3/Vtbd QQ4mkGSyYfzzICbZrRhiLazTy5l4a26M/mxh53ncyUGp2znktpIdtLR87odrt10+l018 A5mCFZ98Dd+9Qkwt7OGergBaRG6kc1aEv+dcFDmISGivvxlfLdyjuOZ/RWvatgnNqdxW fXUQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :in-reply-to:from:references:to:content-language:subject:user-agent :mime-version:date:message-id:dkim-signature:arc-filter:dmarc-filter :delivered-to; bh=aE3aE+uhzT9Hwe76lTg9/qOdD5RWMD88/DzjZYC4Bn8=; fh=U4Oxu8wVnBRVc+7Z2YdxYnccRaEmehXwfih2gvmyKwI=; b=IqXA//lMMuodOqsSFBsIhFmAOlhzohaS1YjRoojWj7rd6zToICx0X8qRLQHiycBlJX JCDlAexV06SgLQrdUQ2innXqLF036TOP9a/5jKGnOgXb7JnH6CuV86mT9ySQJCTY0YOy 72vEeyc3UQPIz1eEsg7TMgrVnTApoISW4xBYfhQ5bMfungC8yenteBkuJN2Yt0NYja10 l06vzafUxhHLmMJYm9HPN2CCz3PURESGx+tadw2mrSzlm0h7eojTFiaH3SmSddx3LIeY pCsXsHnXCvTSi/0XkPRVm9uyVUqNa79xXe5lAoq9vWHoYyGLX0Jv9mGcHztTcZFDvAX3 H7Mw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b="C+/ku8x3"; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. 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Tue, 20 Feb 2024 17:56:58 +0000 (GMT) Message-ID: Date: Tue, 20 Feb 2024 09:56:58 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 05/11] rs6000, __builtin_vsx_xvneg[sp,dp] add documentation, and test cases Content-Language: en-US To: gcc-patches@gcc.gnu.org, "bergner@linux.ibm.com" , Segher Boessenkool , "Kewen.Lin" References: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> From: Carl Love In-Reply-To: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: p-16WFGIXnqvQLJ0ClzK4PvzSrhPNtge X-Proofpoint-GUID: p-16WFGIXnqvQLJ0ClzK4PvzSrhPNtge X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402200128 X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791441667706673616 X-GMAIL-MSGID: 1791441667706673616 GCC maintainers: The patch adds documentation and test cases for the __builtin_vsx_xvnegsp, __builtin_vsx_xvnegdp built-ins. The patch has been tested on Power 10 with no regressions. Please let me know if this patch is acceptable for mainline. Thanks. Carl ------------------------------------------------------------ rs6000, __builtin_vsx_xvneg[sp,dp] add documentation and test cases Add documentation to the extend.texi file for the two built-ins __builtin_vsx_xvnegsp, __builtin_vsx_xvnegdp. Add test cases for the two built-ins. gcc/ChangeLog: * doc/extend.texi (__builtin_vsx_xvnegsp, __builtin_vsx_xvnegdp): Add documentation. gcc/testsuite/ChangeLog: * gcc.target/powerpc/vsx-builtin-runnable-2.c: New test case. --- gcc/doc/extend.texi | 13 +++++ .../powerpc/vsx-builtin-runnable-2.c | 51 +++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 583b1d890bf..83eed9e334b 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21495,6 +21495,19 @@ The @code{__builtin_vsx_xvcvuxwdp} converts single precision unsigned integer value to a double precision floating point value. Input element at index 2*i is stored in the destination element i. +@smallexample +vector float __builtin_vsx_xvnegsp (vector float); +vector double __builtin_vsx_xvnegdp (vector double); +@end smallexample + +The @code{__builtin_vsx_xvnegsp} and @code{__builtin_vsx_xvnegdp} negate each +vector element. + +@smallexample +vector __int128 __builtin_vsx_xxpermdi_1ti (vector __int128, vector __int128, +const int); + +@end smallexample @node Basic PowerPC Built-in Functions Available on ISA 2.07 @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07 diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c new file mode 100644 index 00000000000..7906a8e01d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c @@ -0,0 +1,51 @@ +/* { dg-do run { target { lp64 } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power7" } */ + +#define DEBUG 0 + +#if DEBUG +#include +#include +#endif + +void abort (void); + +int main () +{ + int i; + vector double vd_arg1, vd_result, vd_expected_result; + vector float vf_arg1, vf_result, vf_expected_result; + + /* VSX Vector Negate Single-Precision. */ + + vf_arg1 = (vector float) {-1.0, 12345.98, -2.1234, 238.9}; + vf_result = __builtin_vsx_xvnegsp (vf_arg1); + vf_expected_result = (vector float) {1.0, -12345.98, 2.1234, -238.9}; + + for (i = 0; i < 4; i++) + if (vf_result[i] != vf_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvnegsp: vf_result[%d] = %f, vf_expected_result[%d] = %f\n", + i, vf_result[i], i, vf_expected_result[i]); +#else + abort(); +#endif + + /* VSX Vector Negate Double-Precision. */ + + vd_arg1 = (vector double) {12345.98, -2.1234}; + vd_result = __builtin_vsx_xvnegdp (vd_arg1); + vd_expected_result = (vector double) {-12345.98, 2.1234}; + + for (i = 0; i < 2; i++) + if (vd_result[i] != vd_expected_result[i]) +#if DEBUG + printf("ERROR, __builtin_vsx_xvnegdp: vd_result[%d] = %f, vd_expected_result[%d] = %f\n", + i, vd_result[i], i, vd_expected_result[i]); +#else + abort(); +#endif + + return 0; +} From patchwork Tue Feb 20 17:57:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carl Love X-Patchwork-Id: 203720 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp568561dyc; Tue, 20 Feb 2024 09:58:39 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWYKsu2F01uoyL2j00y/9qtOpag++fo05/pZvmQzdZM7+1ZmQD5g5vKJ5Ec1bnpXAc8gcBO6UqhofgA7AwPkN3AAM7eAg== X-Google-Smtp-Source: AGHT+IEa40YIMcyVKBtQGbRSexWKzeAaZLwMSjcikLPe0rR0GLWPzuybYfW02msH27j1hdMMxrFl X-Received: by 2002:ac8:59c5:0:b0:42e:2493:5bb1 with SMTP id f5-20020ac859c5000000b0042e24935bb1mr3824604qtf.17.1708451919095; Tue, 20 Feb 2024 09:58:39 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708451919; cv=pass; d=google.com; s=arc-20160816; b=iLfxOF8+cBJKox0TX8CYOQoam257deDF7wsmvQS3jL3T564028ICKbC23zaUwVy2Bg ZjyuCAc32043kFeB/WB3CGKthI/T2rJM01rtbcZXvkxzYesyeEp1dgqh0hMHsnJMRwQj P1AAXRYM8DFbP5lz3u3cnMK6cfE6w9jhPP/5K8GzbrWWvkAPzvuFCi2cJYL2KgMW/yD9 M0qh7tJYzULKr5FuUUIg5qSszGolKOMCNy9VNGFkmlyHSae3HvrTxWcudNKTbI0b9MMf nzo7XAkSkR9Ut3HeSqEDNXDRvUjn0wcCM6MWYyLgGqRyW0+Uc6k1nExjBZzX+CBiCDB8 /Lyg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :in-reply-to:from:references:to:content-language:subject:user-agent :mime-version:date:message-id:dkim-signature:arc-filter:dmarc-filter :delivered-to; bh=vOVEL5/Qaim04ihz55/Bj1Zy3uADekHArFQy0V/OFCw=; fh=U4Oxu8wVnBRVc+7Z2YdxYnccRaEmehXwfih2gvmyKwI=; b=oXYcND1rPN/GoOTC67nFvsO+Jlw0weQ7nw0XzJ6KDzeiL4ujbm/rDWvWzXwmNwSn3m 4+jrN2Dve2Hl0cUw2TPuwk9+zAhkX/zpgjtu2EXHDQfdK/+JMpgXO57WaXjOB5gb5t8R L4YMQQSlB94z3ths5p/yKdoRlEkhzZRGpyiI/NObM5VzRmJUAVVGiFVosONLcZkDXLp/ 9LTvG6Erhtl1KPqHBFRZ0s1qYr5LKID0XjiVpoiTiamEno9TfW0QnC30kDeUZjm74VS+ DBWzC/lHK2yBoTIaOh+U0pdy4zK0y0Z+DpCR6iN0uTLV5diNNvBFG3Nz+cIefz0xd8oN 1s8A==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b="jbCf1/5a"; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. 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Tue, 20 Feb 2024 17:57:12 +0000 (GMT) Message-ID: <2618b501-35e5-4ea2-9425-245dd0df0b3c@linux.ibm.com> Date: Tue, 20 Feb 2024 09:57:12 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 06/11] rs6000, __builtin_vsx_xxpermdi_1ti add documentation, and test case Content-Language: en-US To: gcc-patches@gcc.gnu.org, "bergner@linux.ibm.com" , Segher Boessenkool , "Kewen.Lin" References: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> From: Carl Love In-Reply-To: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ZNRFwgIpSA9bLkuOriNEVPzE1nkuPbRn X-Proofpoint-GUID: ZNRFwgIpSA9bLkuOriNEVPzE1nkuPbRn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 phishscore=0 mlxscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402200129 X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791441679463835897 X-GMAIL-MSGID: 1791441679463835897 GCC maintainers: The patch adds documentation and test case for the __builtin_vsx_xxpermdi_1ti built-in. The patch has been tested on Power 10 with no regressions. Please let me know if this patch is acceptable for mainline. Thanks. Carl ------------------------------------------------------------ rs6000, __builtin_vsx_xxpermdi_1ti add documentation and test case Add documentation to the extend.texi file for the __builtin_vsx_xxpermdi_1ti built-in. Add test cases for the __builtin_vsx_xxpermdi_1ti built-in. gcc/ChangeLog: * doc/extend.texi (__builtin_vsx_xxpermdi_1ti): Add documentation. gcc/testsuite/ChangeLog: * gcc.target/powerpc/vsx-builtin-runnable-3.c: New test case. --- gcc/doc/extend.texi | 7 +++ .../powerpc/vsx-builtin-runnable-3.c | 48 +++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 83eed9e334b..22f67ebab31 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21508,6 +21508,13 @@ vector __int128 __builtin_vsx_xxpermdi_1ti (vector __int128, vector __int128, const int); @end smallexample + +The @code{__builtin_vsx_xxpermdi_1ti} Let srcA[127:0] be the 128-bit first +argument and srcB[127:0] be the 128-bit second argument. Let sel[1:0] be the +least significant bits of the const int argument (third input argument). The +result bits [127:64] is srcB[127:64] if sel[1] = 0, srcB[63:0] otherwise. The +result bits [63:0] is srcA[127:64] if sel[0] = 0, srcA[63:0] otherwise. + @node Basic PowerPC Built-in Functions Available on ISA 2.07 @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07 diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c new file mode 100644 index 00000000000..ba287597cec --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c @@ -0,0 +1,48 @@ +/* { dg-do run { target { lp64 } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power7" } */ + +#include + +#define DEBUG 0 + +#if DEBUG +#include +#include +#endif + +void abort (void); + +int main () +{ + int i; + + vector signed __int128 vsq_arg1, vsq_arg2, vsq_result, vsq_expected_result; + + vsq_arg1[0] = (__int128) 0xFFFF0000FFFF0000; + vsq_arg1[0] = vsq_arg1[0] << 64 | (__int128) 0xFFFF0000FFFF; + vsq_arg2[0] = (__int128) 0x1100110011001100; + vsq_arg2[0] = (vsq_arg2[0] << 64) | (__int128) 0x1111000011110000; + + vsq_expected_result[0] = (__int128) 0x1111000011110000; + vsq_expected_result[0] = (vsq_expected_result[0] << 64) + | (__int128) 0xFFFF0000FFFF0000; + + vsq_result = __builtin_vsx_xxpermdi_1ti (vsq_arg1, vsq_arg2, 2); + + if (vsq_result[0] != vsq_expected_result[0]) + { +#if DEBUG + printf("ERROR, __builtin_vsx_xxpermdi_1ti: vsq_result = 0x%016llx %016llx\n", + (unsigned long long) (vsq_result[0] >> 64), + (unsigned long long) vsq_result[0]); + printf(" vsq_expected_resultd = 0x%016llx %016llx\n", + (unsigned long long)(vsq_expected_result[0] >> 64), + (unsigned long long) vsq_expected_result[0]); +#else + abort(); +#endif + } + + return 0; +} From patchwork Tue Feb 20 17:57:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carl Love X-Patchwork-Id: 203731 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp573715dyc; Tue, 20 Feb 2024 10:03:56 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCX2/QzLMGCuADzEwV30psv/vSUWQW5QK6saMKRIXAdKjY6WtuTDLR3shM/8TWqIxrkb2MbWUqReCbRfPTmk1AdlMvKqWA== X-Google-Smtp-Source: AGHT+IEarx+qVKasyx3gh91AyliavNHwhuDIkPxleJqubV1iEJVgBErU7HAK4xu2sdbf4yDBOQH9 X-Received: by 2002:a05:620a:4143:b0:785:da38:6aca with SMTP id k3-20020a05620a414300b00785da386acamr20451000qko.68.1708452236549; Tue, 20 Feb 2024 10:03:56 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708452236; cv=pass; d=google.com; s=arc-20160816; b=DLPUtpfO2yXa+5hvml1wguH52owNdGUUZ18zQL2LJdmRdk+XnP2lxMNTbFocbvB8Wm qdS+vxFw8q5YUPUiVMkM0QjWGEiTfguWnQuA+ZxVWSCHkATfrET7AWzS/ZWn2/kWPOX6 4jU91LbWzg5YZMdlBAe8jHK8P/dxgfPUA0QOXtNfKAPtgF0h0WGn34TgyefoOVJImvhi H6GLpFmkSSvm6Wj/zM0OY8h+552lbJjOeMbePoYZPvCT/eLE47ukho9E1VXz66EuvkoQ e9WJp3/gMSRQ1YvTg1g4J+eRxq6xuIbsMTt7+tB2PcRgT/VtbK36hWmv8OsD7ukPKRcF N3Mg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :in-reply-to:from:references:to:content-language:subject:user-agent :mime-version:date:message-id:dkim-signature:arc-filter:dmarc-filter :delivered-to; bh=dBOm/Yjg1lA2eYLY2miYgpVCDaxBg9sYakcXR99IaOk=; fh=U4Oxu8wVnBRVc+7Z2YdxYnccRaEmehXwfih2gvmyKwI=; b=vYfUtRU9/aX4Anmrnqrwk8kfOYfxQxHsy50IiS4Ep42cSbaXhQ6AA7odg2O5wDpKZn VtxI3TQ8j2PE+BK5H0uGmoFaYURWHpmrUUspQQm4L1gkT+w+tqEoedaeV9NWgnjMQObY 6mkhH9GeNjJmtwKYv9DCCAf/PKQQJINmNSyuB5RKQ14lFbT0+Au9J+RV95YfXME8XNx3 f5dCtn4e9zw5+H83gYIF5eBgtUIVsrac5/SpCEIKpV5wUtqqwywZrDk9nB74XV+LAew3 kj9V4gKtEBKkzyCsWKEV2jGEkRye5uxM0U9vTB7iLa71xjBkDShkH6R4ZkfClUjdQbjj v+1w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=rl5vzLvL; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. 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Tue, 20 Feb 2024 17:57:27 +0000 (GMT) Message-ID: <91b2efe8-76d6-4aa8-8d67-8c8512e1dd81@linux.ibm.com> Date: Tue, 20 Feb 2024 09:57:27 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 07/11] rs6000, __builtin_vsx_xvcmpeq[sp, dp, sp_p] add, documentation and test case Content-Language: en-US To: gcc-patches@gcc.gnu.org, "bergner@linux.ibm.com" , Segher Boessenkool , "Kewen.Lin" References: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> From: Carl Love In-Reply-To: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: mSytaPFbglihn-DqYldVBDHIgUtnQhbh X-Proofpoint-GUID: mSytaPFbglihn-DqYldVBDHIgUtnQhbh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 adultscore=0 priorityscore=1501 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402200129 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791442012373719405 X-GMAIL-MSGID: 1791442012373719405 GCC maintainers: The patch adds documentation and test case for the __builtin_vsx_xvcmpeq[sp, dp, sp_p] built-ins. The patch has been tested on Power 10 with no regressions. Please let me know if this patch is acceptable for mainline. Thanks. Carl ------------------------------------------------------------ rs6000, __builtin_vsx_xvcmpeq[sp, dp, sp_p] add documentation and test case Add a test case for the __builtin_vsx_xvcmpeqsp_p built-in. Add documentation for the __builtin_vsx_xvcmpeqsp_p, __builtin_vsx_xvcmpeqdp, and __builtin_vsx_xvcmpeqsp builtins. gcc/ChangeLog: * doc/extend.texi (__builtin_vsx_xvcmpeqsp_p, __builtin_vsx_xvcmpeqdp, __builtin_vsx_xvcmpeqsp): Add documentation. gcc/testsuite/ChangeLog: * gcc.target/powerpc/vsx-builtin-runnable-4.c: New test case. --- gcc/doc/extend.texi | 23 +++ .../powerpc/vsx-builtin-runnable-4.c | 135 ++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 22f67ebab31..87fd30bfa9e 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -22700,6 +22700,18 @@ vectors of their defined type. The corresponding result element is set to all ones if the two argument elements are less than or equal and all zeros otherwise. +@smallexample +const vf __builtin_vsx_xvcmpeqsp (vf, vf); +const vd __builtin_vsx_xvcmpeqdp (vd, vd); +@end smallexample + +The builti-ins @code{__builtin_vsx_xvcmpeqdp} and +@code{__builtin_vsx_xvcmpeqdp} compare two floating point vectors and return +a vector. If the corresponding elements are equal then the corresponding +vector element of the result is set to all ones, it is set to all zeros +otherwise. + + @node PowerPC AltiVec Built-in Functions Available on ISA 2.07 @subsubsection PowerPC AltiVec Built-in Functions Available on ISA 2.07 @@ -23989,6 +24001,17 @@ is larger than 128 bits, the result is undefined. The result is the modulo result of dividing the first input by the second input. +@smallexample +const signed int __builtin_vsx_xvcmpeqdp_p (signed int, vd, vd); +@end smallexample + +The first argument of the builti-in @code{__builtin_vsx_xvcmpeqdp_p} is an +integer in the range of 0 to 1. The second and third arguments are floating +point vectors to be compared. The result is 1 if the first argument is a 1 +and one or more of the corresponding vector elements are equal. The result is +1 if the first argument is 0 and all of the corresponding vector elements are +not equal. The result is zero otherwise. + The following builtins perform 128-bit vector comparisons. The @code{vec_all_xx}, @code{vec_any_xx}, and @code{vec_cmpxx}, where @code{xx} is one of the operations @code{eq, ne, gt, lt, ge, le} perform pairwise diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c new file mode 100644 index 00000000000..8ac07c7c807 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c @@ -0,0 +1,135 @@ +/* { dg-do run { target { power10_hw } } } */ +/* { dg-do link { target { ! power10_hw } } } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -save-temps" } */ +/* { dg-require-effective-target power10_ok } */ + +#define DEBUG 0 + +#if DEBUG +#include +#include +#endif + +void abort (void); + +int main () +{ + int i; + int result; + vector float vf_arg1, vf_arg2; + vector double d_arg1, d_arg2; + + /* Compare vectors with one equal element, check + for all elements unequal, i.e. first arg is 1. */ + vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0}; + vf_arg2 = (vector float) {1.0, 3.0, 2.0, 8.0}; + result = __builtin_vsx_xvcmpeqsp_p (1, vf_arg1, vf_arg2); + +#if DEBUG + printf("result = 0x%x\n", (unsigned int) result); +#endif + + if (result != 1) + for (i = 0; i < 4; i++) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcmpeqsp_p 1: arg 1 = 1, varg3[%d] = %f, varg3[%d] = %f\n", + i, vf_arg1[i], i, vf_arg2[i]); +#else + abort(); +#endif + /* Compare vectors with one equal element, check + for all elements unequal, i.e. first arg is 0. */ + vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0}; + vf_arg2 = (vector float) {1.0, 3.0, 2.0, 8.0}; + result = __builtin_vsx_xvcmpeqsp_p (0, vf_arg1, vf_arg2); + +#if DEBUG + printf("result = 0x%x\n", (unsigned int) result); +#endif + + if (result != 0) + for (i = 0; i < 4; i++) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcmpeqsp_p 2: arg 1 = 0, varg3[%d] = %f, varg3[%d] = %f\n", + i, vf_arg1[i], i, vf_arg2[i]); +#else + abort(); +#endif + + /* Compare vectors with all unequal elements, check + for all elements unequal, i.e. first arg is 1. */ + vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0}; + vf_arg2 = (vector float) {8.0, 3.0, 2.0, 8.0}; + result = __builtin_vsx_xvcmpeqsp_p (1, vf_arg1, vf_arg2); + +#if DEBUG + printf("result = 0x%x\n", (unsigned int) result); +#endif + + if (result != 0) + for (i = 0; i < 4; i++) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcmpeqsp_p 3: arg 1 = 1, varg3[%d] = %f, varg3[%d] = %f\n", + i, vf_arg1[i], i, vf_arg2[i]); +#else + abort(); +#endif + + /* Compare vectors with all unequal elements, check + for all elements unequal, i.e. first arg is 0. */ + vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0}; + vf_arg2 = (vector float) {8.0, 3.0, 2.0, 8.0}; + result = __builtin_vsx_xvcmpeqsp_p (0, vf_arg1, vf_arg2); + +#if DEBUG + printf("result = 0x%x\n", (unsigned int) result); +#endif + + if (result != 1) + for (i = 0; i < 4; i++) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcmpeqsp_p 4: arg 1 = 0, varg3[%d] = %f, varg3[%d] = %f\n", + i, vf_arg1[i], i, vf_arg2[i]); +#else + abort(); +#endif + + /* Compare vectors with all equal elements, check + for all elements equal, i.e. first arg is 1. */ + vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0}; + vf_arg2 = (vector float) {1.0, 2.0, 3.0, 4.0}; + result = __builtin_vsx_xvcmpeqsp_p (1, vf_arg1, vf_arg2); + +#if DEBUG + printf("result = 0x%x\n", (unsigned int) result); +#endif + + if (result != 1) + for (i = 0; i < 4; i++) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcmpeqsp_p 5: arg 1 = 1, varg3[%d] = %f, varg3[%d] = %f\n", + i, vf_arg1[i], i, vf_arg2[i]); +#else + abort(); +#endif + + /* Compare vectors with all equal elements, check + for all elements unequal, i.e. first arg is 0. */ + vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0}; + vf_arg2 = (vector float) {1.0, 2.0, 3.0, 4.0}; + result = __builtin_vsx_xvcmpeqsp_p (0, vf_arg1, vf_arg2); + +#if DEBUG + printf("result = 0x%x\n", (unsigned int) result); +#endif + + if (result != 0) + for (i = 0; i < 4; i++) +#if DEBUG + printf("ERROR, __builtin_vsx_xvcmpeqsp_p 6: arg 0 = 1, varg3[%d] = %f, varg3[%d] = %f\n", + i, vf_arg1[i], i, vf_arg2[i]); +#else + abort(); +#endif + return 0; +} From patchwork Tue Feb 20 17:57:41 2024 Content-Type: text/plain; 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Tue, 20 Feb 2024 17:57:41 +0000 (GMT) Message-ID: <62e46788-a420-41c7-9441-3b7c4b97f7b3@linux.ibm.com> Date: Tue, 20 Feb 2024 09:57:41 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 08/11] rs6000, add tests and documentation for various, built-ins Content-Language: en-US To: gcc-patches@gcc.gnu.org, "bergner@linux.ibm.com" , Segher Boessenkool , "Kewen.Lin" References: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> From: Carl Love In-Reply-To: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: w_a2VZvk3-APPQzUW8RF00MOsvRQjdqL X-Proofpoint-GUID: w_a2VZvk3-APPQzUW8RF00MOsvRQjdqL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 mlxscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402200129 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791441942006274946 X-GMAIL-MSGID: 1791441942006274946 GCC maintainers: The patch adds documentation a number of built-ins. The patch has been tested on Power 10 with no regressions. Please let me know if this patch is acceptable for mainline. Thanks. Carl ------------------------------------------------------------ rs6000, add tests and documentation for various built-ins This patch adds a test case and documentation in extend.texi for the following built-ins: __builtin_altivec_fix_sfsi __builtin_altivec_fixuns_sfsi __builtin_altivec_float_sisf __builtin_altivec_uns_float_sisf __builtin_altivec_vrsqrtfp __builtin_altivec_mask_for_load __builtin_altivec_vsel_1ti __builtin_altivec_vsel_1ti_uns __builtin_vec_init_v16qi __builtin_vec_init_v4sf __builtin_vec_init_v4si __builtin_vec_init_v8hi __builtin_vec_set_v16qi __builtin_vec_set_v4sf __builtin_vec_set_v4si __builtin_vec_set_v8hi gcc/ChangeLog: * doc/extend.texi (__builtin_altivec_fix_sfsi, __builtin_altivec_fixuns_sfsi, __builtin_altivec_float_sisf, __builtin_altivec_uns_float_sisf, __builtin_altivec_vrsqrtfp, __builtin_altivec_mask_for_load, __builtin_altivec_vsel_1ti, __builtin_altivec_vsel_1ti_uns, __builtin_vec_init_v16qi, __builtin_vec_init_v4sf, __builtin_vec_init_v4si, __builtin_vec_init_v8hi, __builtin_vec_set_v16qi, __builtin_vec_set_v4sf, __builtin_vec_set_v4si, __builtin_vec_set_v8hi): Add documentation. gcc/testsuite/ChangeLog: * gcc.target/powerpc/altivec-38.c: New test case. --- gcc/doc/extend.texi | 98 ++++ gcc/testsuite/gcc.target/powerpc/altivec-38.c | 503 ++++++++++++++++++ 2 files changed, 601 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/altivec-38.c diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 87fd30bfa9e..89d0a1f77b0 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -22678,6 +22678,104 @@ if the VSX instruction set is available. The @samp{vec_vsx_ld} and @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. +@smallexample +vector signed int __builtin_altivec_fix_sfsi (vector float); +vector signed int __builtin_altivec_fixuns_sfsi (vector float); +vector float __builtin_altivec_float_sisf (vector int); +vector float __builtin_altivec_uns_float_sisf (vector int); +vector float __builtin_altivec_vrsqrtfp (vector float); +@end smallexample + +The @code{__builtin_altivec_fix_sfsi} converts a vector of single precision +floating point values to a vector of signed integers with round to zero. + +The @code{__builtin_altivec_fixuns_sfsi} converts a vector of single precision +floating point values to a vector of unsigned integers with round to zero. If +the rounded floating point value is less then 0 the result is 0 and VXCVI +is set to 1. + +The @code{__builtin_altivec_float_sisf} converts a vector of single precision +signed integers to a vector of floating point values using the rounding mode +specified by RN. + +The @code{__builtin_altivec_uns_float_sisf} converts a vector of single +precision unsigned integers to a vector of floating point values using the +rounding mode specified by RN. + +The @code{__builtin_altivec_vrsqrtfp} returns a vector of floating point +estimates of the reciprical square root of each floating point source vector +element. + +@smallexample +vector signed char test_altivec_mask_for_load (const void *); +@end smallexample + +The @code{__builtin_altivec_vrsqrtfp} returns a vector mask based on the +bottom four bits of the argument. Let X be the 32-byte value: +0x00 || 0x01 || 0x02 || ... || 0x1D || 0x1E || 0x1F. +Bytes sh to sh+15 are returned where sh is given by the least significant 4 +bit of the argument. See description of lvsl, lvsr instructions. + +@smallexample +vector signed __int128 __builtin_altivec_vsel_1ti (vector signed __int128, + vector signed __int128, + vector unsigned __int128); +vector unsigned __int128 + __builtin_altivec_vsel_1ti_uns (vector unsigned __int128, + vector unsigned __int128, + vector unsigned __int128) +@end smallexample + +Let the arguments of @code{__builtin_altivec_vsel_1ti} and +@code{__builtin_altivec_vsel_1ti_uns} be src1, src2, mask. The result is +given by (src1 & ~mask) | (src2 & mask). + +@smallexample +vector signed char +__builtin_vec_init_v16qi (signed char, signed char, signed char, signed char, + signed char, signed char, signed char, signed char, + signed char, signed char, signed char, signed char, + signed char, signed char, signed char, signed char); + +vector short int __builtin_vec_init_v8hi (short int, short int, short int, + short int, short int, short int, + short int, short int); +vector signed int __builtin_vec_init_v4si (signed int, signed int, signed int, + signed int); +vector float __builtin_vec_init_v4sf (float, float, float, float); +vector __int128 __builtin_vec_init_v1ti (signed __int128); +vector double __builtin_vec_init_v2df (double, double); +vector signed long long __builtin_vec_init_v2di (signed long long, + signed long long); +@end smallexample + +The builti-ins @code{__builtin_vec_init_v16qi}, @code{__builtin_vec_init_v8hi}, +@code{__builtin_vec_init_v4si}, @code{__builtin_vec_init_v4sf}, +@code{__builtin_vec_init_v1ti}, @code{__builtin_vec_init_v2df} and +@code{__builtin_vec_init_v2di} return a +vector corresponding to the argument type initialized with the value of the +arguments. + +@smallexample +vector signed char __builtin_vec_set_v16qi (vector signed char, signed char, + const int); +vector short int __builtin_vec_set_v8hi (vector short int, short int, + const int); +vector signed int __builtin_vec_set_v4si (vector signed int, signed int, + const int); +vector float __builtin_vec_set_v4sf (vector float, float, const int); +vector __int128 __builtin_vec_set_v1ti (vector __int128, __int128, const int); +vector double __builtin_vec_set_v2dfi (vector double, double, const int); +vector signed long long __builtin_vec_set_v2dfi (vector signed long long, + signed long long, const int); +@end smallexample + +The builti-ins @code{__builtin_vec_set_v16qi}, @code{__builtin_vec_set_v8hi}, +@code{__builtin_vec_set_v4si}, @code{__builtin_vec_set_v4sf}, +@code{__builtin_vec_set_v1ti}, @code{__builtin_vec_set_v2dfi} and +@code{__builtin_vec_set_v2dfi} return the input source vector with the element +indexed by the const int replaced by the scalar argument. + @smallexample vector signed char __builtin_vsx_cmple_16qi (vector signed char, vector signed char); diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-38.c b/gcc/testsuite/gcc.target/powerpc/altivec-38.c new file mode 100644 index 00000000000..01330e67110 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-38.c @@ -0,0 +1,503 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -save-temps" } */ + +#define DEBUG 0 + +#include +#include + +#if DEBUG +#include +#include +#endif + +void abort (void); + +void test_altivec_fix_sfsi (vector float vf_arg, + vector int vsi_expected_result) +{ + int i; + vector signed int vsi_result; + + vsi_result = __builtin_altivec_fix_sfsi (vf_arg); + + for (i = 0; i < 4; i++) + if (vsi_expected_result[i] != vsi_result[i]) +#if DEBUG + printf ("test_altivec_fix_sfsi: vsi_result[%d] = %i, vsi_expected_result[%d] = %d\n", + i, vsi_result[i], i, vsi_expected_result[i]); +#else + abort(); +#endif +} + +void test_altivec_fixuns_sfsi (vector float vf_arg, + vector unsigned int vui_expected_result) +{ + int i; + vector unsigned int vui_result; + + vui_result = __builtin_altivec_fixuns_sfsi (vf_arg); + + for (i = 0; i < 4; i++) + if (vui_expected_result[i] != vui_result[i]) +#if DEBUG + printf ("test_altivec_fixuns_sfsi: vui_result[%d] = %i, vsi_expected_result[%d] = %d\n", + i, vui_result[i], i, vui_expected_result[i]); +#else + abort(); +#endif +} + +void test_altivec_float_sisf (vector signed int vsi_arg, + vector float vf_expected_result) +{ + int i; + vector float vf_result; + + vf_result = __builtin_altivec_float_sisf (vsi_arg); + + for (i = 0; i < 4; i++) + if (vf_expected_result[i] != vf_result[i]) +#if DEBUG + printf ("test_altivec_float_sisf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n", + i, vf_result[i], i, vf_expected_result[i]); +#else + abort(); +#endif +} + +void test_altivec_uns_float_sisf (vector unsigned int vui_arg, + vector float vf_expected_result) +{ + int i; + vector float vf_result; + + vf_result = __builtin_altivec_uns_float_sisf (vui_arg); + + for (i = 0; i < 4; i++) + if (vf_expected_result[i] != vf_result[i]) +#if DEBUG + printf ("test_altivec_uns_float_sisf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n", + i, vf_result[i], i, vf_expected_result[i]); +#else + abort(); +#endif +} + +void test_altivec_vrsqrtfp (vector float vf_arg, + vector float vf_expected_result) +{ + /* Compute the reciprical of the square root of each vector element. */ + int i; + vector float vf_result; + + vf_result = __builtin_altivec_vrsqrtfp (vf_arg); + + for (i = 0; i < 4; i++) + if (vf_expected_result[i] != vf_result[i]) +#if DEBUG + printf ("test_altivec_vrsqrtfp: vf_result[%d] = %f, vf_expected_result[%d] = %f\n", + i, vf_result[i], i, vf_expected_result[i]); +#else + abort(); +#endif +} + +void test_altivec_mask_for_load (const double *sh, + vector signed char vsc_expected_result) +{ + int i; + vector signed char vsc_result; + + vsc_result = __builtin_altivec_mask_for_load (sh); + + for (i = 0; i < 16; i++) + if (vsc_expected_result[i] != vsc_result[i]) +#if DEBUG + printf ("test_altivec_mask_for_load: vsc_result[%d] = 0x%x, vsc_expected_result[%d] = 0x%x\n", + i, vsc_result[i], i, vsc_expected_result[i]); +#else + abort(); +#endif +} + +void test_altivec_vsel_1ti(vector signed __int128 vsq_arg1, + vector signed __int128 vsq_arg2, + vector unsigned __int128 vuq_arg3, + vector signed __int128 vsc_expected_result) +{ + vector signed __int128 vsc_result; + + vsc_result = __builtin_altivec_vsel_1ti (vsq_arg1, vsq_arg2, vuq_arg3); + + if (vsc_expected_result[0] != vsc_result[0]) + { +#if DEBUG + printf ("test_altivec_vsel_1ti: vsc_result = "); + printf(" (0x%llx%llx)", + (unsigned long long)(vsc_result[0] >> 64), + (unsigned long long)(vsc_result[0] & 0xFFFFFFFFFFFFFFFF)); + + printf (", vsc_expected_result = "); + printf(" (0x%llx%llx)\n", + (unsigned long long)(vsc_expected_result[0] >> 64), + (unsigned long long)(vsc_expected_result[0] + & 0xFFFFFFFFFFFFFFFF)); +#else + abort(); +#endif + } +} + +void test_altivec_vsel_1ti_uns (vector unsigned __int128 vuq_arg1, + vector unsigned __int128 vuq_arg2, + vector unsigned __int128 vuq_arg3, + vector unsigned __int128 vuc_expected_result) +{ + vector unsigned __int128 vuc_result; + + vuc_result = __builtin_altivec_vsel_1ti_uns (vuq_arg1, vuq_arg2, vuq_arg3); + + if (vuc_expected_result[0] != vuc_result[0]) + { +#if DEBUG + printf ("test_altivec_vsel_1ti_uns: vuc_result = "); + printf(" (0x%llx%llx)", + (unsigned long long)(vuc_result[0] >> 64), + (unsigned long long)(vuc_result[0] & 0xFFFFFFFFFFFFFFFF)); + + printf (", vuc_expected_result = "); + printf(" (0x%llx%llx)\n", + (unsigned long long)(vuc_expected_result[0] >> 64), + (unsigned long long)(vuc_expected_result[0] + & 0xFFFFFFFFFFFFFFFF)); +#else + abort(); +#endif + } +} + +void test_vec_init_v16qi (signed char sc_arg1, signed char sc_arg2, + signed char sc_arg3, signed char sc_arg4, + signed char sc_arg5, signed char sc_arg6, + signed char sc_arg7, signed char sc_arg8, + signed char sc_arg9, signed char sc_arg10, + signed char sc_arg11, signed char sc_arg12, + signed char sc_arg13, signed char sc_arg14, + signed char sc_arg15, signed char sc_arg16, + vector signed char vsc_expected_result) +{ + vector signed char vsc_result; + int i; + + vsc_result = __builtin_vec_init_v16qi (sc_arg1, sc_arg2, sc_arg3, sc_arg4, + sc_arg5, sc_arg6, sc_arg7, sc_arg8, + sc_arg9, sc_arg10, sc_arg11, sc_arg12, + sc_arg13, sc_arg14, sc_arg15, + sc_arg16); + + for (i = 0; i < 16; i++) + if (vsc_expected_result[i] != vsc_result[i]) +#if DEBUG + printf ("test_vec_init_v16qi: vsc_result[%d] = 0x%x, vsc_expected_result[%d] = 0x%x\n", + i, vsc_result[i], i, vsc_expected_result[i]); +#else + abort(); +#endif +} + +void test_vec_init_v4sf (float sf_arg1, float sf_arg2, + float sf_arg3, float sf_arg4, + vector float vf_expected_result) +{ + vector float vf_result; + int i; + + vf_result = __builtin_vec_init_v4sf (sf_arg1, sf_arg2, sf_arg3, sf_arg4); + + for (i = 0; i < 4; i++) + if (vf_expected_result[i] != vf_result[i]) +#if DEBUG + printf ("test_vec_init_v4sf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n", + i, vf_result[i], i, vf_expected_result[i]); +#else + abort(); +#endif +} + +void test_vec_init_v4si (int si_arg1, int si_arg2, + int si_arg3, int si_arg4, + vector signed int vsi_expected_result) +{ + vector signed int vsi_result; + int i; + + vsi_result = __builtin_vec_init_v4si (si_arg1, si_arg2, si_arg3, si_arg4); + + for (i = 0; i < 4; i++) + if (vsi_expected_result[i] != vsi_result[i]) +#if DEBUG + printf ("test_vec_init_v4si: vsi_result[%d] = %d, vsi_expected_result[%d] = %d\n", + i, vsi_result[i], i, vsi_expected_result[i]); +#else + abort(); +#endif +} + +void test_vec_init_v8hi (short int ss_arg1, short int ss_arg2, + short int ss_arg3, short int ss_arg4, + short int ss_arg5, short int ss_arg6, + short int ss_arg7, short int ss_arg8, + vector signed short int vss_expected_result) +{ + vector signed short int vss_result; + int i; + + vss_result = __builtin_vec_init_v8hi (ss_arg1, ss_arg2, ss_arg3, ss_arg4, + ss_arg5, ss_arg6, ss_arg7, ss_arg8); + + for (i = 0; i < 8; i++) + if (vss_expected_result[i] != vss_result[i]) +#if DEBUG + printf ("test_vec_init_v8hi: vss_result[%d] = %d, vss_expected_result[%d] = %d\n", + i, vss_result[i], i, vss_expected_result[i]); +#else + abort(); +#endif +} + +void test_vec_set_v16qi (vector signed char vsc_arg1, + signed char sc_arg1, + vector signed char vsc_expected_result) +{ + vector signed char vsc_result; + int i; + + vsc_result = __builtin_vec_set_v16qi (vsc_arg1, sc_arg1, 3); + + for (i = 0; i < 16; i++) + if (vsc_expected_result[i] != vsc_result[i]) +#if DEBUG + printf ("test_vec_set_v16qi: vsc_result[%d] = 0x%x, vsc_expected_result[%d] = 0x%x\n", + i, vsc_result[i], i, vsc_expected_result[i]); +#else + abort(); +#endif +} + +void test_vec_set_v4sf (vector float vsf_arg, float sf_arg1, + vector float vf_expected_result) +{ + vector float vf_result; + int i; + + vf_result = __builtin_vec_set_v4sf (vsf_arg, sf_arg1, 0); + + for (i = 0; i < 4; i++) + if (vf_expected_result[i] != vf_result[i]) +#if DEBUG + printf ("test_vec_init_v4sf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n", + i, vf_result[i], i, vf_expected_result[i]); +#else + abort(); +#endif +} + +void test_vec_set_v4si (vector int vsi_arg, int si_arg1, + vector signed int vsi_expected_result) +{ + vector signed int vsi_result; + int i; + + vsi_result = __builtin_vec_set_v4si (vsi_arg, si_arg1, 1); + + for (i = 0; i < 4; i++) + if (vsi_expected_result[i] != vsi_result[i]) +#if DEBUG + printf ("test_vec_init_v4si: vsi_result[%d] = %d, vsi_expected_result[%d] = %d\n", + i, vsi_result[i], i, vsi_expected_result[i]); +#else + abort(); +#endif +} + +void test_vec_set_v8hi (vector short int vss_arg, short int ss_arg, + vector signed short int vss_expected_result) +{ + vector signed short int vss_result; + int i; + + vss_result = __builtin_vec_set_v8hi (vss_arg, ss_arg, 2); + + for (i = 0; i < 8; i++) + if (vss_expected_result[i] != vss_result[i]) +#if DEBUG + printf ("test_vec_init_v8hi: vss_result[%d] = %d, vss_expected_result[%d] = %d\n", + i, vss_result[i], i, vss_expected_result[i]); +#else + abort(); +#endif +} + +int main () +{ + signed int si_arg1, si_arg2, si_arg3, si_arg4; + vector signed int vsi_arg, vsi_expected_result; + vector unsigned int vui_arg, vui_expected_result; + vector float vf_arg, vf_expected_result; + vector signed char vsc_arg, vsc_expected_result; + vector signed __int128 vsq_arg1, vsq_arg2, vsq_expected_result; + vector unsigned __int128 vuq_arg1, vuq_arg2, vuq_arg3, vuq_expected_result; + + signed char sc_arg1, sc_arg2, sc_arg3, sc_arg4, sc_arg5, sc_arg6, sc_arg7; + signed char sc_arg8, sc_arg9, sc_arg10, sc_arg11, sc_arg12, sc_arg13; + signed char sc_arg14, sc_arg15, sc_arg16; + + signed short int ss_arg1, ss_arg2, ss_arg3, ss_arg4, ss_arg5, ss_arg6; + signed short int ss_arg7, ss_arg8; + vector signed short int vss_arg, vss_expected_result; + + float sf_arg1, sf_arg2, sf_arg3, sf_arg4; + + vf_arg = (vector float) {1.1, -2.2, 4.6, -6.9}; + + vsi_expected_result = (vector int) {1, -2, 4, -6}; + test_altivec_fix_sfsi (vf_arg, vsi_expected_result); + + vui_expected_result = (vector unsigned int) {1, 0, 4, 0}; + test_altivec_fixuns_sfsi (vf_arg, vui_expected_result); + + vsi_arg = (vector int) {-27, 33, 293, -123}; + vf_expected_result = (vector float) {-27.0, 33.0, 293.0, -123.0}; + test_altivec_float_sisf (vsi_arg, vf_expected_result); + + vui_arg = (vector unsigned int) {27, 33, 293, 123}; + vf_expected_result = (vector float) {27.0, 33.0, 293.0, 123.0}; + test_altivec_uns_float_sisf (vui_arg, vf_expected_result); + + vf_arg = (vector float) { 0.25, 0.01, 1.0, 64.0 }; + vf_expected_result = (vector float) {2.0, 10.0, 1.0, 0.125}; + test_altivec_vrsqrtfp (vf_arg, vf_expected_result); + + vsc_expected_result = (vector signed char) {0x0F, 0x0E, 0x0D, 0x0C, + 0x0B, 0x0A, 0x09, 0x08, + 0x07, 0x06, 0x05, 0x04, + 0x03, 0x02, 0x01, 0x00}; + /* NULL, Lower bits are zero so result will be case 0x0 of the lvsl inst. */ + test_altivec_mask_for_load (NULL, vsc_expected_result); + + vsq_arg1 = (vector signed __int128) {0x0123456789ABCDEF}; + vsq_arg1 = (vsq_arg1 << 64) | (vector signed __int128) {0x0123456789ABCDEF}; + vsq_arg2 = (vector signed __int128) {0xFEDCBA9876543210}; + vsq_arg2 = (vsq_arg2 << 64) | (vector signed __int128) {0xFEDCBA9876543210}; + vuq_arg3 = (vector unsigned __int128) {0xFFFF00000000FFFF}; + vuq_arg3 = (vuq_arg3 << 64) | + (vector unsigned __int128) {0x0000FFFFFFFF0000}; + vsq_expected_result = (vector signed __int128) {0xFEDC456789AB3210}; + vsq_expected_result = (vsq_expected_result << 64) + | (vector signed __int128) {0x0123ba987654cdef}; + + test_altivec_vsel_1ti (vsq_arg1, vsq_arg2, vuq_arg3, vsq_expected_result); + + vuq_arg1 = (vector unsigned __int128) {0x0123456789ABCDEF}; + vuq_arg1 = (vuq_arg1 << 64) + | (vector unsigned __int128) {0x0123456789ABCDEF}; + vuq_arg2 = (vector unsigned __int128) {0xFEDCBA9876543210}; + vuq_arg2 = (vuq_arg2 << 64) + | (vector unsigned __int128) {0xFEDCBA9876543210}; + vuq_arg3 = (vector unsigned __int128) {0xFFFF00000000FFFF}; + vuq_arg3 = (vuq_arg3 << 64) + | (vector unsigned __int128) {0x0000FFFFFFFF0000}; + vuq_expected_result = (vector unsigned __int128) {0xFEDC456789AB3210}; + vuq_expected_result = (vuq_expected_result << 64) + | (vector unsigned __int128) {0x0123ba987654cdef}; + + test_altivec_vsel_1ti_uns (vuq_arg1, vuq_arg2, vuq_arg3, + vuq_expected_result); + + sc_arg1 = 1; + sc_arg2 = 2; + sc_arg3 = 3; + sc_arg4 = 4; + sc_arg5 = 5; + sc_arg6 = 6; + sc_arg7 = 7; + sc_arg8 = 8; + sc_arg9 = 9; + sc_arg10 = 10; + sc_arg11 = 11; + sc_arg12 = 12; + sc_arg13 = 13; + sc_arg14 = 14; + sc_arg15 = 15; + sc_arg16 = 16; + vsc_expected_result = (vector signed char) {0x1, 0x2, 0x3, 0x4, 0x5, 0x6, + 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, + 0xD, 0xE, 0xf, 0x10}; + + test_vec_init_v16qi (sc_arg1, sc_arg2, sc_arg3, sc_arg4, sc_arg5, + sc_arg6, sc_arg7, sc_arg8, sc_arg9, sc_arg10, + sc_arg11, sc_arg12, sc_arg13, sc_arg14, + sc_arg15, sc_arg16, vsc_expected_result); + + sf_arg1 = 1.0; + sf_arg2 = 2.0; + sf_arg3 = 3.0; + sf_arg4 = 4.0; + vf_expected_result = (vector float) {1.0, 2.0, 3.0, 4.0}; + test_vec_init_v4sf (sf_arg1, sf_arg2, sf_arg3, sf_arg4, + vf_expected_result); + + si_arg1 = 1; + si_arg2 = 2; + si_arg3 = 3; + si_arg4 = 4; + vsi_expected_result = (vector signed int) {1, 2, 3, 4}; + test_vec_init_v4si (si_arg1, si_arg2, si_arg3, si_arg4, + vsi_expected_result); + + ss_arg1 = 1; + ss_arg2 = 2; + ss_arg3 = 3; + ss_arg4 = 4; + ss_arg5 = 5; + ss_arg6 = 6; + ss_arg7 = 7; + ss_arg8 = 8; + vss_expected_result = (vector signed short int) {1, 2, 3, 4, 5, 6, 7, 8}; + test_vec_init_v8hi (ss_arg1, ss_arg2, ss_arg3, ss_arg4, + ss_arg5, ss_arg6, ss_arg7, ss_arg8, + vss_expected_result); + + vsc_arg = (vector signed char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, + 14, 15, 16}; + sc_arg1 = 40; + vsc_expected_result = (vector signed char) {1, 2, 3, 40, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 16}; + test_vec_set_v16qi (vsc_arg, sc_arg1, vsc_expected_result); + + vf_arg = (vector float) {1.0, 2.0, 3.0, 4.0}; + sf_arg1 = 10.0; + vf_expected_result = (vector float) {10.0, 2.0, 3.0, 4.0}; + test_vec_set_v4sf (vf_arg, sf_arg1, vf_expected_result); + + vsi_arg = (vector signed int) {1, 2, 3, 4}; + si_arg1 = 20; + vsi_expected_result = (vector signed int) {1, 20, 3, 4}; + test_vec_set_v4si (vsi_arg, si_arg1, vsi_expected_result); + + vss_arg = (vector signed short) {1, 2, 3, 4, 5, 6, 7, 8}; + ss_arg1 = 30; + vss_expected_result = (vector signed short) {1, 2, 30, 4, 5, 6, 7, 8}; + test_vec_set_v8hi (vss_arg, ss_arg1, vss_expected_result); +} + +/* { dg-final { scan-assembler-times "xvcvspsxws" 1 } } */ +/* { dg-final { scan-assembler-times "xvcvspuxws" 1 } } */ +/* { dg-final { scan-assembler-times "xvcvsxwsp" 1 } } */ +/* { dg-final { scan-assembler-times "xvcvuxwsp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrsqrtesp" 1 } } */ +/* { dg-final { scan-assembler-times "lvsl" 1 } } */ +/* { dg-final { scan-assembler-times "xxsel" 4 } } */ From patchwork Tue Feb 20 17:57:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carl Love X-Patchwork-Id: 203733 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp573810dyc; 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Tue, 20 Feb 2024 17:57:56 +0000 (GMT) Message-ID: Date: Tue, 20 Feb 2024 09:57:56 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 09/11] rs6000, add test cases for the vec_cmpne built-ins Content-Language: en-US To: gcc-patches@gcc.gnu.org, "bergner@linux.ibm.com" , Segher Boessenkool , "Kewen.Lin" References: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> From: Carl Love In-Reply-To: <41290fb1-e2e8-4779-b76f-2208c2dadedd@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: X2ii6WA30GQIYhaEoSDDp4SyBgqaSrak X-Proofpoint-ORIG-GUID: X2ii6WA30GQIYhaEoSDDp4SyBgqaSrak X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=877 lowpriorityscore=0 spamscore=0 suspectscore=0 mlxscore=0 adultscore=0 phishscore=0 bulkscore=0 malwarescore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402200129 X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791442019383679972 X-GMAIL-MSGID: 1791442019383679972 GCC maintainers: The patch adds test cases for the vec_cmpne of built-ins. The patch has been tested on Power 10 with no regressions. Please let me know if this patch is acceptable for mainline. Thanks. Carl ------------------------------------------------------------ rs6000, add test cases for the vec_cmpne built-ins Add test cases for the signed int, unsigned it, signed short, unsigned short, signed char and unsigned char built-ins. Note, the built-ins are documented in the Power Vector Instrinsic Programing reference manual. gcc/testsuite/ChangeLog: * gcc.target/powerpc/vec-cmple.c: New test case. * gcc.target/powerpc/vec-cmple.h: New test case include file. --- gcc/testsuite/gcc.target/powerpc/vec-cmple.c | 35 ++++++++ gcc/testsuite/gcc.target/powerpc/vec-cmple.h | 84 ++++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-cmple.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-cmple.h diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmple.c b/gcc/testsuite/gcc.target/powerpc/vec-cmple.c new file mode 100644 index 00000000000..766a1c770e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmple.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +/* Test that the vec_cmpne builtin generates the expected Altivec + instructions. */ + +#include "vec-cmple.h" + +int main () +{ + /* Note macro expansions for "signed long long int" and + "unsigned long long int" do not work for the vec_vsx_ld builtin. */ + define_test_functions (int, signed int, signed int, si); + define_test_functions (int, unsigned int, unsigned int, ui); + define_test_functions (short, signed short, signed short, ss); + define_test_functions (short, unsigned short, unsigned short, us); + define_test_functions (char, signed char, signed char, sc); + define_test_functions (char, unsigned char, unsigned char, uc); + + define_init_verify_functions (int, signed int, signed int, si); + define_init_verify_functions (int, unsigned int, unsigned int, ui); + define_init_verify_functions (short, signed short, signed short, ss); + define_init_verify_functions (short, unsigned short, unsigned short, us); + define_init_verify_functions (char, signed char, signed char, sc); + define_init_verify_functions (char, unsigned char, unsigned char, uc); + + execute_test_functions (int, signed int, signed int, si); + execute_test_functions (int, unsigned int, unsigned int, ui); + execute_test_functions (short, signed short, signed short, ss); + execute_test_functions (short, unsigned short, unsigned short, us); + execute_test_functions (char, signed char, signed char, sc); + execute_test_functions (char, unsigned char, unsigned char, uc); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmple.h b/gcc/testsuite/gcc.target/powerpc/vec-cmple.h new file mode 100644 index 00000000000..4126706b99a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmple.h @@ -0,0 +1,84 @@ +#include "altivec.h" + +#define N 4096 + +#include +void abort (); + +#define PRAGMA(X) _Pragma (#X) +#define UNROLL0 PRAGMA (GCC unroll 0) + +#define define_test_functions(VBTYPE, RTYPE, STYPE, NAME) \ +\ +RTYPE result_le_##NAME[N] __attribute__((aligned(16))); \ +STYPE operand1_##NAME[N] __attribute__((aligned(16))); \ +STYPE operand2_##NAME[N] __attribute__((aligned(16))); \ +RTYPE expected_##NAME[N] __attribute__((aligned(16))); \ +\ +__attribute__((noinline)) void vector_tests_##NAME () \ +{ \ + vector STYPE v1_##NAME, v2_##NAME; \ + vector bool VBTYPE tmp_##NAME; \ + int i; \ + UNROLL0 \ + for (i = 0; i < N; i+=16/sizeof (STYPE)) \ + { \ + /* result_le = operand1!=operand2. */ \ + v1_##NAME = vec_vsx_ld (0, (const vector STYPE*)&operand1_##NAME[i]); \ + v2_##NAME = vec_vsx_ld (0, (const vector STYPE*)&operand2_##NAME[i]); \ +\ + tmp_##NAME = vec_cmple (v1_##NAME, v2_##NAME); \ + vec_vsx_st (tmp_##NAME, 0, &result_le_##NAME[i]); \ + } \ +} + +#define define_init_verify_functions(VBTYPE, RTYPE, STYPE, NAME) \ +__attribute__((noinline)) void init_##NAME () \ +{ \ + int i; \ + for (i = 0; i < N; ++i) \ + { \ + result_le_##NAME[i] = 7; \ + if (i%3 == 0) \ + { \ + /* op1 < op2. */ \ + operand1_##NAME[i] = 1; \ + operand2_##NAME[i] = 2; \ + } \ + else if (i%3 == 1) \ + { \ + /* op1 > op2. */ \ + operand1_##NAME[i] = 2; \ + operand2_##NAME[i] = 1; \ + } \ + else if (i%3 == 2) \ + { \ + /* op1 == op2. */ \ + operand1_##NAME[i] = 3; \ + operand2_##NAME[i] = 3; \ + } \ + /* For vector comparisons: "For each element of the result_le, the \ + value of each bit is 1 if the corresponding elements of ARG1 and \ + ARG2 are equal." {or whatever the comparison is} "Otherwise, the \ + value of each bit is 0." */ \ + expected_##NAME[i] = -1 * (RTYPE)(operand1_##NAME[i] <= operand2_##NAME[i]); \ + } \ +} \ +\ +__attribute__((noinline)) void verify_results_##NAME () \ +{ \ + int i; \ + for (i = 0; i < N; ++i) \ + { \ + if ( (result_le_##NAME[i] != expected_##NAME[i]) ) \ + abort(); \ + } \ +} + +#define execute_test_functions(VBTYPE, RTYPE, STYPE, NAME) \ +{ \ + init_##NAME (); \ + vector_tests_##NAME (); \ + verify_results_##NAME (); \ +} +