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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id bt14-20020a056000080e00b002417e7f0685sm14576047wrb.9.2022.11.16.03.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 03:54:10 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] dt-bindings: arm: rockchip: Add SOQuartz Blade Date: Wed, 16 Nov 2022 12:53:34 +0100 Message-Id: <20221116115337.541601-2-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> References: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749654341676943112?= X-GMAIL-MSGID: =?utf-8?q?1749654341676943112?= This adds an enum for the SOQuartz Blade base board to the rockchip platforms binding. The SOQuartz Blade is a PoE-capable carrier board for the CM4 SoM form factor, designed around the SOQuartz CM4 System-on-Module. The board features the usual connectivity (GPIO, USB, HDMI, Ethernet) and an M.2 slot for SSDs. It may also be powered from a 5V barrel jack input, and has a 3.5mm jack for UART debug output. Signed-off-by: Nicolas Frattaroli Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index e40a3da90000..19797aca1fa0 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -578,6 +578,7 @@ properties: - description: Pine64 SoQuartz SoM items: - enum: + - pine64,soquartz-blade - pine64,soquartz-cm4io - const: pine64,soquartz - const: rockchip,rk3566 From patchwork Wed Nov 16 11:53:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 20993 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp102542wru; Wed, 16 Nov 2022 04:08:41 -0800 (PST) X-Google-Smtp-Source: AA0mqf7gV9VE/4ZmEaiPPIKgBEtaxdGh+jb7iJKG7PvoUaUZESo440kCy/6sQKurVESnaJpc4kmT X-Received: by 2002:a17:902:6bcc:b0:186:b063:339 with SMTP id m12-20020a1709026bcc00b00186b0630339mr8779630plt.70.1668600520637; Wed, 16 Nov 2022 04:08:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668600520; cv=none; d=google.com; s=arc-20160816; b=JMUGFYFnHngjr93gSwH6gC9zpbVZ87IROxEnv+PCYDULpFWry/a8jrqL8NR9IAl1ca OwIEXSe1PFwFzLrCnqcX0EVLWNd28w5Mm5QIYzid8U6Q52nlfWIJcZ/WBKwUT67FfNQT BH7sm3Zc5e20uzEsyXtQ26/1tL6Z+CGWSNXYSbwPfYDu5Msx8GRkTIt/OvVht6ddnzkL Ca8uFHaaPiyu9cQkF130Fmla3NudM77yPqJaw2QGp5/VbHqSNrCKdNMwtxxGnVkmtHWa F09hN5giKw/wZe3Cfz+trH5fXaE+qLKyfu6YlyJmJS4Oq3IwmVztutregN7kKAQzTvlu 2A+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UEGuDewmjyhmirLQjxFElQEIujVfJzvNkwrmuTJz5Vk=; b=kDlrnMrY7+XLm8ISAe9hAi93l2MEnDgjLN+PW0thmaJXjxQNKqXUzisSUbRZJu65o+ PJITkx31pf02lIaj1y9FrQnaro9jXEadERY4Vm8PrngIP1wD+wbNHvnljtbYVRcNBaY3 uHjq4rPMx2ZDL7D+AHTlfjhWBg2vRppedEaS+XM2okB9FNNhyaseYSp9oW4PXdUUiWDv yKLBU8TPBPlXP91SfuhZhNBiyUp3za3i/YlP3OA+8NIZOYSeAVTOktjf/OAjVQdiSWRf 5UG1JK/pj0x3VWmG1b+suGDNvXMyIuCYKy8SvsL+hKkvoA+tS6qwyu8bhIX9WfVnKG7j zeHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=XZAFWdid; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id bt14-20020a056000080e00b002417e7f0685sm14576047wrb.9.2022.11.16.03.54.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 03:54:14 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Andrew Powers-Holmes , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] arm64: dts: rockchip: Add SOQuartz blade board Date: Wed, 16 Nov 2022 12:53:35 +0100 Message-Id: <20221116115337.541601-3-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> References: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749654459494011024?= X-GMAIL-MSGID: =?utf-8?q?1749654459494011024?= From: Andrew Powers-Holmes This adds a device tree for the PINE64 SOQuartz blade baseboard, a 1U rack mountable baseboard for the CM4 form factor with PoE support designed for the SOQuartz CM4 System-on-Module. The board takes power from either PoE or a 5V DC input, and allows for mounting an M.2 SSD. The board also features one USB 2.0 host port, one HDMI output, a 3.5mm jack for UART, and the aforementioned gigabit networking port. Signed-off-by: Andrew Powers-Holmes [rebase, squash, reword, misc fixes] Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3566-soquartz-blade.dts | 194 ++++++++++++++++++ 2 files changed, 195 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 832613143030..528a02b11552 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts new file mode 100644 index 000000000000..4e49bebf548b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include + +#include "rk3566-soquartz.dtsi" + +/ { + model = "PINE64 RK3566 SOQuartz on Blade carrier board"; + compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* labeled VCC_SSD in schematic */ + vcc3v3_pcie_p: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v_dcin: vcc5v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + color = ; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "disk-activity"; + status = "okay"; +}; + +&led_work { + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc3v3_pcie_p>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +&sdmmc0 { + vmmc-supply = <&vcc3v0_sd>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vbus>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc5v_dcin>; +}; From patchwork Wed Nov 16 11:53:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 20992 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp102484wru; Wed, 16 Nov 2022 04:08:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf4Cmb51q2pKa1CpFIBblHlls4QC7LZLBrJ/bRIdkjDPJbBKEtoLTUyjEVuU1Ur01NRVfuE+ X-Received: by 2002:a63:ff1a:0:b0:476:7faf:e0bf with SMTP id k26-20020a63ff1a000000b004767fafe0bfmr12848594pgi.80.1668600513920; Wed, 16 Nov 2022 04:08:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id bt14-20020a056000080e00b002417e7f0685sm14576047wrb.9.2022.11.16.03.54.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 03:54:19 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] dt-bindings: arm: rockchip: Add SOQuartz Model A Date: Wed, 16 Nov 2022 12:53:36 +0100 Message-Id: <20221116115337.541601-4-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> References: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749654452523726730?= X-GMAIL-MSGID: =?utf-8?q?1749654452523726730?= The SOQuartz Model A base board is a carrier board for the CM4 form factor, designed around the PINE64 SOQuartz CM4 SoM. The board sports "Model A" dimensions like the Quartz64 Model A, but is not to be confused with that. As for I/O, it features USB 2 ports, Gigabit Ethernet, a PCIe 2 x1 slot, HDMI, a 40-pin GPIO header, CSI/DSI connectors, an eDP flat-flex cable connector, a 12V DC barrel jack for power input and power/reset buttons as well as a microSD card slot. Signed-off-by: Nicolas Frattaroli Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 19797aca1fa0..1eff0afc19a1 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -580,6 +580,7 @@ properties: - enum: - pine64,soquartz-blade - pine64,soquartz-cm4io + - pine64,soquartz-model-a - const: pine64,soquartz - const: rockchip,rk3566 From patchwork Wed Nov 16 11:53:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 20990 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp101676wru; Wed, 16 Nov 2022 04:07:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf7pzenDCy52K3Th03Ay11HEQEPkRbt8aPvk6pirpsqUXvdu3rbdwtOCrIgOp/btbKXg/7WH X-Received: by 2002:a63:df14:0:b0:476:e84c:ab65 with SMTP id u20-20020a63df14000000b00476e84cab65mr2451845pgg.513.1668600422161; Wed, 16 Nov 2022 04:07:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668600422; cv=none; d=google.com; s=arc-20160816; b=E7H2UJXQIPB5J8Gyx3wngmhTiOVBpdTPLk/qmz2ZI9fWuxnGIzthzXREQRcwIQkojF FZ43pYU2SrOX0kJQtmJI8XzpV1K4HKq4F885NCgnA7hHgHk34vjj7vqp+OQUi7BZ3qku 8rRwPq8Zuprsoxwwe9DtsWjrdeLtWaW5lZ8KyoDD8nWyp/RSYO0xblncIMHKr9bRxmki cxP6ekI81w+OsidxVW8+W1LFfnNFpZB+BNR1JbcdI0AZCwN/rxhz4YTmu3cscVjXop64 4aTSKw5dmesVeFn1l9tYAdt5iaEZHNzpHvlxr7xApqYcjQxnyYsWHav6nCKIJEn8Wbjo UaVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6/TfDkn8E1wKATyX/gU0RGSZ6sAmInYSFUBAN2pVLwE=; b=uzSBFsDpdHMIfUTHoXE2DBG6z0lpRW2Mg4+S7WZ+palAhc1psxjRGIYjqYJpGvHSXS mgIfMh+Odr2kslBrfnHtdLxSTUg1SDGoOvVDtTwp4fu1K6oX35qG6z39OSiHnTmYTqlf 5XUgZ92Ugb+097xvL5nnjS3u4ZLBtc9glCcJjKmFJEutUM7w0jhGHaZjmMh6HNkCTrFE 5l3ttp4KCAm4WbOoqciiHAn1KE/rfCWNQwHBTuxeeh2m1Dw0kKPjVz3ioE6UddHsggnO dWs3DTFI74Q/rfKSE2AYGUIo923tha0CtyZ7Dwk9KmvHUQfu48m4mbquDP6zYLo8gPTJ Pz+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="YD7wB7w/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id bt14-20020a056000080e00b002417e7f0685sm14576047wrb.9.2022.11.16.03.54.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 03:54:23 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Andrew Powers-Holmes , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] arm64: dts: rockchip: rk3566: Add SOQuartz Model A baseboard Date: Wed, 16 Nov 2022 12:53:37 +0100 Message-Id: <20221116115337.541601-5-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> References: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749654356513588071?= X-GMAIL-MSGID: =?utf-8?q?1749654356513588071?= From: Andrew Powers-Holmes This patch adds the device tree for the "Model A" baseboard for the SOQuartz CM4 SoM, which is not to be confused with the Quartz64 Model A, which is the same form factor and SoC, but is not a CM4 carrier board. The board features a PCIe 2 x1 slot, USB 2 host ports, CSI/DSI connectors, an eDP FFC connector, gigabit ethernet, HDMI, and a 12V DC barrel jack. Also present is a microSD card slot, 40-pin GPIO, and a power and reset button. Signed-off-by: Andrew Powers-Holmes [rebase, misc fixes, reword] Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3566-soquartz-model-a.dts | 232 ++++++++++++++++++ 2 files changed, 233 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 528a02b11552..f78c0a935bce 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts new file mode 100644 index 000000000000..2208dbfb7f0a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model = "PINE64 RK3566 SOQuartz on Model A carrier board"; + compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled DCIN_12V in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* + * Labelled VCC3V0_SD in schematic to not conflict with PMIC + * regulator, it's 3.3v in actuality + */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc12v_pcie: vcc12v-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +/* phy for pcie */ +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + + /* + * the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + status = "okay"; +}; + +&led_work { + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +/* + * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+ + * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys, + * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards. + */ +&sdmmc0 { + vmmc-supply = <&vcc3v3_sd>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc5v0_usb>; +}; + +&vcc3v3_sd { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "okay"; +};