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Mon, 19 Feb 2024 15:07:01 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Mon, 19 Feb 2024 23:05:26 +0800 Subject: [PATCH v3 1/3] arm64: dts: hi3798cv200: fix the size of GICR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240219-cache-v3-1-a33c57534ae9@outlook.com> References: <20240219-cache-v3-0-a33c57534ae9@outlook.com> In-Reply-To: <20240219-cache-v3-0-a33c57534ae9@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708355220; l=1236; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=Q7LcOT/VwpsuZcFlk8XRnwmi13g7rI7h0WTW2e9avFs=; b=Jm1sLBoWsNwRJnBJqT57uUsQ1DHPNPKwfkMsWU3hTpw3/doshoWyTEdH8NI4jO9bvXfuXAZ5F FGleHPqE4pEDExYWkqaZcbEFAOM4CmVWgzh11Fe/xVPEr+ime6GIurZ X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791340516936194676 X-GMAIL-MSGID: 1791340516936194676 From: Yang Xiwen During boot, Linux kernel complains: [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set This SoC is using a regular GIC-400 and the GICR space size should be 8KB rather than 256B. With this patch: [ 0.000000] GIC: Using split EOI/Deactivate mode So this should be the correct fix. Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen Cc: stable@vger.kernel.org --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index ed1b5a7a6067..d01023401d7e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,7 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>; /* GICC */ #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; From patchwork Mon Feb 19 15:05:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Xiwen via B4 Relay X-Patchwork-Id: 203145 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp1345253dyc; Mon, 19 Feb 2024 07:10:42 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWKm4VBdMvA16x5zYaeievUC8kQyd+1JTQQDkLlHvOUogfDYjArknmMyMEwra052oqhZywW8hrAlVyGaZUpaCohtrGmzQ== X-Google-Smtp-Source: AGHT+IFbZE2BMZoodaVcWJVw5ltU72avuzR3kmyibhe/34oApRVZ/srnK2L9+yz5xVaeiKIr5CUb X-Received: by 2002:a0c:f310:0:b0:68f:327e:ddfc with SMTP id j16-20020a0cf310000000b0068f327eddfcmr9945786qvl.19.1708355441930; Mon, 19 Feb 2024 07:10:41 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708355441; cv=pass; d=google.com; s=arc-20160816; b=G0Uu8CMsl6uZm+2VphRToJ43jp0y4SKSYqRnfB0EMWjaf+lNvaRDethP2rNARo3YG4 F9kC35HazE+ix5TO3bXqsk6+8XqyDa2g08D2XQ3b6Qeb2WfnKs1lFeGjMhmtlp2piu7a E+18R4QvgfchfNvrVYw/M/KWucJK7SQuNIkMc6MNal16mPD1ATNLxqMR5XnLQWmgvjCN WenZqseENvwdJbEs5OhGp58akG9wtz1uHi1iZ/1jKDiC3iwDAoK8GDRGCTYM8iBmZJbq 2lB1//O6jwp7n6aD4RgV00wTu4tkx8LYi7tUj7xLnwAbFTbsoSnvs0t/Cd2CWE74FGaG hPSA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=reply-to:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:subject:date:from:dkim-signature; bh=3DFSFX6xOmVard0tLEeZ0HKK2KOemEi2o75VeU03MRg=; fh=o4k1Y5gvQFNdxOESfscvcAr2OEII+qxAcHkz3ODI8y4=; b=QW9P32AJYLpLLe8OhqkCBT8fnPKzTsmNCX/MKsfhLoi0EUAROvVtFyNX5K1YSiExHA 82Q3+73DogHtj9oq640YEKsfMI+9gdffMk1pYzsfdIFfw1aly8DuLSfz9xO/wJI5A+mt DGlFZTMnjDbum8lZk/ru/PE5ra0hs9MeiRMJkwKww6R+KVjYmnAkHmkPPaFoLcZh0jYH MO56OVhHnItMb9qpf8gewbNW4Pq7309AU8yfHv1ibUBJ3yplt8aN7hpR3xKPa0uY9Y+N qMGzm0YuIt/K2JOAKOBPVi6rSVqVdO6NEyW227Yhpg10Msrl63rQyhuf6pd3emYNQXvK bSeQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=bAT3um3x; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-71554-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-71554-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Mon, 19 Feb 2024 15:07:01 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Mon, 19 Feb 2024 23:05:27 +0800 Subject: [PATCH v3 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240219-cache-v3-2-a33c57534ae9@outlook.com> References: <20240219-cache-v3-0-a33c57534ae9@outlook.com> In-Reply-To: <20240219-cache-v3-0-a33c57534ae9@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708355220; l=1117; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=oWPOXVSM7W5vHY31kDr4p2HrgQkuCpZx2sc6S9SlCF8=; b=/FnJ4jqTMm6uyoHP9rZXBktLTdCPZvHTR3101rtPQylnDigXhthwv/HvdBRI8vAaP5oYbRtqi QxY1QvVd/7jANK8eTA2Fker2F5B1Huf7MQB1rZkT31lnLt5M6F4+mqW X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791340516005908812 X-GMAIL-MSGID: 1791340516005908812 From: Yang Xiwen This is needed by KVM to make use of VGIC code. Just like regular GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been verified. Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index d01023401d7e..fc64d2fa99eb 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,11 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x2000>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>, /* GICC */ + <0x0 0xf1004000 0x0 0x2000>, /* GICH */ + <0x0 0xf1006000 0x0 0x2000>; /* GICV */ + interrupts = ; #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; From patchwork Mon Feb 19 15:05:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Xiwen via B4 Relay X-Patchwork-Id: 203147 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp1345290dyc; Mon, 19 Feb 2024 07:10:44 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUwyZvuwG/qEHWDfdg8F3KBM8VaDc/1ALjL4lptF4964WnnIoIUcxLqo0Es6al16P8dlSwrzC/bgDJLYAnfjeHtwPTNVg== X-Google-Smtp-Source: AGHT+IF5pI+TCAok1TdxHeCJMHSuoa+Sjt8kW8+JjbKK/szHX+jrwdIUQgxxtB4rKykjQH3AgxSJ X-Received: by 2002:a17:902:da87:b0:1db:28c4:b757 with SMTP id j7-20020a170902da8700b001db28c4b757mr13441168plx.0.1708355444423; Mon, 19 Feb 2024 07:10:44 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708355444; cv=pass; d=google.com; s=arc-20160816; b=XIaziFT0U3lokB4he+rotKAZ8L8noR2q/taNyGWvlYFzPkIKXC+6tbDnGV9f5ME3M+ Bu+kPGJWYAG9sDcgIA5Klt/xnx40hYrTXRsbhe7KhLdHwyEPMx2E+1wrLEa1Al0FK7Db h7P8LItF7y4So5tE+OwkCmXZzFLCDjql9PcMLYAY0DWpuafFLrbk6nD0Se4SeypnRhXw kltxaZ298V/TfUZHT4TUXV5GbpwgB4wL7Md/WmDWG+C8nNNpnz38ESMJAZkP6Ued/miI fJpL96xYiLT2tqsqhcGIyIQ0tPl0dVKBgC5Fs1yz1Eslx0sdqp6g0LL4X/LqB8zpk6qN 7AzA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=reply-to:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:subject:date:from:dkim-signature; bh=EVwGhsn1miE3DNda7Q5W2swOPusm7MxAdq+r1Qs5DQ4=; fh=o4k1Y5gvQFNdxOESfscvcAr2OEII+qxAcHkz3ODI8y4=; b=DPUSEwk5IBnRHXa5pNDQHo+ye1SdgjKkrmSyYcic+ZWlZNIYCKmkVt4bWR7Kp8sbFL Y9sRhiCCE95n47Yt5aSmK1UAMifmwq8dvj75zYjzSUjJcw6WqL2pZxWQ65OYB18On6H5 q6VYO2gdsDSLHsPd1AsUNPTMt5ertUueWrLCAczOC9/+bJxiS9d2Ysx9DWaAMluWXxDP nF3NoLsr8NZ5woYkbsvwWuHUBWRmrhKSHmR7q4jlYkS9n7t96g5ayo4zPbm3OEWSYpK7 xl+qWMimoCk6klvaN61JMtoLDZCY6sz/76WHqgYmivZFYgWIKAgT4CuXAsy6RzI28hDe sGiw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=dGIJ8r5v; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-71555-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-71555-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Mon, 19 Feb 2024 15:07:01 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Mon, 19 Feb 2024 23:05:28 +0800 Subject: [PATCH v3 3/3] arm64: dts: hi3798cv200: add cache info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240219-cache-v3-3-a33c57534ae9@outlook.com> References: <20240219-cache-v3-0-a33c57534ae9@outlook.com> In-Reply-To: <20240219-cache-v3-0-a33c57534ae9@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708355220; l=2828; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=JCsSJLmRtX8xpTr7tVRxOMtB1SM8sQgXyZwjBU7p06U=; b=xqgpLfoVrqGs2VoZ+PuH1dOy0Z9Fq4MUu+Y3kHKp1cEtduRNLeydUq8AxTXjj8so/JunkHLKW Q8mtsMytX5+DXoRi5eQY8ceAPKRU3PIgKKnWzdSWoZKfDdtYhrLPDqF X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791340518596965149 X-GMAIL-MSGID: 1791340518596965149 From: Yang Xiwen During boot, the kernel complains: [ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0 So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1 i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache) With this patch, the line above is gone and the following info is added to the output of `lscpu`: Caches (sum of all): L1d: 128 KiB (4 instances) L1i: 128 KiB (4 instances) L2: 512 KiB (1 instance) Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen Cc: stable@vger.kernel.org --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index fc64d2fa99eb..f6bc001c3832 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -31,6 +31,13 @@ cpu@0 { device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@1 { @@ -38,6 +45,13 @@ cpu@1 { device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@2 { @@ -45,6 +59,13 @@ cpu@2 { device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@3 { @@ -52,9 +73,25 @@ cpu@3 { device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; }; + L2: l2-cache { + compatible = "cache"; + cache-unified; + cache-size = <0x80000>; /* 512 KiB */ + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */