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bh=9bZTQfFErD83ZpeUe8f6tUjcWK8u+2HNM0QEJ6Cyo2s=; b=hFjUjvKR0JKs/dssdk3MOmFCIW3zrTofvZq+9VGGWnsKnyqLBoZPGYaUBP3GS8EXdr1DUl 7ypoTNyPVIx/0+aNooOCTkLGGDTb77pTqCqArMCw7b+mFHgRZZi9uvCNxcTBPREg9OoZQx ksdvTDvQe6oT1rnst6F03X0B3SLkhWUZEUv2aZhwIt2yeeZDCxo9aq2dmfZ+0Ew7+oLf2/ WJrP5yOehtVQAfPqWR9XQoddQ5Mk7ccY+SNhJ/uBinfZH7QYWETfKjLNgcl67vMRRqXT4F 6IxEumVeXKw/Z9XOG2BWLq4ZH0QBJSJmZ2uB7oFY6rPOlXgC7J2efvVFLuPiPA== From: Alexander Stein To: Stefan Agner , Alison Wang , David Airlie , Daniel Vetter , Matthias Schiffer Cc: Alexander Stein , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [RESEND 1/2] drm: fsl-dcu: Use dev_err_probe Date: Mon, 19 Feb 2024 13:24:48 +0100 Message-Id: <20240219122449.3083748-1-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791330156338272696 X-GMAIL-MSGID: 1791330156338272696 fsl_dcu_drm_modeset_init can return -EPROBE_DEFER, so use dev_err_probe to remove an invalid error message and add it to deferral description. Signed-off-by: Alexander Stein --- drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index a395f93449f3..90cbd18f096d 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -103,10 +103,8 @@ static int fsl_dcu_load(struct drm_device *dev, unsigned long flags) int ret; ret = fsl_dcu_drm_modeset_init(fsl_dev); - if (ret < 0) { - dev_err(dev->dev, "failed to initialize mode setting\n"); - return ret; - } + if (ret < 0) + return dev_err_probe(dev->dev, ret, "failed to initialize mode setting\n"); ret = drm_vblank_init(dev, dev->mode_config.num_crtc); if (ret < 0) { From patchwork Mon Feb 19 12:24:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 203039 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp1247552dyc; Mon, 19 Feb 2024 04:26:10 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXaqW81qmajtdottx4X9CFUw9wAF4pto44Z1yREGsxoeheB4SMjhewCjPUaH4ZOM38U6HVwq+Wwa0quhgpi3ucPCz+Uww== X-Google-Smtp-Source: AGHT+IHwTrxxuvjXYtZr/ycXkTe2oP88pXXoBZNPUyUlrIILToUfcxOqTp3M/sRyCV37LDM2Fbds X-Received: by 2002:a05:6214:4989:b0:68f:3fad:f6f6 with SMTP id pf9-20020a056214498900b0068f3fadf6f6mr14016689qvb.9.1708345570332; Mon, 19 Feb 2024 04:26:10 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708345570; cv=pass; d=google.com; s=arc-20160816; b=b78ofeS8sLy61p1+FmS9ttG99/2abINiD0d1NgnAXV1w8+6+1XRLW8151hNU5lPoIA i7yMTUuOYo4R/UO2niZoYP/PUbyvZcsaeLci3DAFccQb9/uiga+l+vXRfHunqBIrHbCu iuGP0dGGbJYZR7YaYHpKoa57/FDvjnI38u4DZlswjm8ZBUyFQRqkvvHIUEuUcJWamsqB IV9M97nJ5LxSagGzJ/ilJ9QaqJya9Etea5hJLVZxNg1Bes9RVdYKWtrsIN4pf7zvPCYj ChklYSfNbWjH4PKufM3VPVGJhETOZUkPXHZQubUg45dc5S6BnoHtd9sW+YNvBtmyyxFE z3PQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature:dkim-signature; bh=ih/v3JlPgjnunjeMXetvHkaR0ZTTwffvOCV3Ri/27Bg=; fh=CuVphc63AmGNEZ6KqOLSqSkA3DRazp+8tNJu0RWIWtQ=; b=VwvUZzsA1Z9sL0YCSj+rzzLan3TFu+V0eNMsst4PNztKLvqu4cgFimVfH29/lNJCDY +kVMCPUmW12CZnywMphxH9Sx3aZCky6YN45XQAaViXjoCqF3Fdl3qGQiu8NtVRmr5vtX QFT5Z6WR+weQHs/2D5g6G6SK2pYEArIYALouWglprX2t+zMq+oUiuVjrNPjZieR3dj8d JxA6DtBawA3L2BJxLAZL66jBfDP/aHymqC1S4HArrZD4snksm6cOs3kqMEGpgTrmvkeI yqXIBjSLUAe3bL1J+pAXcr+xNeQNX5g7IW2fq556ALc0lybTuMLKshCgJOSKdRO1EBWC ieBg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@tq-group.com header.s=key1 header.b="FU4/egJ2"; dkim=temperror (no key for signature) header.i=@ew.tq-group.com header.s=dkim header.b=J2+oV1ZK; arc=pass (i=1 spf=pass spfdomain=ew.tq-group.com dkim=pass dkdomain=tq-group.com dmarc=pass fromdomain=ew.tq-group.com); spf=pass (google.com: domain of linux-kernel+bounces-71300-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-71300-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=tq-group.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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d=ew.tq-group.com; s=dkim; t=1708345498; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ih/v3JlPgjnunjeMXetvHkaR0ZTTwffvOCV3Ri/27Bg=; b=J2+oV1ZKOKLcn/qz2bJ4YrrX7urblOuYeRkmuWrGrDbzdB83S6EHxLju7VhlxI1o9gdH4P gOPTG5kfX1mapEHgwI8olPJSvd6Sa8WK+dLdHrcsR4q1ZPV4ufqTOyRTH4F/2Fc7bBGOtp mI+xwz2RrdckbZnKGrEnvt99ogvYyCo/e9XZYaHDKlmkXFtvDbWn3gdKnr7J3LmD3tfyq9 /5J2Ntk5yfaIdHw3vH/gxNUBr+G+1I7A88E6eom7g6dsY1DzEVdHekMeyS7jtj2NHDeYGZ IESZMabRoKToR7tODX+CySpQCeTl4bWR9MQVyqyMFQOglcj+IK+omsmIptYlFg== From: Alexander Stein To: Stefan Agner , Alison Wang , David Airlie , Daniel Vetter , Matthias Schiffer Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Stein Subject: [RESEND 2/2] drm: fsl-dcu: enable PIXCLK on LS1021A Date: Mon, 19 Feb 2024 13:24:49 +0100 Message-Id: <20240219122449.3083748-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219122449.3083748-1-alexander.stein@ew.tq-group.com> References: <20240219122449.3083748-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791330165246278479 X-GMAIL-MSGID: 1791330165246278479 From: Matthias Schiffer The PIXCLK needs to be enabled in SCFG before accessing certain DCU registers, or the access will hang. Signed-off-by: Matthias Schiffer Signed-off-by: Alexander Stein --- drivers/gpu/drm/fsl-dcu/Kconfig | 1 + drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 14 ++++++++++++++ drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 3 +++ 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/fsl-dcu/Kconfig b/drivers/gpu/drm/fsl-dcu/Kconfig index 5ca71ef87325..c9ee98693b48 100644 --- a/drivers/gpu/drm/fsl-dcu/Kconfig +++ b/drivers/gpu/drm/fsl-dcu/Kconfig @@ -8,6 +8,7 @@ config DRM_FSL_DCU select DRM_PANEL select REGMAP_MMIO select VIDEOMODE_HELPERS + select MFD_SYSCON if SOC_LS1021A help Choose this option if you have an Freescale DCU chipset. If M is selected the module will be called fsl-dcu-drm. diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index 90cbd18f096d..283858350961 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -100,12 +100,26 @@ static void fsl_dcu_irq_uninstall(struct drm_device *dev) static int fsl_dcu_load(struct drm_device *dev, unsigned long flags) { struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; + struct regmap *scfg; int ret; ret = fsl_dcu_drm_modeset_init(fsl_dev); if (ret < 0) return dev_err_probe(dev->dev, ret, "failed to initialize mode setting\n"); + scfg = syscon_regmap_lookup_by_compatible("fsl,ls1021a-scfg"); + if (PTR_ERR(scfg) != -ENODEV) { + /* + * For simplicity, enable the PIXCLK unconditionally. Disabling + * the clock in PM or on unload could be implemented as a future + * improvement. + */ + ret = regmap_update_bits(scfg, SCFG_PIXCLKCR, SCFG_PIXCLKCR_PXCEN, + SCFG_PIXCLKCR_PXCEN); + if (ret < 0) + return dev_err_probe(dev->dev, ret, "failed to enable pixclk\n"); + } + ret = drm_vblank_init(dev, dev->mode_config.num_crtc); if (ret < 0) { dev_err(dev->dev, "failed to initialize vblank\n"); diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h index e2049a0e8a92..566396013c04 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h @@ -160,6 +160,9 @@ #define FSL_DCU_ARGB4444 12 #define FSL_DCU_YUV422 14 +#define SCFG_PIXCLKCR 0x28 +#define SCFG_PIXCLKCR_PXCEN BIT(31) + #define VF610_LAYER_REG_NUM 9 #define LS1021A_LAYER_REG_NUM 10