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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41J94ZnV011977; Mon, 19 Feb 2024 03:04:39 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , Subject: [PATCH v2 1/2] arm64: dts: ti: k3-j722s-evm: Enable CPSW3G RGMII1 Date: Mon, 19 Feb 2024 14:34:34 +0530 Message-ID: <20240219090435.934383-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219090435.934383-1-vaishnav.a@ti.com> References: <20240219090435.934383-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791317541299219396 X-GMAIL-MSGID: 1791317541299219396 From: Siddharth Vadapalli Enable MAC Port 1 of CPSW3G instance of CPSW Ethernet Switch in RGMII-RXID mode of operation. Port 2 is not connected on the EVM, thus keep it disabled. Signed-off-by: Siddharth Vadapalli Signed-off-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index b4f2fee53a97..9e12a6e9111f 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include #include "k3-j722s.dtsi" / { @@ -160,6 +161,58 @@ J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ >; bootph-all; }; + + mdio_pins_default: mdio-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + }; +}; + +&cpsw3g { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; }; &main_gpio1 { From patchwork Mon Feb 19 09:04:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 202975 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp1163038dyc; Mon, 19 Feb 2024 01:05:29 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXhUG0vD1t4KqSlPclOt/QrPvy7UInEElPKAOYovnnfXzS/setNqXs8aRKYJ7IpH5Qd0nTnPt/Pcx/ylHbcqFm7+5KllQ== X-Google-Smtp-Source: AGHT+IErO/1FMhD6PHrdgKEwEUlNy/G7Z1TARG+BkDraZrLvkXtQaybSGXc3Z/EBNt6d+mwYO0qt X-Received: by 2002:a17:907:bb8d:b0:a3e:9ad2:5f37 with SMTP id xo13-20020a170907bb8d00b00a3e9ad25f37mr1167163ejc.16.1708333529632; Mon, 19 Feb 2024 01:05:29 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708333529; cv=pass; d=google.com; s=arc-20160816; b=v+O9rfp7nNegMxl8Tat6fIk3XmPjybUPRDrlWiTXrZiEEJ+/DKBlcJZEfdKQQL4Xh6 OZk1Lbjkm8AI/aFKv7LSWJWIaoPvljnUmN41DmjmrdNmnFreYATWHZO6/j/AZ2MCY+BC VgGO0DsimPq0SwFA0LB1FVjPSoY18ECr9uNmoFJEnL+IDkszCob4a20ybQ/1DGjExNAm TBEZh8SrmqsUeHq+/FSjJ26GuHwPP1WPjr0fpqZWYkt3MHSGXR5g58RDUOt4+eCjDQ1Q /mAd4L4ujjcqiDSk/w1BYJkIG7WBUYtir+4Ts9gCjodj72ycfpqvaaS+QLXL6TUvODii yy9Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=UX+R3vrf/vh6sGWWi37SEiGJ2+BZgfectRVJ4DobpLE=; fh=j03uLb/fUHd4PvvwK6aOXFRssHiOxsq7jQ36+mIKgOU=; b=K0v0zYg1G6lW1TIzEU8G231ai7R0YAUuEECwj/VW7snzqGa3O9bWJyuC09jlo3KAzB JRa5QVy2GFyV4HlxQnm5Z4UNela7d7pDLeRf+FszZCVcSYQ95v90FA6GUnVEqDFbDtV1 fNQ5DW5jtwSDH8b1Q0ZqeNbVcChvl0ELxA8OVzy8Q/G9sri+ludRj/LHHr+AuMw9m4a9 g7nH+nSxkiWiJStUP4sxDWPZeDFqKN6BWlj4A4a0X2fgcJCnfTEIbYKHSyLFK9p5T/vq 4TMC3/2j/ny0Pgp3U5uIGcNuWGXGEJ7++KzXP8PC7+FEBRg4VeFS1s37hblGK8pbn906 CjXA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FZW+i+br; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-70993-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-70993-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41J94ZnW011977; Mon, 19 Feb 2024 03:04:43 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , Subject: [PATCH v2 2/2] arm64: dts: ti: k3-j722s-evm: Enable OSPI NOR support Date: Mon, 19 Feb 2024 14:34:35 +0530 Message-ID: <20240219090435.934383-3-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219090435.934383-1-vaishnav.a@ti.com> References: <20240219090435.934383-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791317539438704426 X-GMAIL-MSGID: 1791317539438704426 J722S EVM has S28HS512T 64 MiB Octal SPI NOR flash connected to the OSPI interface, add support for the flash and describe the partition information as per bootloader. Signed-off-by: Vaishnav Achath --- V1->V2: * Update comments indicating PAD numbers. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 79 +++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 9e12a6e9111f..cee3a8661d5e 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -169,6 +169,23 @@ J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ >; }; + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ + J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ + J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ + J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ + J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ + J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ + J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */ + J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */ + J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */ + J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */ + J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */ + >; + bootph-all; + }; + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ @@ -290,6 +307,68 @@ exp1: gpio@23 { }; }; +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x00 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; + +}; + &sdhci1 { /* SD/MMC */ vmmc-supply = <&vdd_mmc1>;