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Sun, 18 Feb 2024 12:03:07 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 18 Feb 2024 20:02:50 +0800 Subject: [PATCH v2 1/3] arm64: dts: hi3798cv200: fix the size of GICR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240218-cache-v2-1-1fd919e2bd3e@outlook.com> References: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com> In-Reply-To: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708257770; l=1243; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=cM/+jwZOd1PTjdjnQjIchbxxptzvx3CBS8/AnT/3vpc=; b=9ye8m+R+egKhjC5UJ+pb6xvl8IP230gTwbautYtnWhtxuD4VgdJgtFjSOfy8w1OnxjZ/Xfz/d 3/khw/OdTQlDHls8FP7JFJJ6nhA2eFmRHIk3RuxiJkK8AssUaCT5xFy X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791238190301624450 X-GMAIL-MSGID: 1791238190301624450 From: Yang Xiwen During boot, kernel complains: [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set Looking at GIC-400 datasheet, I believe this SoC is using a regular GIC-400 and the GICR space size should be 8 KB rather than 256B. With this patch: [ 0.000000] GIC: Using split EOI/Deactivate mode So this should be the correct fix. Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index ed1b5a7a6067..d01023401d7e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,7 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>; /* GICC */ #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; From patchwork Sun Feb 18 12:02:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Xiwen via B4 Relay X-Patchwork-Id: 202791 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp746851dyc; Sun, 18 Feb 2024 04:04:25 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWhPAAFS+9jLJhsIHclax+zb6bgawg05YPTU3s3i+BMdgPYXMdNflz6V4/1QM5G834WrlZKY3jTZ6Ek2U8Ahdxu6Q1sbA== X-Google-Smtp-Source: AGHT+IEilUnHgnjMPP7/dbCNYvd9Q1x9iMIzmvuLEkZhgntnoKwNrLOSNgE09FSAMrDpGjsKnCpb X-Received: by 2002:a17:90a:eb04:b0:299:6c50:c2a0 with SMTP id j4-20020a17090aeb0400b002996c50c2a0mr1714349pjz.23.1708257865120; Sun, 18 Feb 2024 04:04:25 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708257865; cv=pass; d=google.com; s=arc-20160816; b=hYQ3plRBF10fJqYy3Zh5Z3L8mdXxmdVAckJwHQx9Lm3smQFFJwoUEn6VLmbi09WIqv FfsMsa3flUn/U5PxqaQ8/vCybydu59GZ6fVlAYx/JAUb8zn8hlF/xUJTc5WmB9/yjv2T qKVoXibYCHa7P6WKJbGor7eXGICByPcGSwgyeNUgC5jE8pI6m7gkfHWsdz2FBLAxU7q/ eh32flNavoB6xU5Xw6Q8EnOm+EBwqUrnV5rYUJh5CDvkYnjIzWbBOLCoudOukRoY4ztc DTHaU23xPsZCQqRySqlxSA0yzp2toMCsCNl70pPHedgNtMOD2UslI6k1V7CfvrAR/tGf hiJg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=reply-to:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:subject:date:from:dkim-signature; bh=3DFSFX6xOmVard0tLEeZ0HKK2KOemEi2o75VeU03MRg=; fh=29BeSxQRolKTTenbNnypbAFTlVYixRCnPjbHsJYzT6k=; b=nq6XvNjQhdEX7+MtQgXOp+SMoTENQxCrB4KE+k91MPNEofbPbl7i5Bgk4UsHT2mjie LCWVHysqH6/kckoWtWD4me0F98+T/Y2XkE4Wi25dR5jdbNUesLbGypS+Vm7vDjT3pjXw NutuvQog664uV/v1ugkIOmZMpPRNCuZ2dYmIo4bQvwQIqh13TblcAtgZ/2YKlQDgNdIJ Vkj3sGMcXbNaxpxxZyRKPthpawXK3zb1poc6r+UOTN2Rt/g5zDk6YDn42RqlUwG3sAaI Jx8Pm0Jg0ZJJaIcGBcIAiezyFphhXwH6h9TdG7gCYh+g5mTJYAj1HJ5rEvXh4n7/cw/m JA4w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=C10tmYII; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-70380-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-70380-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Just like regular GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been verified. Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index d01023401d7e..fc64d2fa99eb 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,11 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x2000>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>, /* GICC */ + <0x0 0xf1004000 0x0 0x2000>, /* GICH */ + <0x0 0xf1006000 0x0 0x2000>; /* GICV */ + interrupts = ; #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; From patchwork Sun Feb 18 12:02:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Xiwen via B4 Relay X-Patchwork-Id: 202789 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp746706dyc; Sun, 18 Feb 2024 04:04:02 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCULuIEzNX6Lg5wHXxK+ZAbALl5OnPF/HGHKibICaq0tzDMXbsFNe3u7JEqK6M06UAsyq3zSMv1rU0YVSXqB/vpoQCjqBw== X-Google-Smtp-Source: AGHT+IGvqJTB2MljSrtY9WAvw4SOYabnYEnwVDnKqQCKmKBs5KTOqhPMgwokzQbPJMxCzf4kj2un X-Received: by 2002:ac8:7f8f:0:b0:42e:b75:a0ad with SMTP id z15-20020ac87f8f000000b0042e0b75a0admr895240qtj.25.1708257842560; Sun, 18 Feb 2024 04:04:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708257842; cv=pass; d=google.com; s=arc-20160816; b=XMqQdhk+SVD8u5XAWIy9/4AkWF9zWMPaiYua5Tyu3Hp/Kg3FL9AgQOwtIblCrFQw9w +g6nW3SZwvxK7Ynq5uxpoRO13dMlJRXNDooWIrhAduYsXr0T9oybB+LTe0ZKotI2fi2G eA6FWz3mqtIqGo0t9xqLVktm6aMtAdepmTTCT4/ulLa96maJ+IZJ4ihruH6dQ2EW7INT DeyAtS4MXgdU3c8k/eCwInVcVCd85tbqjEdZ2Z0DyKf9EYIWJ6AU98zwPp3x2X4nul5B TrKAGDVhaVKgvqI7DdFEBHqD7NOAbVOHXUSMdRo7LvTUuCObTMdV4tbuK9Uz6rXyB9WL gKag== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=reply-to:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:subject:date:from:dkim-signature; bh=nNJKlEb4fqHKH9YDsFRvt0IgpoqtitSbhbd4mrdTqi0=; fh=29BeSxQRolKTTenbNnypbAFTlVYixRCnPjbHsJYzT6k=; b=LIQ/ZB5fo/m0oR4Zh3hpmYb8qbS4HF2zPLQ9pa7TCdlUxEVu9IGPvisS70zbMXPgjr AQA1nLmuD3ZzEct2IhTdRTs0rs/NMPjMjqosnKV07mORNSXqa3hKlC6TK0Wr0vUZoPgd +cyuhSyIMGrSWz2h4FquXZjC0VDhLLMNVpTND5hqmgealK9/WUJf6feLY4SfwV+NF+4/ 7p0qzg0uSo8XX7nJ46JlMzA0ZnZZbbnOUxC/+Nvg9XytyhMVcxwkUPkW8AzWJU/u65IG 8XPuou560wg2IexwM+CPlrn92c+AmaztLclBzy+SNA6OndRwsJo+WCiljkS5DFIMTkhp 0r0w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=s5j4LxXL; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-70381-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-70381-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Sun, 18 Feb 2024 12:03:07 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 18 Feb 2024 20:02:52 +0800 Subject: [PATCH v2 3/3] arm64: dts: hi3798cv200: add cache info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240218-cache-v2-3-1fd919e2bd3e@outlook.com> References: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com> In-Reply-To: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708257770; l=2811; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=JVX6c8jTFahxkecrZwVOU639nIRHmAeZFLG8nHeqRQM=; b=JfVOap8CG+9J+E/Wm9alsBTwAWzwAa30YeKl9pEufes8+h0zju2JexaoXi9zJ24xOTA6Ym/tx 3BKeMaXqBtQA/Lc5JcMCrWHU37OQ1tA6/S3j7lG/WBT03JlR3QilC2D X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791238175396967258 X-GMAIL-MSGID: 1791238175396967258 From: Yang Xiwen During boot, the kernel complains: [ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0 So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1 i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache) With this patch, the line above is gone and the following info is added to the output of `lscpu`: Caches (sum of all): L1d: 128 KiB (4 instances) L1i: 128 KiB (4 instances) L2: 512 KiB (1 instance) Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index fc64d2fa99eb..0a9533786f50 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -31,6 +31,13 @@ cpu@0 { device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2_0>; }; cpu@1 { @@ -38,6 +45,13 @@ cpu@1 { device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2_0>; }; cpu@2 { @@ -45,6 +59,13 @@ cpu@2 { device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2_0>; }; cpu@3 { @@ -52,9 +73,25 @@ cpu@3 { device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2_0>; }; }; + L2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-size = <0x80000>; /* 512 KiB */ + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */