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Sun, 18 Feb 2024 09:40:34 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 18 Feb 2024 17:40:30 +0800 Subject: [PATCH 1/2] arm64: dts: hi3798cv200: Fix the size of GICR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240218-cache-v1-1-2c0a8a4472e7@outlook.com> References: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> In-Reply-To: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708249233; l=1243; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=cM/+jwZOd1PTjdjnQjIchbxxptzvx3CBS8/AnT/3vpc=; b=/A9JI75VcknvkbU5W9gkLRmoqf1WJh/ohHjKqGbIMBsKkkK/WPK5yfIjww3AcQbSkUzL8JDSV NrPoGdyLs04AXuPMwP/6CSlzS2G1hIP7BvdWXE43WyHj2CAK/4lqJ+l X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791229186952291280 X-GMAIL-MSGID: 1791229186952291280 From: Yang Xiwen During boot, kernel complains: [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set Looking at GIC-400 datasheet, I believe this SoC is using a regular GIC-400 and the GICR space size should be 8 KB rather than 256B. With this patch: [ 0.000000] GIC: Using split EOI/Deactivate mode So this should be the correct fix. Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index ed1b5a7a6067..d01023401d7e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,7 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>; /* GICC */ #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; From patchwork Sun Feb 18 09:40:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Xiwen via B4 Relay X-Patchwork-Id: 202761 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp705971dyc; Sun, 18 Feb 2024 01:41:09 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUDaHWIhi/WXB8HPq6LycKB3OBQf4CeFDrcSsr5cxddQxXnRuZ5w92MpTI9n8bB09lnkPy8WvLQs5sSVb78xGveRVM4GA== X-Google-Smtp-Source: AGHT+IE+RzESptzPLiaTZZhqD4ZpLFBF0WIywFJMO6wR1x0d8bAHqQyuDuS/ftHIjGJaiESj0FKG X-Received: by 2002:ac8:5d0c:0:b0:42c:826c:d2dd with SMTP id f12-20020ac85d0c000000b0042c826cd2ddmr13026878qtx.39.1708249269338; Sun, 18 Feb 2024 01:41:09 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708249269; cv=pass; d=google.com; s=arc-20160816; b=fjRQvjXwpu5QUpUwor5cmCTneI/oV6dHuThRszski3CgTpzyrVk4m+3384WMSGEv/v uOTXuHsAnYsgy/2MO0xH0Znm1lXf5r7mFU7IPi7F79IOmJicpIoLtjQgvR2EP4xAjGPk KMtCQI7wuIncOnLyuFbTi5ig1+v+0VRR645vJyRvTX0kXatU6hk30jAURpmHscXkT/LS eK8qiaxfOa3+OW06W7Q55eg7ioFTaUEpefvegytv6wg0NJcyLbFnMqJMm0hKR5P40IWN CxVniC8tm2817YzQFPBYL3+g47v6BEvvhjaqLnKszYy+k+CNoIfDlcBMcEq6oETbSi/F VCuQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=reply-to:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:subject:date:from:dkim-signature; bh=1AcreEIcHwwlr1OiFtSoJbWWQLZdpv1uvUU7PQWXbOA=; fh=29BeSxQRolKTTenbNnypbAFTlVYixRCnPjbHsJYzT6k=; b=hkfUSUizrh1VOH4FXnprzk6NYwU/suTg/KmR7bb7f6ZA8+OhIpQBFY9eP8xbv7DKDg 38+XX2eL8qn11LCKUR5nRR7ngt5QLjMBzc8Mk6SofJUtVnfvc4yy6Red9EmmsDbO4CKb 4ApEguZM7bhXDau1XMsIRJb7j0uvqe+0s3D3PPvaip7MRmkjRPubA0+nBoNK3heJvrHz jWI42Y58ufSR1EGOepPJ7tXuXnw6YXrhBgZPraMxJ47JEYR+ATBxQAl07RHI1VvXfTsn T2N5+eobEf0wVx49DruChwA6MMqPcUaI9mcZeMHZKEmMiwiwtXQ/N7GXMunE+XeOVQms WebA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=SCnzg6Dq; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-70321-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-70321-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Sun, 18 Feb 2024 09:40:34 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 18 Feb 2024 17:40:31 +0800 Subject: [PATCH 2/2] arm64: dts: hi3798cv200: add cache info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240218-cache-v1-2-2c0a8a4472e7@outlook.com> References: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> In-Reply-To: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708249233; l=2811; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=7KtnkY7Pm5plqx77OK2FVNdCRnse/+VsWvkr9ingato=; b=JgA/U1XbhkecOKg3NeY5nWpK5pQs6KzWIhJQ7X5xYdZ3SEesjg9+XYCBOp0+LuD/DF19H6XYU Vv1JSbzdVzpDkyQ+MyZfC9+r5HMNAtIuLJYhviNxsTYQACEzr1IuWHB X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791229185915408764 X-GMAIL-MSGID: 1791229185915408764 From: Yang Xiwen During boot, the kernel complains: [ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0 So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1 i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache) With this patch, the line above is gone and the following info is added to the output of `lscpu`: Caches (sum of all): L1d: 128 KiB (4 instances) L1i: 128 KiB (4 instances) L2: 512 KiB (1 instance) Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index d01023401d7e..33ded6b97f61 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -31,6 +31,13 @@ cpu@0 { device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2_0>; }; cpu@1 { @@ -38,6 +45,13 @@ cpu@1 { device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2_0>; }; cpu@2 { @@ -45,6 +59,13 @@ cpu@2 { device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2_0>; }; cpu@3 { @@ -52,9 +73,25 @@ cpu@3 { device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2_0>; }; }; + L2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-size = <0x80000>; /* 512 KiB */ + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */