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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g3-20020a170902740300b0017a0f71990dsi14200927pll.141.2022.11.16.02.45.06; Wed, 16 Nov 2022 02:45:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="lv8j/Vyg"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232401AbiKPKot (ORCPT + 99 others); Wed, 16 Nov 2022 05:44:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238605AbiKPKoU (ORCPT ); Wed, 16 Nov 2022 05:44:20 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0BBD326D8 for ; Wed, 16 Nov 2022 02:32:23 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id j15so29201134wrq.3 for ; Wed, 16 Nov 2022 02:32:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/17qFFdiyY8/qqzcwQc7JrCxEfqjOBVfmroYZxPEvcg=; b=lv8j/VygZ2Jknu5BYv9QAT2AkZ+ZRoYTxCuAFEx6BwPx8DuuVJ/dcSKBWoIa2+LGmZ qt8y8PRBhh0evs1Fl/qQZLo2W/TAQhDv9OyDHmUZlQHEa11GvmsFObj8Q1GAJ/IM02yV HSlPUHZJDzziRffY2guYgvP1+IrqRVK5Wh7PX5C+RAOeljyGkBB5P7vDIYLX8xWYIv99 wB8+6p1IOG572HZBPP9mHXc/Edol+Caj9TLbdoIuJ7WlTvmMUmVzLv3rmNLok9isycPr TQPVX8hvGSn5y166hyKG9s9uRR2/soflJ+PRQXwK1rP1+2sbapNPv4f69XiX983vVruZ 7Zwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/17qFFdiyY8/qqzcwQc7JrCxEfqjOBVfmroYZxPEvcg=; b=wk1se6Kd8dyTi3gW+41X7h8bHxZV8Z668MaYMZ194+4GAT0nXMmZeH8lkGrGbMJ7EM A4yjfSwrIYVAObez7aUEEufkp0uObIMMJVmPBMMGrL6DI/7NI8QKdHYon1lBwCVFpKwn tn+1QKJ28vQGdW975lQ402CXermjFMKzVogHsFXt15nHGHMfZwbWg+sxLKVahFpK9YKd o0Cw+vp/m5XTqAHuNThEtMrd1fRU1DWc7xrTB0Hc6zJmLHZX+83EbueVnNA2Ohj9y2t9 zFDNvFLMwpDFHJsHx+TS87jq74codKbtmK5YW0Znn0KM4/UJ1GMl1CG+TaQ8X8GMLTg2 6Vkw== X-Gm-Message-State: ANoB5pnkkH/i5+plEGJGWkZlWEFyousFlT2xuuXALNK5tSc8eF9K360A 1l8r9ac2/U5L1Ci6Mi5vQ2sdgQ== X-Received: by 2002:adf:f845:0:b0:236:7d20:cd63 with SMTP id d5-20020adff845000000b002367d20cd63mr12512055wrq.284.1668594742274; Wed, 16 Nov 2022 02:32:22 -0800 (PST) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id bh9-20020a05600005c900b0022e36c1113fsm15107032wrb.13.2022.11.16.02.32.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 02:32:21 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , "vkoul@kernel.org" , Srinivas Kandagatla Subject: [PATCH 01/10] dt-bindings: arm: qcom: Document SM8550 SoC and boards Date: Wed, 16 Nov 2022 12:31:37 +0200 Message-Id: <20221116103146.2556846-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221116103146.2556846-1-abel.vesa@linaro.org> References: <20221116103146.2556846-1-abel.vesa@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749649215152086376?= X-GMAIL-MSGID: =?utf-8?q?1749649215152086376?= Document the SM8550 SoC binding and the MTP board. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 7637cf27d799..a586a38c3461 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -68,6 +68,7 @@ description: | sm8250 sm8350 sm8450 + sm8550 The 'board' element must be one of the following strings: @@ -818,6 +819,11 @@ properties: - sony,pdx223 - const: qcom,sm8450 + - items: + - enum: + - qcom,sm8550-mtp + - const: qcom,sm8550 + # Board compatibles go above qcom,msm-id: From patchwork Wed Nov 16 10:31:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 20921 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp70142wru; Wed, 16 Nov 2022 02:45:43 -0800 (PST) X-Google-Smtp-Source: AA0mqf7dLK/iaqSrbsamA66y9KNndd6TmRQG+dfdAzsEwqgb7RJWx5OaHtw/Zz9NREvm6KBSfhDn X-Received: by 2002:a17:902:cf4c:b0:185:4703:9f5f with SMTP id e12-20020a170902cf4c00b0018547039f5fmr8563602plg.156.1668595542665; Wed, 16 Nov 2022 02:45:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595542; cv=none; d=google.com; s=arc-20160816; b=wsZe5FajXLf1qdQnnrCF6gnr94HftTuTT7drJo8rz83/ObPtYLbtRf9ACLOEE5U9hO f9zt4A/UFGbX3o/joWZOaSkvnojVF7OtPYIEd7RELQQ3REJ2VOgmEfzCmFiSAo4ytipC LaYNLA9W61ZRTcJ+zjiVP+Mv01otWIs1WgHZA5uWewWdWMH9sZ2veJ0DKuDs+mIXAnAp D6dLCpIw9CIwUAaWUPo88JazMwL43GYC7WQvHULxtqRDq1xFmTh58HECZg2ZXSRh+SN/ QoU7z/0hoOtie4k7HdksoRSu8kn63V2JwCk1clEfZXqNhnbhuTowF1gDuxgMgmzYonev IQYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uDuvHNY6/RgcsCirjd/1UySR0GEHvbrhOUfMHflal1M=; b=KM025nB2CO5sABgqUkHsDN7aShUw84tgGyUdbKRDyUep6yLEPL9EtRQxZlGpjDqQ8b bGw7TZ1THsnRrxR/ubxgsHaSQiQzIMA+Z8bDV+q1ZSaZi4HcjBZBcLTELI5Qz2B+hf2c rE7UrBNbY45UlAYSTTos2YYhBnD4G82wYTpCTEJTXlLEGpv7MQhSq8EnFS2IaahJaBj+ z4LQKNNI0yXjHKU0AlAdIp0OR3Y1kPgXo2eXiJTZxFIc2wc2kJK5hecyp2VnKcGLePcb mfqtLq8NAMyCM9OMVQBrd5aT0RZ30vfoYzaezu0kAFdqmW5etzF67KI6wC7snQ/arens wPpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IQnxo8UA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 3986 ++++++++++++++++++++++++++ 1 file changed, 3986 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8550.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi new file mode 100644 index 000000000000..07ba709ca35f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -0,0 +1,3986 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <76800000>; + }; + + pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + + ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000>; + }; + + ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000>; + }; + + ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <588>; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <2700>; + exit-latency-us = <3500>; + min-residency-us = <13959>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8550", "qcom,scm"; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,sm8550-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,sm8550-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp-region@80000000 { + reg = <0x0 0x80000000 0x0 0xa00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@80a00000 { + reg = <0x0 0x80a00000 0x0 0x400000>; + no-map; + }; + + hyp_tags_mem: hyp-tags-region@80e00000 { + reg = <0x0 0x80e00000 0x0 0x3d0000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@d8100000 { + reg = <0x0 0xd8100000 0x0 0x40000>; + no-map; + }; + + + hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { + reg = <0x0 0x811d0000 0x0 0x30000>; + no-map; + }; + + /* merged xbl_dt_log, xbl_ramdump, aop_image */ + xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { + reg = <0x0 0x81a00000 0x0 0x260000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ + aop_config_merged_mem: aop-config-merged-region@81c80000 { + reg = <0x0 0x81c80000 0x0 0x74000>; + no-map; + }; + + /* secdata region can be reused by apps */ + smem: smem-region@81d00000 { + compatible = "qcom,smem"; + reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg = <0x0 0x81f00000 0x0 0x20000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg = <0x0 0x82600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg = <0x0 0x82700000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { + reg = <0x0 0x82800000 0x0 0x4600000>; + no-map; + }; + + mpss_mem: mpss-region@8a800000 { + reg = <0x0 0x8a800000 0x0 0x10800000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { + reg = <0x0 0x9b000000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9b080000 { + reg = <0x0 0x9b080000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9b090000 { + reg = <0x0 0x9b090000 0x0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { + reg = <0x0 0x9b09a000 0x0 0x2000>; + no-map; + }; + + spss_region_mem: spss-region@9b100000 { + reg = <0x0 0x9b100000 0x0 0x180000>; + no-map; + }; + + /* First part of the "SPU secure shared memory" region */ + spu_tz_shared_mem: spu-tz-shared-region@9b280000 { + reg = <0x0 0x9b280000 0x0 0x60000>; + no-map; + }; + + /* Second part of the "SPU secure shared memory" region */ + spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { + reg = <0x0 0x9b2e0000 0x0 0x20000>; + no-map; + }; + + camera_mem: camera-region@9b300000 { + reg = <0x0 0x9b300000 0x0 0x800000>; + no-map; + }; + + video_mem: video-region@9bb00000 { + reg = <0x0 0x9bb00000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp-region@9c200000 { + reg = <0x0 0x9c200000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9c900000 { + reg = <0x0 0x9c900000 0x0 0x2000000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { + reg = <0x0 0x9e900000 0x0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { + reg = <0x0 0x9e980000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@9ea00000 { + reg = <0x0 0x9ea00000 0x0 0x4080000>; + no-map; + }; + + /* uefi region can be reused by apps */ + + /* Linux kernel image is loaded at 0xa8000000 */ + + mpss_dsm_mem: mpss-dsm-region@d4d00000 { + compatible = "qcom,mpss-dsm-mem"; + reg = <0x0 0xd4d00000 0x0 0x3300000>; + no-map; + }; + + tz_reserved_mem: tz-reserved-region@d8000000 { + reg = <0x0 0xd8000000 0x0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@d8140000 { + reg = <0x0 0xd8140000 0x0 0x1c0000>; + no-map; + }; + + qtee_mem: qtee-region@d8300000 { + reg = <0x0 0xd8300000 0x0 0x500000>; + no-map; + }; + + ta_mem: ta-region@d8800000 { + reg = <0x0 0xd8800000 0x0 0x8a00000>; + no-map; + }; + + tz_tags_mem: tz-tags-region@e1200000 { + reg = <0x0 0xe1200000 0x0 0x2740000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf-region@e6440000 { + reg = <0x0 0xe6440000 0x0 0x279000>; + no-map; + }; + + trust_ui_vm_mem: trust-ui-vm-region@f3600000 { + reg = <0x0 0xf3600000 0x0 0x4aee000>; + no-map; + }; + + trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { + reg = <0x0 0xf80ee000 0x0 0x1000>; + no-map; + }; + + trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { + reg = <0x0 0xf80ef000 0x0 0x9000>; + no-map; + }; + + trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { + reg = <0x0 0xf80f8000 0x0 0x4000>; + no-map; + }; + + trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { + reg = <0x0 0xf80fc000 0x0 0x4000>; + no-map; + }; + + trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { + reg = <0x0 0xf8100000 0x0 0x100000>; + no-map; + }; + + oem_vm_mem: oem-vm-region@f8400000 { + reg = <0x0 0xf8400000 0x0 0x4800000>; + no-map; + }; + + oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { + reg = <0x0 0xfcc00000 0x0 0x4000>; + no-map; + }; + + oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { + reg = <0x0 0xfcc04000 0x0 0x100000>; + no-map; + }; + + hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { + reg = <0x0 0xfce00000 0x0 0x2900000>; + no-map; + }; + + hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { + reg = <0x0 0xff700000 0x0 0x100000>; + no-map; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,sm8550-gcc"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk", + "pcie_1_phy_aux_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_1_phy_aux_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; + reg = <0x0 0x00408000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; + #dma-cells = <3>; + reg = <0x0 0x00800000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x3e>; + iommus = <&apps_smmu 0x436 0x0>; + status = "disabled"; + }; + + qupv3_id_1: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x423 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c8: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi8: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi9: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi10: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi11: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c12: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi12: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c13: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00894000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi13: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c15: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0089c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi15: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; + #dma-cells = <3>; + reg = <0x0 0x00a00000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x1e>; + iommus = <&apps_smmu 0xb6 0x0>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xa3 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; + interconnect-names = "qup-core"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c0: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi0: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi3: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi4: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_data_clk>; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_data_clk>; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a98000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart7: serial@a9c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_default>; + interrupts = ; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,sm8550-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x13080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,sm8550-config-noc"; + reg = <0x0 0x01600000 0x0 0x6200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,sm8550-system-noc"; + reg = <0x0 0x01680000 0x0 0x1D080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,sm8550-pcie-anoc"; + reg = <0x0 0x016c0000 0x0 0x12200>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm8550-aggre1-noc"; + reg = <0x0 0x016e0000 0x0 0x14400>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm8550-aggre2-noc"; + reg = <0x0 0x01700000 0x0 0x1E400>; + #interconnect-cells = <2>; + clocks = <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,sm8550-mmss-noc"; + reg = <0x0 0x01780000 0x0 0x5B800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible = "qcom,sm8550-tcsrcc", "syscon"; + reg = <0x0 0x01fc0000 0x0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_PAD_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,sm8550-lpass-lpiaon-noc"; + reg = <0x0 0x07400000 0x0 0x19080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_lpicx_noc: interconnect@7430000 { + compatible = "qcom,sm8550-lpass-lpicx-noc"; + reg = <0x0 0x07430000 0x0 0x3A200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,sm8550-lpass-ag-noc"; + reg = <0x0 0x07e40000 0x0 0xE080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x540 0x0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd SM8550_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0x0>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8550-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, + <125 63 1>, <126 716 12>, + <138 251 5>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c271000 { + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg = <0 0x0c271000 0 0x1000>, /* TM */ + <0 0x0c222000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c272000 { + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg = <0 0x0c272000 0 0x1000>, /* TM */ + <0 0x0c223000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c273000 { + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg = <0 0x0c273000 0 0x1000>, /* TM */ + <0 0x0c224000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c3f0000 0x0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x4000000>, + <0x0 0x0c440000 0x0 0x80000>, + <0x0 0x0c4c0000 0x0 0x20000>, + <0x0 0x0c42d000 0x0 0x4000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + qcom,bus-id = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sm8550-tlmm"; + reg = <0x0 0x0f100000 0x0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + wakeup-parent = <&pdc>; + + hub_i2c0_data_clk: hub-i2c0-data-clk-state { + scl-pins { + pins = "gpio17"; + function = "i2chub0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio16"; + function = "i2chub0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + hub_i2c1_data_clk: hub-i2c1-data-clk-state { + scl-pins { + pins = "gpio19"; + function = "i2chub0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio18"; + function = "i2chub0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + hub_i2c2_data_clk: hub-i2c2-data-clk-state { + scl-pins { + pins = "gpio21"; + function = "i2chub0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio20"; + function = "i2chub0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + hub_i2c3_data_clk: hub-i2c3-data-clk-state { + scl-pins { + pins = "gpio23"; + function = "i2chub0_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio22"; + function = "i2chub0_se3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + hub_i2c4_data_clk: hub-i2c4-data-clk-state { + scl-pins { + pins = "gpio5"; + function = "i2chub0_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio4"; + function = "i2chub0_se4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + hub_i2c5_data_clk: hub-i2c5-data-clk-state { + scl-pins { + pins = "gpio7"; + function = "i2chub0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio6"; + function = "i2chub0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + hub_i2c6_data_clk: hub-i2c6-data-clk-state { + scl-pins { + pins = "gpio9"; + function = "i2chub0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio8"; + function = "i2chub0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + hub_i2c7_data_clk: hub-i2c7-data-clk-state { + scl-pins { + pins = "gpio11"; + function = "i2chub0_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio10"; + function = "i2chub0_se7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + hub_i2c8_data_clk: hub-i2c8-data-clk-state { + scl-pins { + pins = "gpio207"; + function = "i2chub0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio206"; + function = "i2chub0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + hub_i2c9_data_clk: hub-i2c9-data-clk-state { + scl-pins { + pins = "gpio85"; + function = "i2chub0_se9"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio84"; + function = "i2chub0_se9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio95"; + function = "pcie0_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio97"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio98"; + function = "pcie1_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + scl-pins { + pins = "gpio29"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio28"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + scl-pins { + pins = "gpio33"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio32"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + scl-pins { + pins = "gpio37"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio36"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + scl-pins { + pins = "gpio41"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio40"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + scl-pins { + pins = "gpio45"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio44"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + scl-pins { + pins = "gpio53"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio52"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + scl-pins { + pins = "gpio49"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio48"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + scl-pins { + pins = "gpio57"; + function = "qup2_se0_l1_mira"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio56"; + function = "qup2_se0_l0_mira"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + scl-pins { + pins = "gpio61"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio60"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + scl-pins { + pins = "gpio65"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio64"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + scl-pins { + pins = "gpio69"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio68"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + scl-pins { + pins = "gpio3"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio2"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + scl-pins { + pins = "gpio81"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio80"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + scl-pins { + pins = "gpio106"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + + sda-pins { + pins = "gpio72"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c-pull; + }; + }; + + qup_spi0_cs: qup-spi0-cs-state { + cs-pins { + pins = "gpio31"; + function = "qup1_se0"; + }; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + clk-pins { + pins = "gpio30"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio28"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio29"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi1_cs: qup-spi1-cs-state { + cs-pins { + pins = "gpio35"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + clk-pins { + pins = "gpio34"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio32"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio33"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi2_cs: qup-spi2-cs-state { + cs-pins { + pins = "gpio39"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + clk-pins { + pins = "gpio38"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio36"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio37"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi3_cs: qup-spi3-cs-state { + cs-pins { + pins = "gpio43"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + clk-pins { + pins = "gpio42"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio40"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio41"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi4_cs: qup-spi4-cs-state { + cs-pins { + pins = "gpio47"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + clk-pins { + pins = "gpio46"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio44"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio45"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi5_cs: qup-spi5-cs-state { + cs-pins { + pins = "gpio55"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + clk-pins { + pins = "gpio54"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio52"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio53"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi6_cs: qup-spi6-cs-state { + cs-pins { + pins = "gpio51"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + clk-pins { + pins = "gpio50"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio48"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio49"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi8_cs: qup-spi8-cs-state { + cs-pins { + pins = "gpio59"; + function = "qup2_se0_l3_mira"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + clk-pins { + pins = "gpio58"; + function = "qup2_se0_l2_mira"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio56"; + function = "qup2_se0_l0_mira"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio57"; + function = "qup2_se0_l1_mira"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi9_cs: qup-spi9-cs-state { + cs-pins { + pins = "gpio63"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + clk-pins { + pins = "gpio62"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio60"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio61"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi10_cs: qup-spi10-cs-state { + cs-pins { + pins = "gpio67"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + clk-pins { + pins = "gpio66"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio64"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio65"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi11_cs: qup-spi11-cs-state { + cs-pins { + pins = "gpio71"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + clk-pins { + pins = "gpio70"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio68"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio69"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi12_cs: qup-spi12-cs-state { + cs-pins { + pins = "gpio119"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + clk-pins { + pins = "gpio118"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio2"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio3"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi13_cs: qup-spi13-cs-state { + cs-pins { + pins = "gpio83"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + clk-pins { + pins = "gpio82"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio80"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio81"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi15_cs: qup-spi15-cs-state { + cs-pins { + pins = "gpio75"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + clk-pins { + pins = "gpio74"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + miso-pins { + pins = "gpio72"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + mosi-pins { + pins = "gpio106"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qup_uart7_default: qup-uart7-default-state { + rx-pins { + pins = "gpio27"; + function = "qup1_se7"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio26"; + function = "qup1_se7"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8550-smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ + <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17140000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x17420000 0x0 0x1000>; + ranges = <0 0 0 0x20000000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x17423000 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x17425000 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x17427000 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x17429000 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x1742b000 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x1742d000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>, + <0x0 0x17a30000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm8550-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sm8550-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17D91000 0x0 0x1000>, + <0x0 0x17D92000 0x0 0x1000>, + <0x0 0x17D93000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; + #freq-domain-cells = <1>; + }; + + pmu@240b6400 { + compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; + reg = <0x0 0x240b6400 0x0 0x600>; + interrupts = ; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <4577000>; + }; + opp-1 { + opp-peak-kBps = <7110000>; + }; + opp-2 { + opp-peak-kBps = <9155000>; + }; + opp-3 { + opp-peak-kBps = <12298000>; + }; + opp-4 { + opp-peak-kBps = <14236000>; + }; + opp-5 { + opp-peak-kBps = <16265000>; + }; + }; + }; + + pmu@24091000 { + compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0x0 0x24091000 0x0 0x1000>; + interrupts = ; + interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2086000>; + + }; + opp-1 { + opp-peak-kBps = <2929000>; + + }; + opp-2 { + opp-peak-kBps = <5931000>; + + }; + opp-3 { + opp-peak-kBps = <6515000>; + + }; + opp-4 { + opp-peak-kBps = <7980000>; + + }; + opp-5 { + opp-peak-kBps = <10437000>; + + }; + opp-6 { + opp-peak-kBps = <12157000>; + + }; + opp-7 { + opp-peak-kBps = <14060000>; + + }; + opp-8 { + opp-peak-kBps = <16113000>; + + }; + }; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,sm8550-gem-noc"; + reg = <0x0 0x24100000 0x0 0xBB800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system-cache-controller@25000000 { + compatible = "qcom,sm8550-llcc"; + reg = <0x0 0x25000000 0x0 0x800000>, + <0x0 0x25800000 0x0 0x200000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,sm8550-nsp-noc"; + reg = <0x0 0x320C0000 0x0 0xE080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu3-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + cpu3_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + cpu3_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + cpu4_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + cpu4_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + cpu5_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + cpu5_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + cpu6_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + cpu6_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + cpu7_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-middle-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + cpu7_middle_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + + trips { + cpu7_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cdsp0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp0_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp1_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp2_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp3-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp3_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + ddr_config0: ddr0-config { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss0_config0: mdmss0-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss0_config1: mdmss0-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss1_config0: mdmss1-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss1_config1: mdmss1-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss2_config0: mdmss2-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss2_config1: mdmss2-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss3_config0: mdmss3-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss3_config1: mdmss3-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 14>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu0_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu1_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu2_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu3_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu4_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu5_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-6-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu6_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-7-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu7_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Wed Nov 16 10:31:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 20917 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp70042wru; Wed, 16 Nov 2022 02:45:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf62M+51C/Zip6S/b509EVRgJ/nXzxkNxjvHsTIPqSF+5oXd6L0Y4whlBTLUkT5ySD1GmEzC X-Received: by 2002:a65:4c88:0:b0:476:cb2a:b99b with SMTP id m8-20020a654c88000000b00476cb2ab99bmr5071201pgt.436.1668595526795; Wed, 16 Nov 2022 02:45:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595526; cv=none; d=google.com; s=arc-20160816; b=dZytXAEp80i/3qvahE9bJrn7Kb/c2A3kxvVPkWLWu2BoNTzyhja0pHu47JMwGrbS8N /WymXZcg3701AphQsAW4BB/GUe0jcLzlFiYQmmxPOa93LvuPQToA+YkGaY3YSoC/Fmac XwMhjd2t2id4ABplI+u16F61gg2ozuRBIqQ8QbTBDODD7/MA9vneFXnnbFaNuAsZP8PT Lasp1IqQvS4PFVTvQYoQaYK0wIIJo6hL1P4v//o50rCrAh36kpB1LksF5jqFcVqovlxa r2YAhXjXkUmYi/sJZMvEWxTl8edAAl7mJ92uOz6HM0QPnXoYYNy0Cy3Hoc1396+CE629 A1zw== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id a11-20020a170902eccb00b0017f8290fcf0si16881298plh.272.2022.11.16.02.45.13; Wed, 16 Nov 2022 02:45:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NaIxLKZF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238876AbiKPKoz (ORCPT + 99 others); Wed, 16 Nov 2022 05:44:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232883AbiKPKoU (ORCPT ); Wed, 16 Nov 2022 05:44:20 -0500 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84EAA326DE for ; Wed, 16 Nov 2022 02:32:25 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id p16so11570570wmc.3 for ; Wed, 16 Nov 2022 02:32:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hN+FF5b10U9u5b3X80NCWb//I7PpVmPUTmgHrwmcTRM=; b=NaIxLKZFDN3yFP5TrGsVbGy/qkr9dfFF6m7hCwNGLb8cSHiD0ixYkl+dW8QGQ5cd0b KQQc1PmHUJuz9kupK3T2hOM4HCwijx/YR6IKXOzvYDMMWvcAvVSzFoeZ6zjeer7MNf3d 5YAHDbbgw3B0QA42zMfgzzSNjH9vArSnqRPvH3tpCcF891XM7wnHsfQRHA4C1hV9CsAh rRyoAagDztBYnSMHf6qO0ypahum3CDMuLNSPdXIDkE5ceolMdea2mKn0S6HQcxIXAMof xAq+xoo4BL46ZbJfoH/kL3kajaKuLSZAvqzaFIsiF6l6U6LwQQdMvc39Jx4mveyyiDqs uyKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hN+FF5b10U9u5b3X80NCWb//I7PpVmPUTmgHrwmcTRM=; b=Hx/B43ySxB+dw5zlZdcGzuQ5NkE/5qdT8THDKGw4SWAAR5ihyJUS1rUqMc6gfsXNQy mAhz/5U/jOwedPADnYbd2Mn1+S+7Og+KgUYNSUFrF7cFyG30x3uPc7sqXt95oG7wEv9A PHrwjUNGXTVc6yLSXf52Q23+/wmONyBzaodbFotsuA21O4clKaczRcb2o9MVnIhZlbl7 4oIIc89kh5XH3fHx3I3sIqRsF6uxFy6bZii7MINPkx9sj5qiYgBYXuGor72AENvlfo3u hlVbIWyHjg4U06bw1u+oW1A4y/LAImElSeskt68NxnOQYLEqArWXoqIqmwgusY795wot cUVw== X-Gm-Message-State: ANoB5pmKkwiMSs6N9PIs6hebtJU7tWZWGTujP3PlpX/J4wEV5sEb6SXg tr4SfeCsGy+55NHLPyOFTutSaw== X-Received: by 2002:a1c:e908:0:b0:3b3:3084:5ddb with SMTP id q8-20020a1ce908000000b003b330845ddbmr1636214wmc.108.1668594745056; Wed, 16 Nov 2022 02:32:25 -0800 (PST) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id bh9-20020a05600005c900b0022e36c1113fsm15107032wrb.13.2022.11.16.02.32.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 02:32:24 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , "vkoul@kernel.org" , Srinivas Kandagatla Subject: [PATCH 03/10] arm64: dts: qcom: Add pm8010 pmic dtsi Date: Wed, 16 Nov 2022 12:31:39 +0200 Message-Id: <20221116103146.2556846-4-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221116103146.2556846-1-abel.vesa@linaro.org> References: <20221116103146.2556846-1-abel.vesa@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749649223459856104?= X-GMAIL-MSGID: =?utf-8?q?1749649223459856104?= From: Neil Armstrong Add nodes for pm8010 in separate dtsi file. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8010.dtsi | 84 ++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8010.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8010.dtsi b/arch/arm64/boot/dts/qcom/pm8010.dtsi new file mode 100644 index 000000000000..0ea641e12209 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8010.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8010-m-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8010_m_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8010-n-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8010_n_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8010_m: pmic@c { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_m_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; + + pm8010_n: pmic@d { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xd SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_n_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; +}; From patchwork Wed Nov 16 10:31:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 20918 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp70100wru; Wed, 16 Nov 2022 02:45:37 -0800 (PST) X-Google-Smtp-Source: AA0mqf4hGm87NDFRN5hPlobeUV3ukWacTm2+Edsq8/Loz/Ko42qtrD+lPyocpEwiJHJA4r8rAjFx X-Received: by 2002:a17:90a:d984:b0:213:d1d5:d661 with SMTP id d4-20020a17090ad98400b00213d1d5d661mr3214041pjv.43.1668595537088; Wed, 16 Nov 2022 02:45:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595537; cv=none; d=google.com; s=arc-20160816; b=HLWtv2Pdq0HgvnX2RXSE4PP7TSWAtFmdljxWSv11WIKgfyxMb1+EOANqgzJM6jRudS IUha/pkOPrYQqcRhVofntFAO5JL3tfog11YiziGgLgDrjgF2zK6GFabSTNTpFzdzMbn5 6JGwLH+9ej51LiCGolKZZ0dkfD5CJ8n295HqQzvC2T8jOUovAaguTBPp83NGNxypZwLT Fta2CLeM2O6xexDEviH2yRC572n34E0q7aelSgzchEsgD+7CS/RNzpvMYyMc5ZVyRqwu xAJf9NZ8bGsEG2ZYOmfTmzCI5TXphPsv9ZpvlyIcgPBZtsb8dy6jrjvZ7jCOo9BCYvP1 0tLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iftMMDgL5S/VcToy3kI7H5qJYfE9y0xN9U7Vhz0XQVE=; b=sn2XHE/TBI7tegfEOjiQckgGuzUlq8nM93AqFw5DOnpnZEm5Z/CLtbiBKRcX1YY3Wm +MU6D81mawgnBnhuCNB8YVvFauL8VYrPO0ruvwc6v5aaYMdEgsm3mXHWUFe1BSuOrN5K 5BL6yoLSI1jLSaFnDjMyYQayAwEjIzVKfrOCJKkMXjVSOrbxzYqB7xi4h7ESuv1OVcmY biQwr1J6anVHlJ4Barg/6bs1VzUp06fKYRKbJaVYljtrxvAtocjQu1AjRRQiCdzqhvbJ zhWLuupPyPYJlBUHzEvLu4WJV7srtAbCXTcqJJH83AudMJL8Rc1+zKT/H2q/r3Kpl7L2 bjJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jrNZFvP9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8550.dtsi | 59 ++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8550.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi new file mode 100644 index 000000000000..46396ec1a330 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8550-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550: pmic@1 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550_gpios: gpio@8800 { + compatible = "qcom,pm8550-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From patchwork Wed Nov 16 10:31:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 20919 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp70123wru; Wed, 16 Nov 2022 02:45:40 -0800 (PST) X-Google-Smtp-Source: AA0mqf6/dETDiO4yGLM/Urjit+Qg98QKtwLZxziPeW1zBNIkz60V/PdWcwoQOY77Zh5iLJEACh4x X-Received: by 2002:a17:90a:3e47:b0:213:1a9f:8d72 with SMTP id t7-20020a17090a3e4700b002131a9f8d72mr3156839pjm.155.1668595540554; Wed, 16 Nov 2022 02:45:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595540; cv=none; d=google.com; s=arc-20160816; b=iPEY1SvIaeVKQtR2K4yV2IQ6fbO6FM57u0XYoOevL50ML7AVZj2PGE8CO2OtabERI0 3IlFsL0Qp4JAWDUgLao4KR7FQcCZ72cSzi36FgVlfn5oXHfxB0i0vtU8m/ovU0iC1W52 +RpDHOKZLnFLSaDEc6AAu7v/KuqrUI3Y/DQe+toKN7g5tCLNWPbl2pHCb/T+u8l9BvLW 346Bj7eA0fBlYmBKJwukw57bkU8FqkpANOFTvWNHP4C4/Sx+rOks1R0vf3mE+eZpbQaG mtciH0TQpIQ8Xr0H+4jH2e5CWRgyHb9WyzjmqIQ6QvWjgzIyJ9YzveQv3NpuHVjhtm+6 te+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VBLdk6CIr4nsexgTsIaAvKj9UzU1NeK6BDO+l9f0nh0=; b=qfFwpbV1wwNqHcCLTDfjIA/DcUXrhiV2Noxo/eQoqASMhc7brORSsSoUMYAJ6LOeN5 NBFdeJkM6QjPeEWaGkn0eXpIq193KoX2gcd+5NBP3UmBJEJnTeG/Kv4zvFzgPjCbIxgm rVsZzuGF4TkhGRUiGHIf6Z3sjGEh651qr1GIePUdU3/5bwFDmX/x3DIDainSzy3TsCYy xkUH+oo6XhGyDjPCVlO8uImvB83DgWFz0wT7RnqirAN4jxuq4CBqEJOM+0UycPvtAsgO p3bVnPhWrFFNux0fFWDeXnvjGf4drGFPNFrzshzju/aQ9tkXod6sSyDOCfGDRqHFa4D3 Jj0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RA75zzhd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8550b.dtsi | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8550b.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qcom/pm8550b.dtsi new file mode 100644 index 000000000000..16bcfb64d735 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8550b-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550b_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550b: pmic@7 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550b_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550b_gpios: gpio@8800 { + compatible = "qcom,pm8550b-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550b_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From patchwork Wed Nov 16 10:31:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 20920 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp70149wru; Wed, 16 Nov 2022 02:45:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf4q76N275Pl81cYnKyY//3cNe1981A7d7oB1X9islmU4ndVy8OMNxN4qVJ94HwmeI2oIPkJ X-Received: by 2002:a05:6a00:8cc:b0:56c:ba99:8735 with SMTP id s12-20020a056a0008cc00b0056cba998735mr22232303pfu.15.1668595543948; Wed, 16 Nov 2022 02:45:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595543; cv=none; d=google.com; s=arc-20160816; b=tm8RBslKS/SKqcq27yGhr/P3ZuMK0+enp3+iQ00ncjzjA9TD05QEjxNHKC/VjkEDeW pr+HkxfGDgG3V61/nF4Eb6qKBlSWaxmbRSFxEJFIUIf2sivHnDG1h1JPhKQUiUOfqKzd /9lBtgmg5TWuBcWIBbd0gSddJLhhmwj+Jjyw8K8UHMTtLEGfWX4vXIwPWjxvBtVoxW27 6pAcE6xaCLw/S2b/XHWllKG/TxN3wYKiia5WuoX/9PHff4hvyXr4Hl7LJ8mYnDoVy5TQ OBQ3+5Z83Q2Hy663aNW35NLLDK9kpR3hGJ8FfjWlk4VuZyTAHhvAKqyYgqmR/yT/fVC6 AAdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jXGEEgZKJBWa8C/rhY3g+R200GQq5Ds7ySOfHwjfhow=; b=DW28b/sCNAtnkOW3lPUqqTbMKCJU5GApfXAn4ficooExeUSmIP5H4FWMMc1nNK68dO 4iiyjLJhJeLtmGGYQ2qNXXF3s7VVq7HW1MR+3MI8p6HriA74/NjjwomvbAnywSiGNQhH 0ZWm2Y3lkTJ1bKGIWeWKb2bI9PuT/P7PNqIbtER7Ie9iOYgEokJAhVtqe7TnJNtRgzAy zbevtfTytymuDPMvQC0EwjxR6Jz5Lki2N8PGUVRJS1hJqvDqNGNML+9qp3G0bkiybYqL dVfcTksGsSHAE6IRohKRWawkQXnhLPlXhLzowI/EkjjSbRuw0OmJdavlr+XaJiJcfGVk bg3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qHqSZfWZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 59 ++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8550ve.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi new file mode 100644 index 000000000000..c47646a467be --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8550ve-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550ve_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550ve: pmic@5 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550ve_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550ve_gpios: gpio@8800 { + compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550ve_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From patchwork Wed Nov 16 10:31:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 20922 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp70231wru; Wed, 16 Nov 2022 02:45:57 -0800 (PST) X-Google-Smtp-Source: AA0mqf6bLeKfwTaOJl62fGWApe53hw3zcT/Q0Ue6yXI2zAtnOEFqMC84UGX5j6Xk4LnB9c7KtYGJ X-Received: by 2002:a17:902:bc41:b0:177:ed70:70ff with SMTP id t1-20020a170902bc4100b00177ed7070ffmr8474229plz.28.1668595557281; Wed, 16 Nov 2022 02:45:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595557; cv=none; d=google.com; s=arc-20160816; b=i/PVn1c7nCNWZSes+njAg6qgtqH6gVaeTVxbBra3vO9fZTBw1kz8JJxTfnQz06PGnU cHwo7fD13h71TsnSHIlZxM+FwPMK02F8Svx685W7gaMFs6vtGMqGx5kbmHvBO1AIzq9q 5C4bS05ehtQua/QfcxPp08Zw7/55hydsFU8dKTRcZQGa2JCDvaZgqM4G+y9waG04B103 hKAm57W860g8tzBqaEaJt1MVG0Dnj1C9ZAcy8PyoypObb6qNOWrxR0UoLwuvtXm6iTvs YDKAIBFGtdumiUD/gstenO+k0tGW3rmTseucWKRo+VIUWQuCvkbcQOm0QL43EHk3C8hc Sjew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GfhVZ/BVYLN1ISOzaAC+apO93yea8c8znHb9gCW91uc=; b=JzqowjjYZVYOXMHy2K2Xh/ywZPsJIryIAtq1Z06FLdxvkq0uUl4zA+gql6ks9KpDj6 5BjiR5BDWjwweDzF7elTnIrDj4ShCEAhIuYfpM33ll5dT4LEUyrH9FtNpsx1ama6j42c ysWu5+0tzqNrLDsxsDNwRShy0a9jkyLgMRju7fxWCCeI4fRIpEwb1OBzSxr0cdoSYQrK gj9ut19hEahL5aBc3+lV9xP5QGUEzqluUiSZwYJ0vb7XCXfBPoSMnx7j+P1CZmBHCxG5 2WSIlYgp+RtQTgP/430mInYH0CgRR5Gu/wPUvrSSi7H8vBNS2rRIk0Yigs4wfqUbpnd9 WCQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FYNQPCkj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 194 +++++++++++++++++++++++++ 1 file changed, 194 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8550vs.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi new file mode 100644 index 000000000000..97b1c18aa7d8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8550vs-c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_c_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550vs-d-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_d_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550vs-e-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_e_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550vs-g-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_g_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550vs_c: pmic@2 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_c_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_c_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_c_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_d: pmic@3 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_d_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_d_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_d_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_e: pmic@4 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_e_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_e_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_e_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_g: pmic@6 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_g_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_g_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_g_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From patchwork Wed Nov 16 10:31:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 20923 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp70267wru; Wed, 16 Nov 2022 02:46:03 -0800 (PST) X-Google-Smtp-Source: AA0mqf47vtFcSEUN41pWOQYQEad68gS91nbgOy13alxeWjJ5OOcidH9yo4FiTKBOn7VaKb+orGj5 X-Received: by 2002:a17:903:445:b0:186:95ca:1e4c with SMTP id iw5-20020a170903044500b0018695ca1e4cmr8490264plb.13.1668595562909; Wed, 16 Nov 2022 02:46:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595562; cv=none; d=google.com; s=arc-20160816; b=MqJX/6j7nTRMC4UP+ZHR0eseyLHEFdVn4IqnXDZyfAxzwkCUIC7CAkDa5G2S+EZJKG axu3jIS9An8EX/hzhOTrdHQx7T1F4p1jsQy4C48Kd8mbje5p+xN8SMUE82vt0z7emRm6 2WmvcvF4mh9DZqNW63Y6pT2RPcOpi8ySEp+RV4psYlJcjjz/GtguTaDD3pOlIL95cdBE VQq0bWjrmuhdBMGb6is50+uuNzYFnU2bXh3XDk5yYFBhRQVSmqiMaYW5GJ5yhe0CbCmG lfqQ6C56TDs8THqvr2YqD1f/Lapd/a/M/O5D8KFT+3pt19QZxWhRk9M2A4ckHAKg601k Zrfw== ARC-Message-Signature: i=1; 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Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmk8550.dtsi | 54 +++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmk8550.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi new file mode 100644 index 000000000000..1f707202f5da --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include + +&spmi_bus { + pmk8550: pmic@0 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8550_pon: pon@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + status = "disabled"; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8550_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + pmk8550_gpios: gpio@8800 { + compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; + reg = <0xb800>; + gpio-controller; + gpio-ranges = <&pmk8550_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From patchwork Wed Nov 16 10:31:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 20924 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp70312wru; Wed, 16 Nov 2022 02:46:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf4f+m3k4ofS9iKMVsixxSZmo0lmdCmJjS+RYH0sCbsIytRoAluezJXHLNAunYVC3pwjt8B1 X-Received: by 2002:aa7:95bb:0:b0:571:3fb3:9b5f with SMTP id a27-20020aa795bb000000b005713fb39b5fmr22298719pfk.86.1668595571515; Wed, 16 Nov 2022 02:46:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595571; cv=none; d=google.com; s=arc-20160816; b=O/Ex9BbIP30fybn94uNmUv9jTrvP0FDHINDyJDMDMSNoHBmHJF8RptGJuXR9i9owzE vfKXjvZ+PtyhQi4gsZgq88pm5MqpMOvKKb+Voxjj2jkMg6t+wjJ0YWSgOj+UZ4C7GxSk ngceAGah9J46mrK52yfhNUZWfdMLcNLIKR147im0wUIhXbx/oGTdfASt0IeA3r1MGLFY +zz0azH+yMHMKQ3elhMXTXnTMmokHj9iEjZbqQyp7cca1P9b4HKmvzTqTH/QXDWXshT7 dE/shvBffT5FCVA4r/RX+3Dt/kOMGiM1G/5rRsOG3ZzzQbErdyrk+yB01sr8RMm3k2Zx nIHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=R9i0aUERYAp64Dg3f9TW8aPPux8LTTvHSLBDJ/TZVE4=; b=WFfgwCUccmpyOJuC1fvalONctS3AMWhXkGcAp1hLa5KaM6SiC5kxwc+CHEynUHSpmk IA2M/TpIV0PZKdJLuDCsyR1CUDlcW07QZl7Z6M/Y715nXkDn/Z8C5w1rSiAHSgqb4yFI k2hwL3wR6fyeG6wpYdJ3iHV4FhH7lprK3kmJ/5SHCxcHmoq/m1p+mIm4BJCvo9GghT6A boKLOU/igpKdFu4uA/+S0FIiFsiWgiWJsWhCp2ifLOvQgrqp0a5+pH5nC1s9arC9ag/x F7XWNCKeBzOeLTJ9Hnq9oNPyikx0x2LG06u4mGP4BesCBq2xdO3BPaW+cGXh9TtVRudr 6cag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S3vzocug; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmr735d.dtsi | 104 ++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmr735d.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmr735d.dtsi b/arch/arm64/boot/dts/qcom/pmr735d.dtsi new file mode 100644 index 000000000000..41fb664a10b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmr735d.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pmr735d-k-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmr735d_k_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmr735d-l-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmr735d_l_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pmr735d_k: pmic@a { + compatible = "qcom,pmr735d", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735d_k_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735d_k_gpios: gpio@8800 { + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735d_k_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmr735d_l: pmic@b { + compatible = "qcom,pmr735d", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735d_l_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735d_l_gpios: gpio@8800 { + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735d_l_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From patchwork Wed Nov 16 10:31:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 20925 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp70336wru; Wed, 16 Nov 2022 02:46:15 -0800 (PST) X-Google-Smtp-Source: AA0mqf6DHBYzo0mioE+01H0ZKyt51rp40X+PgCWT0jI0b4GPVwOiqARRUf9MXHkLLZJxlVmV5vuG X-Received: by 2002:a63:7f1c:0:b0:476:7742:de19 with SMTP id a28-20020a637f1c000000b004767742de19mr14154935pgd.343.1668595575179; Wed, 16 Nov 2022 02:46:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595575; cv=none; d=google.com; s=arc-20160816; b=RKVLJnxqjpCjDnPU9pu7uBAZTJFLUrjNr25foRiQfE7mhss5SX4oyNlTmUF1DJOwP/ 68PIi6XwKM123pEOoKgH8EdR3jh/q6psHDeVeiemwXloEHt31ovlTNXhQCKU8+9jQ7Op 1iXv8HNQZqHSBlRA4elA61RUy0KgMJCsE9v7h62zch5V6rjsJf+Dzcb3nRT4xP5/+Ii5 ZnpHUT/Gguq7moc1hlOlwUzhDwJjqAxjA55e3i50FGDMClhAuGtPp32cAh8P44rZVBwh D4pNNUtKkHpjqbDaHr8lGhrMWTlfL57d20DwbGQ2Nl+Smq3za0VWQ21V4U4QuFfmOxnq 8VQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4U0hbok1FMn7nJASPoh7+9zeA5JHztgL3oEzZzACTGw=; b=napJDctVwYKdWu7OjYSPb1VyFHOswZSk1FocWX8H2W1WATQOuruGk46MXcBQLl5jNn vJ0n+FTQeyFH+NZ/LvbX6b1zUmtWBrdtQhjFkn9p2YpP995vB3z2ILxeFmofq1FauCCD a+lldUakstFENvKgopuNDc2lWRkgSvnbJ2GDbI+Qq4wpJOI1l+Jo/fmHDh8rDQo2THMZ RwttC3QfEPM897Kh05jhAB+ZbpatYoATuqfmURJ/DwDIRPHE3k0Gf7fmahlnc8zsTc57 NrK7HoVIpBZBQfpXBkwowrNA8jarSaACV4nwX7OYt8m23zxymw6HTgclbdXhJXhihYG6 cZOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i3xFo2NH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 419 ++++++++++++++++++++++++ 2 files changed, 420 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8550-mtp.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index afe496a93f94..b447b3082c84 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -169,3 +169,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts new file mode 100644 index 000000000000..d4c8d5b2497e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8550 MTP"; + compatible = "qcom,sm8550-mtp", "qcom,sm8550"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + pm8550b-rpmh-regulators { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p3>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p3>; + vdd-l12-supply = <&vreg_s6g_1p8>; + vdd-l15-supply = <&vreg_s6g_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + pm8550c-rpmh-regulators { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l3-supply = <&vreg_s4e_0p9>; + + vreg_l3c_0p91: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + pm8550d-rpmh-regulators { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s4e_0p9>; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + pm8550e-rpmh-regulators { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l1-supply = <&vreg_s4e_0p9>; + vdd-l2-supply = <&vreg_s4e_0p9>; + vdd-l3-supply = <&vreg_s4g_1p3>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s4e_0p9: smps4 { + regulator-name = "vreg_s4e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = ; + }; + + vreg_s5e_1p1: smps5 { + regulator-name = "vreg_s5e_1p1"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8550f-rpmh-regulators { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s4e_0p9>; + vdd-l2-supply = <&vreg_s4e_0p9>; + vdd-l3-supply = <&vreg_s4e_0p9>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3f_0p91: ldo3 { + regulator-name = "vreg_l3f_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + pm8550g-rpmh-regulators { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + vdd-l1-supply = <&vreg_s4g_1p3>; + vdd-l2-supply = <&vreg_s4g_1p3>; + vdd-l3-supply = <&vreg_s4g_1p3>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vreg_s1g_1p2: smps1 { + regulator-name = "vreg_s1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_s2g_0p8: smps2 { + regulator-name = "vreg_s2g_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_s3g_0p7: smps3 { + regulator-name = "vreg_s3g_0p7"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s4g_1p3: smps4 { + regulator-name = "vreg_s4g_1p3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s5g_0p8: smps5 { + regulator-name = "vreg_s5g_0p8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s6g_1p8: smps6 { + regulator-name = "vreg_s6g_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2g_1p2: ldo2 { + regulator-name = "vreg_l2g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + card-det-pins { + pins = "gpio12"; + function = "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source = <1>; /* 1.8 V */ + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + bus-width = <4>; + no-sdio; + no-emmc; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; +}; + +&uart7 { + status = "okay"; +};