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Sat, 17 Feb 2024 14:02:51 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sat, 17 Feb 2024 22:02:45 +0800 Subject: [PATCH RFC v2 1/4] dt-bindings: phy: hisi-inno-usb2: convert to YAML Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240217-inno-phy-v2-1-3bf7e87b0e9e@outlook.com> References: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> In-Reply-To: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708178566; l=5202; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=S10kxyAA+0zcLslyAPap5mw+bF2BBsabAHscvCgNtfw=; b=Y3S+hsOizkFLpagFOiUB+KQ7SpeWsONjf/SpDIki3AlBiNOnu9nBJZYogmDnIhD0TAF9otXJR dnBndRX/FHGD9sc0kzZaX7bMFMWEI9OMH/+9Imoj7N0yHbnI2pGRZ/7 X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791155131998303150 X-GMAIL-MSGID: 1791155131998303150 From: Yang Xiwen Also rename to hisilicon,inno-usb2-phy.yaml and add this name to compatible lists. Signed-off-by: Yang Xiwen --- .../bindings/phy/hisilicon,inno-usb2-phy.yaml | 95 ++++++++++++++++++++++ .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 71 ---------------- 2 files changed, 95 insertions(+), 71 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml new file mode 100644 index 000000000000..bfbda1568557 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,inno-usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon HiSTB SoCs INNO USB2 PHY device + +maintainers: + - Yang Xiwen + +properties: + compatible: + minItems: 1 + items: + - enum: + - hisilicon,hi3798cv200-usb2-phy + - hisilicon,hi3798mv100-usb2-phy + - const: hisilicon,inno-usb2-phy + + reg: + maxItems: 1 + description: | + Should be the address space for PHY configuration register in peripheral + controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. + Or direct MMIO address space. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + clocks: + maxItems: 1 + description: reference clock + + resets: + maxItems: 1 + +patternProperties: + 'phy@[0-9a-f]+': + type: object + additionalProperties: false + description: individual ports provided by INNO PHY + + properties: + reg: + maxItems: 1 + + '#phy-cells': + const: 0 + + resets: + maxItems: 1 + + required: + - reg + - '#phy-cells' + - resets + +required: + - compatible + - clocks + - reg + - '#address-cells' + - '#size-cells' + - resets + +additionalProperties: false + +examples: + - | + #include + + usb2-phy@120 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x120 0x4>; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + resets = <&crg 0xbc 4>; + #address-cells = <1>; + #size-cells = <0>; + + phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 8>; + }; + + phy@1 { + reg = <1>; + #phy-cells = <0>; + resets = <&crg 0xbc 9>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt deleted file mode 100644 index 104953e849e7..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt +++ /dev/null @@ -1,71 +0,0 @@ -Device tree bindings for HiSilicon INNO USB2 PHY - -Required properties: -- compatible: Should be one of the following strings: - "hisilicon,inno-usb2-phy", - "hisilicon,hi3798cv200-usb2-phy". -- reg: Should be the address space for PHY configuration register in peripheral - controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. -- clocks: The phandle and clock specifier pair for INNO USB2 PHY device - reference clock. -- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset - signal. -- #address-cells: Must be 1. -- #size-cells: Must be 0. - -The INNO USB2 PHY device should be a child node of peripheral controller that -contains the PHY configuration register, and each device supports up to 2 PHY -ports which are represented as child nodes of INNO USB2 PHY device. - -Required properties for PHY port node: -- reg: The PHY port instance number. -- #phy-cells: Defined by generic PHY bindings. Must be 0. -- resets: The phandle and reset specifier pair for PHY port reset signal. - -Refer to phy/phy-bindings.txt for the generic PHY binding properties - -Example: - -perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8a20000 0x1000>; - - usb2_phy1: usb2-phy@120 { - compatible = "hisilicon,hi3798cv200-usb2-phy"; - reg = <0x120 0x4>; - clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; - resets = <&crg 0xbc 4>; - #address-cells = <1>; - #size-cells = <0>; - - usb2_phy1_port0: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&crg 0xbc 8>; - }; - - usb2_phy1_port1: phy@1 { - reg = <1>; - #phy-cells = <0>; - resets = <&crg 0xbc 9>; - }; - }; - - usb2_phy2: usb2-phy@124 { - compatible = "hisilicon,hi3798cv200-usb2-phy"; - reg = <0x124 0x4>; - clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; - resets = <&crg 0xbc 6>; - #address-cells = <1>; - #size-cells = <0>; - - usb2_phy2_port0: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&crg 0xbc 10>; - }; - }; -}; From patchwork Sat Feb 17 14:02:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Xiwen via B4 Relay X-Patchwork-Id: 202630 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp335842dyc; Sat, 17 Feb 2024 06:03:58 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWA403UCqlkgeiOoxZD9RE4U6L5vsNnQkGFE8h7f9+bB/JWcnwd3EL43iDLYS2mzvdW0I/tYuw2ll/8fd3zE5i5BjQVRg== X-Google-Smtp-Source: AGHT+IGGOwlk8ont2iIAaAI17ysytwZ4D8RxQ2fZEE89bu8Pc3Hak4wo0RF8DXmFOArr4ShHRwOs X-Received: by 2002:a17:90a:c706:b0:296:f874:6844 with SMTP id o6-20020a17090ac70600b00296f8746844mr6964627pjt.15.1708178638192; Sat, 17 Feb 2024 06:03:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708178638; cv=pass; d=google.com; s=arc-20160816; b=A/vxQpednxQwepR7SmLoR06okDAnnHP+4rS0KNxd071URwI8yMifY+UQXBD98PmeGe 6hVZV+tn728b2FEQKySJEHW6XQMYfr6D2JTI/dGPxWi71XolxTwxTnXGkWfE7Yz9tPuq kn6oskfQUf6tTS5Y1qQVWl1UdMIoXJeJF0pka00e9bpCvkIs2eIjDeOjfXLn9KcPJ9zF vxNxH7vuK+sB3Q/iUbxrAxMMfpZ4ngxBME4Q1olCnA0w2Uy2HdfjKefRHeUw+QKTAWq8 u6RpG7CPKIv2woASEQdLqPgy3Mso91hLvC6D/hoIhpMgj5H218tqqyMbgneU7KR8lbIe YOsw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=reply-to:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:subject:date:from:dkim-signature; bh=hQITAdhlUtUX4990G57UYxlif2UybYruSSGjIcXMers=; fh=zeAM21czM+vIwT11j3JBFvwo0dMHxyj0T3l3EYWXLvQ=; b=h/Y4/z1AneFvdEJjdusfDhDVDRcK/wIEkocMEiyHIC5Bp3pkcCQhLCcNUubCyr9uvi Iwvnj45+8liwlw3SrLDLREKQBDI9frQPU0Ct7gSojEcJNnLazMt9EtMPHzZf29SdvtTJ ElLI+NRgOf2zM/TbEGaAZRxRp+SEwLaUt82OJTUAHoccb5YLdHmSabd5t6oA43kggdR5 gviCyOKpkuR6nN+hLJ88ruUI+lyzmQqzS6lifm303xVXeMLrwIP+MhxvhcComLzMeHHW UxF7SarAGY52T99o465MpShz8SbtTOJrtt30gQCz+0YuMMdyZTQ9q8QjKK7BfkxI6J0Y kmbw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=NT9Ie+1H; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-69894-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-69894-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Sat, 17 Feb 2024 14:02:51 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sat, 17 Feb 2024 22:02:46 +0800 Subject: [PATCH RFC v2 2/4] phy: hisilicon: hisi-inno-phy: enable clocks for every ports Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240217-inno-phy-v2-2-3bf7e87b0e9e@outlook.com> References: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> In-Reply-To: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708178566; l=971; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=jGUbESXsyAvU27nkXjLoTOKtwqcjOT068eM8RNJCWfs=; b=UHXOSwwODhww8EbGOJMLYpPN9XmbFpLtbnFuU8Z5k/lZVtDRxNc8n70BZnZEw2b+WB9jx8etr bHvTFAnMpBTAaslzLl5OHfnpTvZcXqAT/TkBUYPvHBe5bCC3fvCPJwM X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791155123406704766 X-GMAIL-MSGID: 1791155123406704766 From: Yang Xiwen This is needed for port1 to work. Fixes: ba8b0ee81fbb ("phy: add inno-usb2-phy driver for hi3798cv200 SoC") Signed-off-by: Yang Xiwen --- drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c index c138cd4807d6..b7e740eb4752 100644 --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -86,8 +86,10 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv, static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv) { + int i; /* The phy clk is controlled by the port0 register 0x06. */ - hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE); + for (i = 0; i < INNO_PHY_PORT_NUM; i++) + hisi_inno_phy_write_reg(priv, i, 0x06, PHY_CLK_ENABLE); msleep(PHY_CLK_STABLE_TIME); } From patchwork Sat Feb 17 14:02:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Xiwen via B4 Relay X-Patchwork-Id: 202631 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp335921dyc; Sat, 17 Feb 2024 06:04:03 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCX/kuxMRdVUsMBsmiM8Q64k2OMnc9+eP+IRPrpImC7edCisnhXebcyzXWkMivnm8NuHmvn7hFbNgJ9DinubQ0+hoN1/DA== X-Google-Smtp-Source: AGHT+IHf3eGBw2flNYFBVf9Qw0D0rqQGCWdYx15xoA1V03Om+BxiaQufd+36snNb87fhrDgbrfar X-Received: by 2002:a17:90b:1990:b0:299:48de:9c7a with SMTP id mv16-20020a17090b199000b0029948de9c7amr2679096pjb.0.1708178643783; Sat, 17 Feb 2024 06:04:03 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708178643; cv=pass; d=google.com; s=arc-20160816; b=Ph0vXfSEsCCdIOosAWcc8HcYneXqizrg4F+8VK+lts8rFvI7Ju/mTCdQZ1wQTjm36n aEvEde6yI98c29dv7UWjrVi2cRNFbJVQ2XK63n6uXYuaA1epkjfDVfmOmyH302uxHB5t zErwLvSlMafArgeiyLKgMooDDidiQmeGnro9Ba6zQAw/wfbuApYLtdYKNQBzx6oQXV1T oqFS/hmRohAzWi+yBfF5P0VKOieGuKYcRUL4wPH+ZijG3MBp2Crvxop7/9V8yX/MOGMJ HAK7c40hcKCg11ZeiCcxLWJpfHcENvWGQ5fx/+En5zgc+THITlklZPvMKhcGDOi7OJQ4 nJiA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=reply-to:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:subject:date:from:dkim-signature; bh=4HZpETrdM17KQGBi5KbHrolV6I/RbZeFDEznsVVeN9k=; fh=zeAM21czM+vIwT11j3JBFvwo0dMHxyj0T3l3EYWXLvQ=; b=Tih5B38g1TQtkNi1rhDD9zjw9W5mwU08U//b+KFHiVxTKcuM4gJEcfDrarbEsXcto6 glHXGSMRo3jLe+fo3/M/VM2xfsdx9bozjNN+W/ie0i7/+r86bQdFvIU2UDiaph0WngWh +9MYx1HEmvtEg6pilosDEkEEd4mpo5hkGSmrBFV2i66KeDZ9GJrQ/+1VLAilWseK9rMn vKwNaHX5SYwqFmCPD7Ti0TvscvGDWJSYYoUloeHBQCOmC1akXoBxwWIhiUqhs49q2NGK B0B7lerZfSYOsvvrhhc78unGNfiVEoP+R3ErmYPEB7AG9GkRDgrvSu0SW/1vVJMYDuCF 0W7w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=ItWTLi+l; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-69893-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-69893-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Sat, 17 Feb 2024 14:02:51 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sat, 17 Feb 2024 22:02:47 +0800 Subject: [PATCH RFC v2 3/4] phy: hisilicon: hisi-inno-phy: add support for Hi3798MV200 INNO PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240217-inno-phy-v2-3-3bf7e87b0e9e@outlook.com> References: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> In-Reply-To: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708178566; l=4896; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=GrCYJatgoRWu7Bx47GQoBXbcdNOq+uSu0U+veti+reE=; b=io0SbJNsSxMgQ3OaTc/0Z9tbTMuoUOoI7sFB5VfjG/ciOZl7aRIc2R0BYahKWoutI+NCTpO1B 377gjmMHMKGC9NMcLg0mt9uEo6KkEz1OM3+1O/B+KLbzoqsmWc1xz3t X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791155129521873131 X-GMAIL-MSGID: 1791155129521873131 From: Yang Xiwen Direct MMIO resgiter access is used by Hi3798MV200. For other models, of_iomap() returns 0 due to insufficient length. So they are unaffected. Also Hi3798MV200 INNO PHY has an extra reset required to be deasserted, switch to reset_control_bulk_() APIs to resolve this. Signed-off-by: Yang Xiwen --- drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 65 ++++++++++++++++++------------ 1 file changed, 39 insertions(+), 26 deletions(-) diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c index b7e740eb4752..5175e5a351ac 100644 --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -43,6 +44,7 @@ #define PHY_CLK_ENABLE BIT(2) struct hisi_inno_phy_port { + void __iomem *base; struct reset_control *utmi_rst; struct hisi_inno_phy_priv *priv; }; @@ -50,7 +52,7 @@ struct hisi_inno_phy_port { struct hisi_inno_phy_priv { void __iomem *mmio; struct clk *ref_clk; - struct reset_control *por_rst; + struct reset_control *rsts; unsigned int type; struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM]; }; @@ -62,26 +64,31 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv, u32 val; u32 value; - if (priv->type == PHY_TYPE_0) - val = (data & PHY_TEST_DATA) | - ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) | - ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) | - PHY0_TEST_WREN | PHY0_TEST_RST; - else - val = (data & PHY_TEST_DATA) | - ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) | - ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) | - PHY1_TEST_WREN | PHY1_TEST_RST; - writel(val, reg); - - value = val; - if (priv->type == PHY_TYPE_0) - value |= PHY0_TEST_CLK; - else - value |= PHY1_TEST_CLK; - writel(value, reg); - - writel(val, reg); + if (priv->ports[port].base) + // stride is 4 + writel(data, (u32 *)priv->ports[port].base + addr); + else { + if (priv->type == PHY_TYPE_0) + val = (data & PHY_TEST_DATA) | + ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) | + ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) | + PHY0_TEST_WREN | PHY0_TEST_RST; + else + val = (data & PHY_TEST_DATA) | + ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) | + ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) | + PHY1_TEST_WREN | PHY1_TEST_RST; + writel(val, reg); + + value = val; + if (priv->type == PHY_TYPE_0) + value |= PHY0_TEST_CLK; + else + value |= PHY1_TEST_CLK; + writel(value, reg); + + writel(val, reg); + } } static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv) @@ -104,7 +111,7 @@ static int hisi_inno_phy_init(struct phy *phy) return ret; udelay(REF_CLK_STABLE_TIME); - reset_control_deassert(priv->por_rst); + reset_control_deassert(priv->rsts); udelay(POR_RST_COMPLETE_TIME); /* Set up phy registers */ @@ -122,7 +129,7 @@ static int hisi_inno_phy_exit(struct phy *phy) struct hisi_inno_phy_priv *priv = port->priv; reset_control_assert(port->utmi_rst); - reset_control_assert(priv->por_rst); + reset_control_assert(priv->rsts); clk_disable_unprepare(priv->ref_clk); return 0; @@ -158,15 +165,16 @@ static int hisi_inno_phy_probe(struct platform_device *pdev) if (IS_ERR(priv->ref_clk)) return PTR_ERR(priv->ref_clk); - priv->por_rst = devm_reset_control_get_exclusive(dev, NULL); - if (IS_ERR(priv->por_rst)) - return PTR_ERR(priv->por_rst); + priv->rsts = devm_reset_control_array_get(dev, false, false); + if (IS_ERR(priv->rsts)) + return PTR_ERR(priv->rsts); priv->type = (uintptr_t) of_device_get_match_data(dev); for_each_child_of_node(np, child) { struct reset_control *rst; struct phy *phy; + void __iomem *base; rst = of_reset_control_get_exclusive(child, NULL); if (IS_ERR(rst)) { @@ -174,7 +182,10 @@ static int hisi_inno_phy_probe(struct platform_device *pdev) return PTR_ERR(rst); } + base = of_iomap(child, 0); + priv->ports[i].utmi_rst = rst; + priv->ports[i].base = base; priv->ports[i].priv = priv; phy = devm_phy_create(dev, child, &hisi_inno_phy_ops); @@ -205,6 +216,8 @@ static const struct of_device_id hisi_inno_phy_of_match[] = { .data = (void *) PHY_TYPE_0 }, { .compatible = "hisilicon,hi3798mv100-usb2-phy", .data = (void *) PHY_TYPE_1 }, + { .compatible = "hisilicon,hi3798mv200-usb2-phy", + .data = (void *) PHY_TYPE_0 }, { }, }; MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match); From patchwork Sat Feb 17 14:02:48 2024 Content-Type: text/plain; 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Sat, 17 Feb 2024 14:02:51 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sat, 17 Feb 2024 22:02:48 +0800 Subject: [PATCH RFC v2 4/4] dt-bindings: phy: hisi-inno-usb2: add compatible of hisilicon,hi3798mv200-usb2-phy Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240217-inno-phy-v2-4-3bf7e87b0e9e@outlook.com> References: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> In-Reply-To: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708178566; l=2016; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=jLZWuS47anxDC0v84kYOmUKJTlxPytV3qZbHvwpp28g=; b=Q/aLZDrqeMAj7mGpkxaMVPftjiJie2s2j/B2+LT4yWcdXm2FhadHAELA55FE9PjR3yynydw5y IDMBjWQCPJoCX6q6Hc93VBJWE1lkbYzChX1fhYBozhNb3cuFi8sj+TC X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791155126122261516 X-GMAIL-MSGID: 1791155126122261516 From: Yang Xiwen It is accessed by direct MMIO, making "ranges" property mandatory for it. Also there is an extra clock for the phy. Signed-off-by: Yang Xiwen --- .../bindings/phy/hisilicon,inno-usb2-phy.yaml | 32 ++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml index bfbda1568557..105dd9eebd4c 100644 --- a/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml @@ -16,6 +16,7 @@ properties: - enum: - hisilicon,hi3798cv200-usb2-phy - hisilicon,hi3798mv100-usb2-phy + - hisilicon,hi3798mv200-usb2-phy - const: hisilicon,inno-usb2-phy reg: @@ -25,18 +26,27 @@ properties: controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. Or direct MMIO address space. + ranges: + maxItems: 1 + '#address-cells': const: 1 '#size-cells': - const: 0 + enum: [0, 1] clocks: maxItems: 1 description: reference clock resets: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reset-names: + items: + - const: port + - const: test patternProperties: 'phy@[0-9a-f]+': @@ -54,6 +64,9 @@ patternProperties: resets: maxItems: 1 + phy_type: + const: utmi + required: - reg - '#phy-cells' @@ -67,6 +80,21 @@ required: - '#size-cells' - resets +allOf: + - if: + properties: + compatible: + contains: + const: hisilicon,hi3798mv200-usb2-phy + then: + required: + - ranges + - reset-names + else: + properties: + ranges: false + reset-names: false + additionalProperties: false examples: