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AJvYcCWd/pjl3DRP2WlHCgaAWW4ItbK4JOs28b/CDz/gktVbZrmvODgcCkF8FbBUgIHyT68dTCEqZRAUw82hcfoV6CQ5Poz96IYweQQbW7Is X-Gm-Message-State: AOJu0Yyc84wqbfCi/+MGOPn/q/MKtX+STegHv+Xq89LX09mns9CsXOM5 HyTvhBYKlZdMsYUo+M+6ebrozu1WOTV7exQvhdRpVtaqDcZJSfTBoNjX8h9Yq8EMhCamnQScMyv ZRQUU2ccz8Z77r4lzAQ== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:2284:b0:dc8:5e26:f4d7 with SMTP id dn4-20020a056902228400b00dc85e26f4d7mr1779458ybb.13.1708175574920; Sat, 17 Feb 2024 05:12:54 -0800 (PST) Date: Sat, 17 Feb 2024 13:12:49 +0000 In-Reply-To: <20240217131206.3667544-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240217131206.3667544-1-ericchancf@google.com> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog Message-ID: <20240217131249.3668103-1-ericchancf@google.com> Subject: [PATCH v6 1/4] riscv/barrier: Define __{mb,rmb,wmb} From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com, conor.dooley@microchip.com, parri.andrea@gmail.com, emil.renner.berthing@canonical.com, samuel.holland@sifive.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791151929471839805 X-GMAIL-MSGID: 1791151929471839805 Introduce __{mb,rmb,wmb}, and rely on the generic definitions for {mb,rmb,wmb}. Although KCSAN is not supported yet, the definitions can be made more consistent with generic instrumentation. Also add a space to make the changes pass check by checkpatch.pl. Without the space, the error message is as below: ERROR: space required after that ',' (ctx:VxV) 26: FILE: arch/riscv/include/asm/barrier.h:23: +#define __mb() RISCV_FENCE(iorw,iorw) ^ Signed-off-by: Eric Chan --- v5 -> v6: let this change to pass review by checkpatch.pl instead of overwriting again in [PATCH 4/4] v3 -> v4: fix commit message weird line breaks arch/riscv/include/asm/barrier.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.44.0.rc0.258.g7320e95886-goog diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 110752594228..173b44a989f8 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -20,9 +20,9 @@ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ -#define mb() RISCV_FENCE(iorw,iorw) -#define rmb() RISCV_FENCE(ir,ir) -#define wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw, iorw) +#define __rmb() RISCV_FENCE(ir, ir) +#define __wmb() RISCV_FENCE(ow, ow) /* These barriers do not need to enforce ordering on devices, just memory. */ #define __smp_mb() RISCV_FENCE(rw,rw) From patchwork Sat Feb 17 13:13:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 202621 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp313317dyc; Sat, 17 Feb 2024 05:13:24 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVWyAN9q+MYnnWbkgoCGnYlvA30GzWALZcirjU+E46hfKmFaf8g26QMm61UlJ5+Nki/GkGFMeG8tBQ/ZUPY0SuYJ6xj2w== X-Google-Smtp-Source: AGHT+IHxGw5xKYeXs7kCClec2BhOa+L74p5CdKKO02UmgX5/RLqn6VwBbYRdcGzfbtXwMkSO7XtQ X-Received: by 2002:a17:906:8445:b0:a3c:bb68:8089 with SMTP id e5-20020a170906844500b00a3cbb688089mr8149712ejy.15.1708175604743; Sat, 17 Feb 2024 05:13:24 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708175604; cv=pass; d=google.com; s=arc-20160816; b=RjAd9fqO/4GtunD5wKRBA12+naMMr63X8C09SWw1czls1GMotZP4upQYA0lbvcowsn 03ThtPmumTf3Z/Bgrh23LpxEMmnECmpXA+5QmVF9Vw1DNVpRkudmhPloiPwlF/WkO5ML 4Z3aaI1yu5S7pjpD8/+FAogm34S2tC6VlOgr69oifa1iopjSVb9zdC+pBEYzv/kgNkri VbiRIhq6t+IvbgEpGuZU/q2AjHu/I6yVU2Zo3gaO9hwGEf708BP1C+hfeh8RMo60Z+YG vsfdDOBXlX27OwYXgvF7O00gUiVJrW0oazXnlRVhFsEMm/rkT58sqRht+k8uozupZXRs z+Ng== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:from:subject:message-id:references:mime-version :list-unsubscribe:list-subscribe:list-id:precedence:in-reply-to:date :dkim-signature; bh=R2+WpDCt8HOz+kxBkD8ukIa/A2HuTgCzwuZw4fcBj8Q=; fh=rjKRgWjubf9rnlpTeY+9Ijv4ky7CNZgvAY8eKoMHr1A=; b=w5f1ulg7d4FbJG32Tn+GmKYmfK4S/62Aj97yLd1f6yZVNdWXcVPiUawrldv/n9JyFV MC3g405yKwaaehiF3jkI25+EMrDypwKEDrtlycjv7+cwg6F4KSB5LyYTq3yEztaWxGrO MUkYNSc6H+cBrhzb/8LXydh/SLeQMzx0nLlw7ePZ6rb7R2Em46Yu+Pvln+DjDEmZQTvl PnRkPfsNA9Mr9ISIP4zq1ZDH4tPNk8lrnA5lArBv6s9Nh+hVQWxBlfmbCcPQ8pgZJ5hc SSQUWWeARQiIESqP5yOSfWHWgznWwBsHIx1wltd/7Zl6rc/WDVj8/jc8Ml34BU4LZdlI NpJw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=hNuZ9CnT; arc=pass (i=1 spf=pass spfdomain=flex--ericchancf.bounces.google.com dkim=pass dkdomain=google.com dmarc=pass fromdomain=google.com); spf=pass (google.com: domain of linux-kernel+bounces-69865-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-69865-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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AJvYcCWSkTJS06HMbkcBKgqldTyYU5YMTTimk0cSsJyMgPpHd1ifBjCmAzdmdjn8JiVQNeKfXIbGPaCXXcOmEn8hWdlyES7ruVSdWw2nzXFU X-Gm-Message-State: AOJu0YzgXzG0Qua56zs0SFKeGdU8r7wFJUyb11ztIuIiZIXOqz3av7Eo xvJ21OLYYlQoyYrOZeMJXfAgrYg1CFsWOJX2ve7dnuBZGNfNRKljWAei4sS9oSR55/y7hZNds4w R9lyI8i/f0yubHUkVyw== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:1029:b0:dc9:5ef8:2b2d with SMTP id x9-20020a056902102900b00dc95ef82b2dmr1930551ybt.4.1708175588280; Sat, 17 Feb 2024 05:13:08 -0800 (PST) Date: Sat, 17 Feb 2024 13:13:02 +0000 In-Reply-To: <20240217131206.3667544-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240217131206.3667544-1-ericchancf@google.com> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog Message-ID: <20240217131302.3668481-1-ericchancf@google.com> Subject: [PATCH v6 2/4] riscv/barrier: Define RISCV_FULL_BARRIER From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com, conor.dooley@microchip.com, parri.andrea@gmail.com, emil.renner.berthing@canonical.com, samuel.holland@sifive.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791151942536495166 X-GMAIL-MSGID: 1791151942536495166 Introduce RISCV_FULL_BARRIER and use in arch_atomic* function. like RISCV_ACQUIRE_BARRIER and RISCV_RELEASE_BARRIER, the fence instruction can be eliminated When SMP is not enabled. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 16 ++++++++-------- arch/riscv/include/asm/cmpxchg.h | 4 ++-- arch/riscv/include/asm/fence.h | 2 ++ 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index f5dfef6c2153..31e6e2e7cc18 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -207,7 +207,7 @@ static __always_inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int " add %[rc], %[p], %[a]\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -228,7 +228,7 @@ static __always_inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, " add %[rc], %[p], %[a]\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -248,7 +248,7 @@ static __always_inline bool arch_atomic_inc_unless_negative(atomic_t *v) " addi %[rc], %[p], 1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -268,7 +268,7 @@ static __always_inline bool arch_atomic_dec_unless_positive(atomic_t *v) " addi %[rc], %[p], -1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -288,7 +288,7 @@ static __always_inline int arch_atomic_dec_if_positive(atomic_t *v) " bltz %[rc], 1f\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -310,7 +310,7 @@ static __always_inline bool arch_atomic64_inc_unless_negative(atomic64_t *v) " addi %[rc], %[p], 1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -331,7 +331,7 @@ static __always_inline bool arch_atomic64_dec_unless_positive(atomic64_t *v) " addi %[rc], %[p], -1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -352,7 +352,7 @@ static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) " bltz %[rc], 1f\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 2f4726d3cfcc..a608e4d1a0a4 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -313,7 +313,7 @@ " bne %0, %z3, 1f\n" \ " sc.w.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" ((long)__old), "rJ" (__new) \ @@ -325,7 +325,7 @@ " bne %0, %z3, 1f\n" \ " sc.d.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" (__old), "rJ" (__new) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 2b443a3a487f..6c26c44dfcd6 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -4,9 +4,11 @@ #ifdef CONFIG_SMP #define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" #define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#define RISCV_FULL_BARRIER "\tfence rw, rw\n" #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER +#define RISCV_FULL_BARRIER #endif #endif /* _ASM_RISCV_FENCE_H */ From patchwork Sat Feb 17 13:13:16 2024 Content-Type: text/plain; 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AJvYcCUT8o2JTLBKJI8LMJRrnievxazwAU5dqxya+BGLvU0nmhyQp3vJnwvRyh1A+PNYoyU7+R7bnmoaNVC8BB+DIWCILLwHMqGYbUx05LBy X-Gm-Message-State: AOJu0YwejeglWObs60GjIcEUlcb2LLzFehAJnrUk/zC1OKEY7bliEbHY uTP3uAt4TWQFHMcYY4TghzFGgJ5TCCCVksCoyMHPu8bvjQ0JzqPCR09gX0CODsJeVyYlJRyeqpK 0mJTSxE18UMutLZx03Q== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a0d:d951:0:b0:608:1b39:245c with SMTP id b78-20020a0dd951000000b006081b39245cmr149033ywe.9.1708175602463; Sat, 17 Feb 2024 05:13:22 -0800 (PST) Date: Sat, 17 Feb 2024 13:13:16 +0000 In-Reply-To: <20240217131206.3667544-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240217131206.3667544-1-ericchancf@google.com> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog Message-ID: <20240217131316.3668927-1-ericchancf@google.com> Subject: [PATCH v6 3/4] riscv/barrier: Consolidate fence definitions From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com, conor.dooley@microchip.com, parri.andrea@gmail.com, emil.renner.berthing@canonical.com, samuel.holland@sifive.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791151959508417406 X-GMAIL-MSGID: 1791151959508417406 Disparate fence implementations are consolidated into fence.h. Also introduce RISCV_FENCE_ASM to make fence macro more reusable. Signed-off-by: Eric Chan --- v4 -> v5: __atomic_acquire_fence and __atomic_release_fence omit-the-fence-on-uniprocessor optimization, and fix the typo of RISCV_RELEASE_BARRIER when spliting the patch in v3. v3 -> v4 fix the form that can pass the checking of checkpatch.pl. v1 -> v2: makes compilation pass with allyesconfig instead of defconfig only, also satisfy scripts/checkpatch.pl. - (__asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory")) + ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) arch/riscv/include/asm/atomic.h | 1 - arch/riscv/include/asm/barrier.h | 3 +-- arch/riscv/include/asm/cmpxchg.h | 1 - arch/riscv/include/asm/fence.h | 10 +++++++--- arch/riscv/include/asm/io.h | 8 ++++---- arch/riscv/include/asm/mmio.h | 5 +++-- arch/riscv/include/asm/mmiowb.h | 2 +- 7 files changed, 16 insertions(+), 14 deletions(-) -- 2.44.0.rc0.258.g7320e95886-goog diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 31e6e2e7cc18..0e0522e588ca 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -17,7 +17,6 @@ #endif #include -#include #define __atomic_acquire_fence() \ __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 173b44a989f8..15857dbc2279 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -11,13 +11,12 @@ #define _ASM_RISCV_BARRIER_H #ifndef __ASSEMBLY__ +#include #define nop() __asm__ __volatile__ ("nop") #define __nops(n) ".rept " #n "\nnop\n.endr\n" #define nops(n) __asm__ __volatile__ (__nops(n)) -#define RISCV_FENCE(p, s) \ - __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ #define __mb() RISCV_FENCE(iorw, iorw) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index a608e4d1a0a4..2fee65cc8443 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -8,7 +8,6 @@ #include -#include #include #define __xchg_relaxed(ptr, new, size) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 6c26c44dfcd6..6bcd80325dfc 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -1,10 +1,14 @@ #ifndef _ASM_RISCV_FENCE_H #define _ASM_RISCV_FENCE_H +#define RISCV_FENCE_ASM(p, s) "\tfence " #p "," #s "\n" +#define RISCV_FENCE(p, s) \ + ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) + #ifdef CONFIG_SMP -#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" -#define RISCV_RELEASE_BARRIER "\tfence rw, w\n" -#define RISCV_FULL_BARRIER "\tfence rw, rw\n" +#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r, rw) +#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw, w) +#define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw, rw) #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 42497d487a17..1c5c641075d2 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -47,10 +47,10 @@ * sufficient to ensure this works sanely on controllers that support I/O * writes. */ -#define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory"); -#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory"); -#define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); -#define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); +#define __io_pbr() RISCV_FENCE(io, i) +#define __io_par(v) RISCV_FENCE(i, ior) +#define __io_pbw() RISCV_FENCE(iow, o) +#define __io_paw() RISCV_FENCE(o, io) /* * Accesses from a single hart to a single I/O address must be ordered. This diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index 4c58ee7f95ec..06cadfd7a237 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -12,6 +12,7 @@ #define _ASM_RISCV_MMIO_H #include +#include #include /* Generic IO read/write. These perform native-endian accesses. */ @@ -131,8 +132,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); }) -#define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) +#define __io_ar(v) RISCV_FENCE(i, ir) +#define __io_bw() RISCV_FENCE(w, o) #define __io_aw() mmiowb_set_pending() #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiowb.h index 0b2333e71fdc..52ce4a399d9b 100644 --- a/arch/riscv/include/asm/mmiowb.h +++ b/arch/riscv/include/asm/mmiowb.h @@ -7,7 +7,7 @@ * "o,w" is sufficient to ensure that all writes to the device have completed * before the write to the spinlock is allowed to commit. */ -#define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory"); +#define mmiowb() RISCV_FENCE(o, w) #include #include From patchwork Sat Feb 17 13:13:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 202623 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp313525dyc; Sat, 17 Feb 2024 05:13:50 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXyReB4fDc9OvfbsrikFcaMKHivFeNlU9sLdpunjKDmsj8DUjd0stReAgBVHl2zYLhTGy3xq25WZHEcOc3MVW8Lzn5Rag== X-Google-Smtp-Source: AGHT+IHZ/7lTebVHt3Cy+2xTJRtc/XVNkf9nrR6UALtISZsRRW96MCzLoDTHoWJB3mKpmVjVaYbR X-Received: by 2002:ac8:5c05:0:b0:42d:e7be:d53d with SMTP id i5-20020ac85c05000000b0042de7bed53dmr4257651qti.29.1708175629922; Sat, 17 Feb 2024 05:13:49 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708175629; cv=pass; d=google.com; s=arc-20160816; b=ONeaG2Y3fhHa4YSA8jzA0iZRdj0gOWONpSvhVUHSm/MA5aOTuZZgE5dAuJrVj8bGpw YoIadOYF34gC2SusogTf3UVJSk0uBxkibhJtin5+ejHA+sCmz7tpn6IORl45Jty6KrV6 bU1OIlOk5ve+zTm9ZpJDTa/rebn+f6ZlC3oZ5jMXYslGSTo4Tsin+oSd1L2BM23iCOsH wgBkdLHFNzHBOVvkuB5tIzKScPGW6g81AHHBINKd7g3jfoWfft3AuHv8WaN7mTQSNz93 9xlAdVZ6U/Ohaj8jE2TNtJbdfwzMV/uGyRip4SriTSQNQcK9aeUm8QxXb81JnIyv3HR4 Nofw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:from:subject:message-id:references:mime-version :list-unsubscribe:list-subscribe:list-id:precedence:in-reply-to:date :dkim-signature; bh=lyeLrRd9CLe7Hw11wYIs8TpWMeWxDTUtralQA0dQ0yM=; fh=IGQz8atl5DmA8JD7gdrd0YJdoR210ac3oGnE0u1UeRg=; b=IwO3zH4HdUan/Ar3o61F7gi9qJNzXw+fbNqimjWVA5zgq67ex4A3/U9eO+Ir+dF+qs r6GNxdyMb2hJyOPMdMNqNTr1wV+WoMgX03J8qtIPKxJfkXp1b4zOiQTLmc1a7QcYdw5S u1FXNdAnoaWyrHNCd26s948sdRNHmBc2KP+yOSnL1ZkEgZUKAulZS15ASmgz5phCcHHv KcRfxDWDmknf8BLU90znjW1mkhudIl45epmL8T6lm7McXKqKg2Ac4mVQdP9IGjOkfRkc R/IvXVKEcufijOabK2M/ikFYFKJCaiTe7+no1qMWyFSMAuMhyzvf1FU4oqSIhcIOkPo2 w3aQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=rkyKN8Ya; arc=pass (i=1 spf=pass spfdomain=flex--ericchancf.bounces.google.com dkim=pass dkdomain=google.com dmarc=pass fromdomain=google.com); spf=pass (google.com: domain of linux-kernel+bounces-69867-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-69867-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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AJvYcCWrBxI7eYA7mu23Xgb8wQkDPwxLZJXOA4gR3S7oGhMzIkl7H6ITkbpGiGx5wHimZs9TPMCR6ZAA0Q5qpC8H/4hpf5JFTPQwF/va9j35 X-Gm-Message-State: AOJu0YxxqBsGb9UK9qUx8yxY1yH5RofTaPmsgyiunom1anliUYfIEMpm ajb/07k0zq1KAGXo2XqZ+CkKvYXyLp7OG38WG4Ld99a1D/etLgA6jWglejP0uWZFUsQ1OmzcrXe /o14K0WBqzZmFBesIHQ== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a17:90b:3a4e:b0:298:eacc:658d with SMTP id oh14-20020a17090b3a4e00b00298eacc658dmr99799pjb.3.1708175614576; Sat, 17 Feb 2024 05:13:34 -0800 (PST) Date: Sat, 17 Feb 2024 13:13:28 +0000 In-Reply-To: <20240217131206.3667544-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240217131206.3667544-1-ericchancf@google.com> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog Message-ID: <20240217131328.3669364-1-ericchancf@google.com> Subject: [PATCH v6 4/4] riscv/barrier: Add missing space after ',' From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com, conor.dooley@microchip.com, parri.andrea@gmail.com, emil.renner.berthing@canonical.com, samuel.holland@sifive.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791151969354702792 X-GMAIL-MSGID: 1791151969354702792 The past form of RISCV_FENCE would cause checkpatch.pl to issue error messages, the example is as follows: ERROR: space required after that ',' (ctx:VxV) 26: FILE: arch/riscv/include/asm/barrier.h:27: +#define __smp_mb() RISCV_FENCE(rw,rw) ^ fix the remaining of RISCV_FENCE. Signed-off-by: Eric Chan --- v5 -> v6: change the error message example in commit message to make it more relevant arch/riscv/include/asm/barrier.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.44.0.rc0.258.g7320e95886-goog diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 15857dbc2279..880b56d8480d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -24,14 +24,14 @@ #define __wmb() RISCV_FENCE(ow, ow) /* These barriers do not need to enforce ordering on devices, just memory. */ -#define __smp_mb() RISCV_FENCE(rw,rw) -#define __smp_rmb() RISCV_FENCE(r,r) -#define __smp_wmb() RISCV_FENCE(w,w) +#define __smp_mb() RISCV_FENCE(rw, rw) +#define __smp_rmb() RISCV_FENCE(r, r) +#define __smp_wmb() RISCV_FENCE(w, w) #define __smp_store_release(p, v) \ do { \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(rw,w); \ + RISCV_FENCE(rw, w); \ WRITE_ONCE(*p, v); \ } while (0) @@ -39,7 +39,7 @@ do { \ ({ \ typeof(*p) ___p1 = READ_ONCE(*p); \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(r,rw); \ + RISCV_FENCE(r, rw); \ ___p1; \ }) @@ -68,7 +68,7 @@ do { \ * instances the scheduler pairs this with an mb(), so nothing is necessary on * the new hart. */ -#define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw) +#define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw) #include