From patchwork Wed Nov 16 10:28:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 20901 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp68098wru; Wed, 16 Nov 2022 02:39:28 -0800 (PST) X-Google-Smtp-Source: AA0mqf6kpo6ZPIAkDE46ONmzJat4Uo8JCSX8weNgJSv0HUqWsKAEtAYpw6mJ0agQBrNDa8q1Lm6j X-Received: by 2002:a05:6402:2947:b0:467:5e8a:bce3 with SMTP id ed7-20020a056402294700b004675e8abce3mr18427692edb.334.1668595168267; Wed, 16 Nov 2022 02:39:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595168; cv=none; d=google.com; s=arc-20160816; b=Sg1mhhrqgaetwmKmTNOCs90FIFrN8f6Xg3nFXG930c8uZO6cvuXEdsC3JHboAAfuDb gGHghVTvevmXLleMD47mjV9ClY4A40Ahuk+L19W8kJTQuuqEQrhSi76Oy4lDaXpNe5u3 EteAGMwijDgo9sQo+IEJ3Az6xmlBykBVW48pEYcZw3X+t6A+Sz6ZGmnMuE1dc/gKAJCf tmA6wca2qkRLxIVXaQOgqku5b6aLT1KPy/H0Q3wA1oJjdDE2nu0yzbj28K9KbHDY/SqF n7i0Yazfk2+FBqpSNEExb8hxeRY6gSbxeKZK0zZ8Rhlz6SZxwcQ/ikurTSDkUkMSiNfM vSGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=o2vFFZj0asvM/eG5j2z+UIf5OoA8cJ4FO5LVI46RoA8=; b=xzPNs24JypWnFW3H4YvBZ+SL/Kf75Cz0P6JP4h55SXrL9tCXrLV3H6N1Sz5cj07cf0 qSX/MmsBlZpO+jv1u0ZDQfH4KskmG+gAEBZQ9nUOtBG324+Uj9uPziqB3C9XDTNcdGn6 t+sXGTlNLPMuF0OGEAkcdS9/3l+wvxr7PzCaBW0dp0GdDR6NnMIYQQGeMkaM3Nh5tf7Y 3vCQQjdX8A17uRBAc1n+1M/HiCEd5L/074zu8QYJM+Z1Faq8lcLbdRKKGt11ugEfzNtc dtXtWcbP6dYCJub6jgGTiDO81abJEOxCS3TAoxyidu1cMtEiGIpl9LEiG2wxueIY+Qan /gtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=N0abli5i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id dt4-20020a170907728400b0073d8ccd37c2si13716427ejc.107.2022.11.16.02.39.04; Wed, 16 Nov 2022 02:39:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=N0abli5i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233612AbiKPKh1 (ORCPT + 99 others); Wed, 16 Nov 2022 05:37:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233471AbiKPKff (ORCPT ); Wed, 16 Nov 2022 05:35:35 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.129.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0BC46429 for ; Wed, 16 Nov 2022 02:28:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1668594517; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=o2vFFZj0asvM/eG5j2z+UIf5OoA8cJ4FO5LVI46RoA8=; b=N0abli5il4jQti6/qWePPd61pmJvXpK7xK+Fz02GMpH8L2IdXROtZVL9ubERZxdec5HTWe O7PAiUEMqaw8vA3A3MAHUQI9i3uC1nmdaEVlDxIcalCfN4lK1mKrmd3JWxCNcGFDmGIEV7 10ieYA44yIx+tJoarnmlDfHnuvn+zXumCT0yNW2S1k3oreQKlPh7r5h0vtZPuZES/UDiuF OL/S0QEJ0WDrQcb5w9e2ktFkLHbzFZ+3HGwZsWGhCK+XV12C9pEDrS6Lg+pAnk+V3VdBWJ SSdt0ZbmFTwxwIIhxc/GEML35i4LidMexRubYvacgZ7AJtMf1uq4YFVZ1cEoHQ== Received: from mail.maxlinear.com (174-47-1-83.static.ctl.one [174.47.1.83]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-119-9UH-ool9MTCCl9vGZhfhXQ-1; Wed, 16 Nov 2022 05:28:36 -0500 X-MC-Unique: 9UH-ool9MTCCl9vGZhfhXQ-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Wed, 16 Nov 2022 02:28:30 -0800 From: Rahul Tanwar To: , , , , , , , CC: , , , , , , , , "Rahul Tanwar" Subject: [PATCH v2 1/2] x86/of: Add support for boot time interrupt delivery mode configuration Date: Wed, 16 Nov 2022 18:28:20 +0800 Message-ID: <9114810c7af7fbaf9d0b2823752afcef865bdda0.1668589253.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749648846727452918?= X-GMAIL-MSGID: =?utf-8?q?1749648846727452918?= Presently, init/boot time interrupt delivery mode is enumerated only for ACPI enabled systems by parsing MADT table or for older systems by parsing MP table. But for OF based x86 systems, it is assumed & hardcoded to legacy PIC mode. This is a bug for platforms which are OF based but do not use 8259 compliant legacy PIC interrupt controller. Such platforms can not even boot because of this bug/hardcoding. Fix this bug by adding support for configuration of init time interrupt delivery mode for x86 OF based systems by introducing a new optional boolean property 'intel,virtual-wire-mode' for interrupt-controller node of local APIC. This property emulates IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer structure [1]. Defaults to legacy PIC mode if absent. Configures it to virtual wire compatibility mode if present. [1] https://www.manualslib.com/manual/77733/Intel-Multiprocessor.html?page=40#manual Fixes: 3879a6f329483 ("x86: dtb: Add early parsing of IO_APIC") Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 5cd51f25f446..2a8833f0f6ae 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -167,7 +167,14 @@ static void __init dtb_lapic_setup(void) return; } smp_found_config = 1; - pic_mode = 1; + if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { + printk(KERN_NOTICE "Virtual Wire compatibility mode.\n"); + pic_mode = 0; + } else { + printk(KERN_NOTICE "IMCR and PIC compatibility mode.\n"); + pic_mode = 1; + } + register_lapic_address(lapic_addr); } From patchwork Wed Nov 16 10:28:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 20906 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp68458wru; Wed, 16 Nov 2022 02:40:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf4zONDaccdXslGso0kmgq6kZAhIb57iWO3Snra9CrFyf0dy8KdeHnfLeyYh3CAOzy+91FzZ X-Received: by 2002:a17:906:d82:b0:7ad:8a7a:2343 with SMTP id m2-20020a1709060d8200b007ad8a7a2343mr16829826eji.225.1668595227308; Wed, 16 Nov 2022 02:40:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668595227; cv=none; d=google.com; s=arc-20160816; b=KGBtgPtRhaRNzg2sh74xCk6kyQjJHfSKEFudZRfR1iV38DIWf39c6ZhRbAPOfBdb/4 jBNwbv56QYiO9TljGDYGuBOKmzJaClztsTXFaMCOk69H1nQt8wOmG5qth5mDJ1t9QHF+ aCxH4RPcc5oKUhBOzPhHJeN8htMVMZE44NuaCF+b16eIcl+1muPZ/Dd3gCWZHiShzcZ7 oCWbiNCRl7coeuqazxuzBMgJ4BFbcHRk8i3C4C7UpdVuXPaXSqRexLEqWy/XUzQg3/TZ N54Xiren3W53ti28WSUBxnKk423Sr2lk5K5JPelxCdLLT/FSU1uPuBfMIIM6VnJHTtVZ p30A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BxEZuRkRGD62WXnjbjEacCdYU53Qf097NU8Yuqsm2b8=; b=Ak2PzrigIGEVHpHQhj8mA4Ut505XX5Wyg6vCkPJWmTALB6clCP6gk8BIzE1IcHKDlh fkJhFHtt2ufb6BGrJ++c2EsjFiQ/7qRGSBDaQ2hfPH1TxIIJOX+QyYbxVFtboNH1/7/8 O0WHbLvbOV7w3e4A1lws4wfHluc7LTxKmk5g3kEgCNPhMALIYKTiAr8OMOjp+BAk8ER9 uXLuIa/a7G60hR5XKqRMJS4qU+sVjkhqWdihdu2hKqftuAD45bocwjN5FbGs3RKRHAvy 9J6Xw/55wOKSZPx7QBeFVtqnYCR3UXPWKnwIFH6pPx7hj+5h9NjvF/FLdUoiWZoC8BHa rLLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=hLJ6uoOa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id fy24-20020a170906b7d800b007418a1e877dsi10762857ejb.580.2022.11.16.02.40.03; Wed, 16 Nov 2022 02:40:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=hLJ6uoOa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232801AbiKPKjD (ORCPT + 99 others); Wed, 16 Nov 2022 05:39:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232850AbiKPKfu (ORCPT ); Wed, 16 Nov 2022 05:35:50 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35E0AFCFC for ; Wed, 16 Nov 2022 02:28:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1668594522; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BxEZuRkRGD62WXnjbjEacCdYU53Qf097NU8Yuqsm2b8=; b=hLJ6uoOaw9bw7dU5Z/RUfbnL15tyjmfy/IPtF1UCJoUZkoLBu199IYWja7guUQ9qt6SGGh MVPN9VmJec5d36wKYUicwNcS4Ypg241tFbK5MOVFcp571oEp+tVAOWh8wtELUQY7wLuRkj nIX60wCL1sgmssOzRcmPxOgBKwHUBiLVLkM6ylXr2IUqsPv2XOqW+WpRCXBb/Y3KYQ0Cz1 pmjFWrv1CvTRYZhb8q+7zJOmAq8ih+kdeisfHPnxEEjeFCclvW4I3CELgsnpf/PLaWyIEl 7WdSB+AQM4VMY4SENQy5qfvEYkQcdlkE7so2RqnMQMAeaWhD3L+qMNsN2tvs5w== Received: from mail.maxlinear.com (174-47-1-83.static.ctl.one [174.47.1.83]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-160-OxDfw-HvPhmT22pZa4OKpg-1; Wed, 16 Nov 2022 05:28:41 -0500 X-MC-Unique: OxDfw-HvPhmT22pZa4OKpg-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Wed, 16 Nov 2022 02:28:35 -0800 From: Rahul Tanwar To: , , , , , , , CC: , , , , , , , , "Rahul Tanwar" Subject: [PATCH v2 2/2] x86/of: Convert & update Intel's APIC related binding schemas Date: Wed, 16 Nov 2022 18:28:21 +0800 Message-ID: <5ba7963fbd82a859ffd99c6d8edb4d717fce0e6c.1668589253.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749648908922358503?= X-GMAIL-MSGID: =?utf-8?q?1749648908922358503?= Intel's APIC family of interrupt controllers support local APIC (lapic) & I/O APIC (ioapic). Convert existing bindings for lapic & ioapic from text to YAML schema. Separate lapic & ioapic schemas. Also, update more info and newly introduced optional property for lapic to choose legacy PIC or virtual wire compatibility interrupt delivery mode. Signed-off-by: Rahul Tanwar --- .../intel,ce4100-ioapic.txt | 26 -------- .../intel,ce4100-ioapic.yaml | 62 ++++++++++++++++++ .../intel,ce4100-lapic.yaml | 63 +++++++++++++++++++ 3 files changed, 125 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt deleted file mode 100644 index 7d19f494f19a..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt +++ /dev/null @@ -1,26 +0,0 @@ -Interrupt chips ---------------- - -* Intel I/O Advanced Programmable Interrupt Controller (IO APIC) - - Required properties: - -------------------- - compatible = "intel,ce4100-ioapic"; - #interrupt-cells = <2>; - - Device's interrupt property: - - interrupts =

; - - The first number (P) represents the interrupt pin which is wired to the - IO APIC. The second number (S) represents the sense of interrupt which - should be configured and can be one of: - 0 - Edge Rising - 1 - Level Low - 2 - Level High - 3 - Edge Falling - -* Local APIC - Required property: - - compatible = "intel,ce4100-lapic"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml new file mode 100644 index 000000000000..537bb69cf2d3 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel I/O Advanced Programmable Interrupt Controller (I/O APIC) + +maintainers: + - Sebastian Andrzej Siewior + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. See bindings/x86/ce4100.txt for more + details on it. + + This schema defines bindings for I/O APIC interrupt controller. + +properties: + compatible: + - const: intel,ce4100-ioapic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + ioapic1: interrupt-controller@fec00000 { + compatible = "intel,ce4100-ioapic"; + reg = <0xfec00000 0x1000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml new file mode 100644 index 000000000000..890e07351506 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) + +maintainers: + - Sebastian Andrzej Siewior + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. See bindings/x86/ce4100.txt for more + details on it. + + This schema defines bindings for local APIC interrupt controller. + +properties: + compatible: + - const: intel,ce4100-lapic + + reg: + maxItems: 1 + + intel,virtual-wire-mode: + description: Intel defines a few possible interrupt delivery + modes. With respect to boot/init time, mainly two interrupt + delivery modes are possible. + PIC Mode - Legacy external 8259 compliant PIC interrupt controller. + Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. + For ACPI or MPS spec compliant systems, it is figured out by some read + only bit field/s available in their respective defined data structures. + For OF based systems, it is by default set to PIC mode. + But if this optional boolean property is set, then the interrupt delivery + mode is configured to virtual wire compatibility mode. + type: boolean + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + lapic0: interrupt-controller@fee00000 { + compatible = "intel,ce4100-lapic"; + reg = <0xfee00000 0x1000>; + intel,virtual-wire-mode; + };