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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS1PEPF00017091.mail.protection.outlook.com (10.167.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Fri, 16 Feb 2024 21:03:57 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 16 Feb 2024 13:03:46 -0800 Received: from pohsuns-pegasus.nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 16 Feb 2024 13:03:44 -0800 From: Pohsun Su To: , , , CC: , , , Pohsun Su Subject: [PATCH v2 1/2] clocksource/drivers/timer-tegra186: add WDIOC_GETTIMELEFT support Date: Sat, 17 Feb 2024 05:02:57 +0800 Message-ID: <20240216210258.24855-2-pohsuns@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240216210258.24855-1-pohsuns@nvidia.com> References: <20240216210258.24855-1-pohsuns@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017091:EE_|LV8PR12MB9334:EE_ X-MS-Office365-Filtering-Correlation-Id: e03ee489-eb75-4e68-e760-08dc2f32cae7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2024 21:03:57.7427 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e03ee489-eb75-4e68-e760-08dc2f32cae7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017091.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9334 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791093723615773010 X-GMAIL-MSGID: 1791093723615773010 This change adds support for WDIOC_GETTIMELEFT so userspace programs can get the number of seconds before system reset by the watchdog timer via ioctl. Signed-off-by: Pohsun Su --- drivers/clocksource/timer-tegra186.c | 44 +++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c index 304537dadf2c..8f516366da86 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2019-2024 NVIDIA Corporation. All rights reserved. */ +#include #include #include #include @@ -29,6 +30,7 @@ #define TMRSR 0x004 #define TMRSR_INTR_CLR BIT(30) +#define TMRSR_PCV GENMASK(28, 0) #define TMRCSSR 0x008 #define TMRCSSR_SRC_USEC (0 << 0) @@ -45,6 +47,9 @@ #define WDTCR_TIMER_SOURCE_MASK 0xf #define WDTCR_TIMER_SOURCE(x) ((x) & 0xf) +#define WDTSR 0x004 +#define WDTSR_CURRENT_EXPIRATION_COUNT GENMASK(14, 12) + #define WDTCMDR 0x008 #define WDTCMDR_DISABLE_COUNTER BIT(1) #define WDTCMDR_START_COUNTER BIT(0) @@ -234,12 +239,49 @@ static int tegra186_wdt_set_timeout(struct watchdog_device *wdd, return 0; } +static unsigned int tegra186_wdt_get_timeleft(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + u32 timeleft; + u32 expiration; + + if (!watchdog_active(&wdt->base)) { + /* return zero if the watchdog timer is not activated. */ + return 0; + } + + /* + * System power-on reset occurs on the fifth expiration of the watchdog timer and so + * when the watchdog timer is configured, the actual value programmed into the counter + * is 1/5 of the timeout value. Once the counter reaches 0, expiration count will be + * increased by 1 and the down counter restarts. + * Hence to get the time left before system reset we must combine 2 parts: + * 1. value of the current down counter + * 2. (number of counter expirations remaining) * (timeout/5) + */ + + /* Get the current number of counter expirations. Should be a value between 0 and 4. */ + expiration = FIELD_GET(WDTSR_CURRENT_EXPIRATION_COUNT, readl_relaxed(wdt->regs + WDTSR)); + + /* Convert the current counter value to seconds, rounding up to the nearest second. */ + timeleft = FIELD_GET(TMRSR_PCV, readl_relaxed(wdt->tmr->regs + TMRSR)); + timeleft = (timeleft + USEC_PER_SEC / 2) / USEC_PER_SEC; + + /* + * Calculate the time remaining by adding the time for the counter value + * to the time of the counter expirations that remain. + */ + timeleft += wdt->base.timeout * (4 - expiration) / 5; + return timeleft; +} + static const struct watchdog_ops tegra186_wdt_ops = { .owner = THIS_MODULE, .start = tegra186_wdt_start, .stop = tegra186_wdt_stop, .ping = tegra186_wdt_ping, .set_timeout = tegra186_wdt_set_timeout, + .get_timeleft = tegra186_wdt_get_timeleft, }; static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *tegra, From patchwork Fri Feb 16 21:02:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pohsun Su X-Patchwork-Id: 202363 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp786455dyb; Fri, 16 Feb 2024 13:07:40 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUyanPifYT2tOzTdH45cuGgCjKm8LFrAhAWoa/bGindNBjG2rReA8M5LZ4Ej4IeGAzy59PqyNddcrML4kL/fF7njjczSA== X-Google-Smtp-Source: AGHT+IExdeoKcxJEducJ7aK4sbkwYol2RQKuBsHYMHvvT+jNSzJQ36GQXvS95nEezA6pBa9JXHAo X-Received: by 2002:a05:6808:1a13:b0:3c0:419f:e9e8 with SMTP id bk19-20020a0568081a1300b003c0419fe9e8mr7015191oib.1.1708117660519; Fri, 16 Feb 2024 13:07:40 -0800 (PST) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Date: Sat, 17 Feb 2024 05:02:58 +0800 Message-ID: <20240216210258.24855-3-pohsuns@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240216210258.24855-1-pohsuns@nvidia.com> References: <20240216210258.24855-1-pohsuns@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FD:EE_|PH0PR12MB7469:EE_ X-MS-Office365-Filtering-Correlation-Id: d42dcc06-f3f9-41a9-ea3e-08dc2f32d049 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EEKsYmdNNyqYCGXgvbqa2pz4rFHDNJyS8kSga45k8yhbk7IXAmh7yHhegZFq0WiCXWLRXfCkEo450ajUi3WPCpxAJj6aQhpc2Mayf7alOuvHqvGre6W/vm7QC94qKjUXdObT7QARTsbwmU1HUPoyVQW1vRCuVcPY0HoWGPCqffmelVm4A6PFl/BIh+NfHhllynqqHwHiu3sw7bCkibcjnw97w/uK5kWM/wnGOiMamzydijJOthzBPIMNJn1E/DcIGHUpsbIKiqgssCt62ednhFxk308gLeH/cFIHz3lXcJ64To+VRB+n4OwR4t7kjKR9P+SMmrkR70cSOxXISXmR0d1+vm0I1Og7CyjX+kLCttjNhGagLXRu2pJbNfHuW8QxrLtbvqNS9JFD8/UGMbE+XML/h25QJbxjuKMaV80uCX5Fxes7XlupZpvQZjU8ytCtr0FCY4FGEGahw9zt71R7/Z3/QMga+wDQO2Y8PFiDPTBbUxz51EgxnmRaO2dFXAVy2Nu1znKTXuS6qbSgxBTQQm88GydoupGIBCeo03VcZKvYHGrV3tfpiuO5Gpx6LGjA0aXHkZl+lETbfAySCMR92iitzMk+6MQOaRWkv6EzkIADQPC2V3+xRCZIShzFodmPLH1zergUK0ep1F8tNjsI6Mlwsp8A1EV+9VNpzAIEZZI= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(39860400002)(376002)(136003)(230922051799003)(82310400011)(451199024)(64100799003)(186009)(1800799012)(36860700004)(46966006)(40470700004)(83380400001)(7636003)(356005)(70586007)(70206006)(82740400003)(8676002)(8936002)(4326008)(2906002)(5660300002)(426003)(107886003)(336012)(2616005)(26005)(1076003)(316002)(16526019)(110136005)(41300700001)(6636002)(54906003)(6666004)(478600001)(7696005)(86362001)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2024 21:04:06.7736 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d42dcc06-f3f9-41a9-ea3e-08dc2f32d049 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7469 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791091183850960774 X-GMAIL-MSGID: 1791091183850960774 This change removes watchdog self-pinging behavior. The timer irq handler is triggered due to the 1st expiration, the handler disables and enables watchdog but also implicitly clears the expiration count so the count can only be 0 or 1. Since this watchdog supports opened, configured, or pinged by systemd, We remove this behavior or the watchdog may not bark when systemd crashes since the 5th expiration never comes. Signed-off-by: Pohsun Su --- drivers/clocksource/timer-tegra186.c | 27 ++------------------------- 1 file changed, 2 insertions(+), 25 deletions(-) diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c index 8f516366da86..acff97da138a 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -175,7 +175,8 @@ static void tegra186_wdt_enable(struct tegra186_wdt *wdt) value |= WDTCR_PERIOD(1); /* enable local interrupt for WDT petting */ - value |= WDTCR_LOCAL_INT_ENABLE; + if (0) + value |= WDTCR_LOCAL_INT_ENABLE; /* enable local FIQ and remote interrupt for debug dump */ if (0) @@ -407,23 +408,10 @@ static int tegra186_timer_usec_init(struct tegra186_timer *tegra) return clocksource_register_hz(&tegra->usec, USEC_PER_SEC); } -static irqreturn_t tegra186_timer_irq(int irq, void *data) -{ - struct tegra186_timer *tegra = data; - - if (watchdog_active(&tegra->wdt->base)) { - tegra186_wdt_disable(tegra->wdt); - tegra186_wdt_enable(tegra->wdt); - } - - return IRQ_HANDLED; -} - static int tegra186_timer_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct tegra186_timer *tegra; - unsigned int irq; int err; tegra = devm_kzalloc(dev, sizeof(*tegra), GFP_KERNEL); @@ -442,8 +430,6 @@ static int tegra186_timer_probe(struct platform_device *pdev) if (err < 0) return err; - irq = err; - /* create a watchdog using a preconfigured timer */ tegra->wdt = tegra186_wdt_create(tegra, 0); if (IS_ERR(tegra->wdt)) { @@ -470,17 +456,8 @@ static int tegra186_timer_probe(struct platform_device *pdev) goto unregister_osc; } - err = devm_request_irq(dev, irq, tegra186_timer_irq, 0, - "tegra186-timer", tegra); - if (err < 0) { - dev_err(dev, "failed to request IRQ#%u: %d\n", irq, err); - goto unregister_usec; - } - return 0; -unregister_usec: - clocksource_unregister(&tegra->usec); unregister_osc: clocksource_unregister(&tegra->osc); unregister_tsc: