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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791053253711642744 X-GMAIL-MSGID: 1791053253711642744 Document the Adreno 750 GMU found on the SM8650 platform. Reviewed-by: Konrad Dybcio Acked-by: Conor Dooley Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 4e1c25b42908..b3837368a260 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -224,6 +224,7 @@ allOf: enum: - qcom,adreno-gmu-730.1 - qcom,adreno-gmu-740.1 + - qcom,adreno-gmu-750.1 then: properties: reg: From patchwork Fri Feb 16 11:03:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 202082 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp435042dyb; Fri, 16 Feb 2024 03:05:07 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXUzHY1PxIikvEReUf1mAE99uMymrjL2GVBedTDEG7t68x/2IYwjgi2oH5blSgCDtfxV0JvZ37z3+Mqj+LjGh14nreTng== X-Google-Smtp-Source: AGHT+IG8viXke67UOAYNyz0Y19aBwaTac65/oYDCHyV9S2/Pj1LC7C3CVEx8LF+dTLDOulcXYT7T X-Received: by 2002:a05:6a00:be3:b0:6db:d5b5:e380 with SMTP id x35-20020a056a000be300b006dbd5b5e380mr4481291pfu.24.1708081506967; Fri, 16 Feb 2024 03:05:06 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708081506; cv=pass; d=google.com; s=arc-20160816; b=rB3Y3Vqi0NGeHGmwLxRARp1JbQYESbel52EvbH7S1BRkBAwgx7cxnyBy3my7p5KwRJ giSTaVuD26rFf/3tGxHW+wBhv1i3hX15Lv7n1CSa3LoWCcv9izR8CvHCC2LRmLYxumXK +V9rtmiYM19S22NnYwJMdeRDgekdXBcd1xSlYqEPU9po94iqkdnqV7Rf9m5AAEPqbuwT 7W7RU+DD37B3158yN0E5jFVLe9UQDaaH09QicrWY+12vSal0QZeMToJVwKfxHB5r6tvn RXYyolKblE8dmgeNqVvgfY+qPKPShqYRbOq1qs9YoWJV8orSZlrOalsdN368/Dt+ReUt iVeA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=AWxHJkBPvh7dfzfYkfpsJVh1kKWdDbAwY9dahQR1fTQ=; fh=+LkWBF1jiMknFRdtyUqidDqZpwC0TJCIBOSg5md6LkQ=; b=Qfxl0HqRsPE5BGv90P/NAf/OiELReM1gjfSUgUtLenL2fqnyk6n4Lnbb7rH1ce5q+A lY48kOnBnAN2I4w6IbuBBp4DvwE94reMo6wVd/1AuYvozmkIv8gway5lO03OPpHYorH5 d7htX6+kwRcy/oujmqs8IZPZUMBHmFeKob7WMKRxZhQAplxRuxHse1Omh42hsGMnm74+ fQ3PDCovRah25VnQ6LVZfY3RdgimCkYcMqBV+7cHgcjq2VRvlvwgX+gvIXoUnctYOsdZ NlLLbz0KA4ZoJaHsKTYo2gAoXlMaj5ND130AdVgmAM1czGzu4+eRR+gx59MXJX6Y60OJ UyBg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LUvD8H/0"; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68482-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68482-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791053274140918217 X-GMAIL-MSGID: 1791053274140918217 The if condition for the SM8[45]50 GPU SMMU is too large, add the other compatible strings to the condition to only allow the clocks for the GPU SMMU nodes. Fixes: 4fff78dc2490 ("dt-bindings: arm-smmu: Document SM8[45]50 GPU SMMU") Suggested-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index a4042ae24770..38c48131e6e7 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -484,7 +484,12 @@ allOf: - if: properties: compatible: - const: qcom,sm8450-smmu-500 + items: + - const: qcom,sm8450-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: properties: clock-names: @@ -508,7 +513,11 @@ allOf: - if: properties: compatible: - const: qcom,sm8550-smmu-500 + items: + - const: qcom,sm8550-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 then: properties: clock-names: From patchwork Fri Feb 16 11:03:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 202083 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp435337dyb; Fri, 16 Feb 2024 03:05:35 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWbn3rboknRo5ZvqHxhIFl7VBwau5HtHjQT51y9CiCVmKtSC6MKGPfyvrK2DyiMxZECJ3k+EygyL9kqjZ4USLcs9HkRMw== X-Google-Smtp-Source: AGHT+IHLq2/CL67J2nedNgKlXDrR5IIEzh2Ow5yvQNicTGYFXyzQDb9VYcAuJjUpTkeNRTXenVVH X-Received: by 2002:a05:6830:1355:b0:6e2:f1ce:4e88 with SMTP id r21-20020a056830135500b006e2f1ce4e88mr4747770otq.19.1708081535012; Fri, 16 Feb 2024 03:05:35 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708081534; cv=pass; d=google.com; s=arc-20160816; b=COuFoYDaNMHdeAeccp5JpH0tISrOHBn7ODC8TBM8ERRDXj3/myPWNdMR3K5DrZSAXS dROa7LPv29JY8SygDv1OqfX1ED4b4Uk+8Fn8urEyMZGHFl7B5DhrA7NMaxCu++KJSocl PXtocE3cQ5mfEul/SCeNQ931jadUw2bI2OtVsnhlbgr7RM4i7hJ1yQYPYEI+YX/SjnTO 0taZk096iKYibbLg+5zX5ZrRs2NtT3J+z/14n/25EUYiFLP2o6CxUvPRk9jvoT9bdfb3 skhyBxFQbYyTjtJIH/H8AuRnxVgjDBcD5Ije2d6lOMtPPRC4VwJ94LXEil8/CsDbsTOD 4zTA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=R8jQXdAWc83YqnRTlVrzU/De4ogxASBLVUqo6LYFo1E=; fh=VrX1l/WKufykqIq7lwVEL49hFaHO+6h/XpSN0CtPkRo=; b=AisESWn4bAa4WptWl/MES213xgtLPtyemjYvs47IuyHh7ziqTzNrXwH3LsTKHb1mTH aGhq7/uAnnY9soB0aO5jHDA6cwOROoVX2W0Y2PDmVqWHKUlOJBu8BFgljnCLYU+VlpqJ +BYcRr5m1dqxAyrBF5T6DQwTr3fC989XHW+bTxObALX7v5GsnBdx35pYSYBuBaonuOv3 alIMH24jSIN1NFubBng9BH49Lu/4JJ8oJKZaesTnE6TplokG/AlO0dozuSeBcqPGgwkm 4f9Qy0+IhR9rPMUv3C39ojE02yJuTI/rS2FwiNiKqNBfDmb7bjY7975KIXYtIobePKGc 7cTg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PGROFv7B; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68483-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68483-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791053303870205295 X-GMAIL-MSGID: 1791053303870205295 Document the GPU SMMU found on the SM8650 platform. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 38c48131e6e7..740631782540 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -93,6 +93,7 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -514,7 +515,9 @@ allOf: properties: compatible: items: - - const: qcom,sm8550-smmu-500 + - enum: + - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -553,7 +556,6 @@ allOf: - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 then: properties: From patchwork Fri Feb 16 11:03:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 202095 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp438390dyb; Fri, 16 Feb 2024 03:11:34 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCX47rhUxIFa1RRSwzQePCjW/SRFhspvrjLaB6zcjM9G3MBhJ8w9x6CUocLIGmNAXslQi43lS11NYiHZKydhd7GwzA6cIw== X-Google-Smtp-Source: AGHT+IEh2m/1jNRFiAWnV/lfKP1gADqL4ENlz+MRIQEllQvyIZBy5BFC62k62KsuLVXumJ341GfJ X-Received: by 2002:a17:902:b944:b0:1d9:893f:cd06 with SMTP id h4-20020a170902b94400b001d9893fcd06mr3943133pls.60.1708081894263; Fri, 16 Feb 2024 03:11:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708081894; cv=pass; d=google.com; s=arc-20160816; b=Seb/baBOKoVYKzFhqvB9OcMzKFt0ZgtuzCvxgB/zlAhLMmJHlQqJA8qKkpdrS6HF4V 4jDBqXcZ48GjoCf2raIAXVuDX3GlLBUdvdxfkVWJpsl9p2UPICQjN4ovzrW7quomozOx jnG/e7n1RZQyc8nMDUJTCIQaB4QoFdwX/VRbaAVe1XH+CkyLPtWbIO2udY05gUUR8ZLY IjDbu7sUlqxPasU3sRA/VyU5uyD7Czpd6DYii8oY3iz+q2MzFbd0RMyk9gam8R0W1Nvw /Fc+HijxngzIdjlbC4b7385lxCf4kZ9In0MuRXZX/HPmWOjXwr5xkq4zCTfaKxh+3i/m oagQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=5ygFt5WEvBpqUpx/ZfEWpp/27W6mJ4fXmmus9YC0aao=; fh=0BTQf3mcvTXMbMI7rGbjeSsehtplrKujV0T7OVUCsTA=; b=BbPeHv2swrGTIfQFTD+Ywx8JV1TzNAVmzF18McCnzUAJCJcVhArQBQTGArVbVPPIl/ GfHJ4lMRBAVX3PUAW+2RNk7yij5ykViNQWFVWN4+qmod8hD6tOJ4YKQEPPCZH31QZTE0 WGRFlgJMqcVqp6ErMI6s8Z3Y7QrETw6JtyM9geXCAj/iuokOmtO1wovp07PopFn4PKrX YCGWEcG8zJ2AKoZjahj28bOocS3/vRicpxktY4gYoeBb1LKA7aQt+uwLJ6LnlLPmhqW7 05D3voAr2vOy1snEzsCNO65KeLWFzFstia2P1yNDGxzn+DJX14cTEJwj5aMk+JYGmgyy qk5w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZafwBbBC; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68484-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68484-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791053680229572712 X-GMAIL-MSGID: 1791053680229572712 Sync missing regs for A750 clock gating control related registers from Mesa a6xx.xml.h generated file. Those registers were added in the !27576 merge request [1]. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27576 Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 863b5e3b0e67..58877464692a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1725,6 +1725,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 +#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad + #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 @@ -1939,12 +1941,19 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d +#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e + +#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f + #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122 +#define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001 + #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff From patchwork Fri Feb 16 11:03:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 202084 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp435516dyb; Fri, 16 Feb 2024 03:05:56 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWBZnGpaZ1T/TIRlHWEAzz/aAXw3vuRhb7+Iv90S0ir6OpkuwAw9ajOHaP+vKfbdEj2JOynLFC4uZlbLCQB7ODbOgUtSQ== X-Google-Smtp-Source: AGHT+IHKhV9SoJl5k31ZMVOzT0fEYkH3HceYr4uMMCxprU+Ny+ysX2UASZB8/ZT4ywKdhugG0ElR X-Received: by 2002:a17:902:e810:b0:1db:4c96:b578 with SMTP id u16-20020a170902e81000b001db4c96b578mr5852874plg.59.1708081555832; Fri, 16 Feb 2024 03:05:55 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708081555; cv=pass; d=google.com; s=arc-20160816; b=d8rKep/zLeJnjn0zocNmrMg03FsF8LhXkxwB/Ry1KqEcHEkuweSoxRD7dLyL78Uxr7 YZbnvty0J1rGMqRrvJOm05bUvPpsHC5Jhy4kUWylrEWuUqejdTdPdqN/+tfuvFP0HXOQ 5MBijoy4LqULIsqdECe2fEub6IaVTKCYjyBlVMFK1NZCoxi/AYuJ9Jkoh/5y4jXJ1dL2 d7kdIAb1NavP22NwazTXHvdHoT7YiU/Pjx3rZeBP0vEZCtlwnKbqo0fzuyniznRah9GD ajjQbbTnell+baJxqvb6XOMc2JDeY2JhZMRYHq2Iq3ZtG4R3ZvYfPwoUMH0BF3BA8Pnv 9FiA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=L+fXQpNXys7p6pXfZBQpQvrvkqt8y/igppueslu3480=; fh=8I+bnjxzAnasIRRH6BBRTwaRXqyW2A8skXePxCncWJk=; b=PN4cFjncIhbS4z7lQOhU/5ER+RlL3cvAhKI1F1Igz5ZA84FFOXx4SR0Y46sBUEkCBj pOm8H6Qd2HLU6NhyV2J20DKZixnOSSzN9tCafV3l+AHW74CxNd+S+TDs1aO88MdEmxnR 5uq1vUM9ldSB/4PC47pPCI8T9lyNXUg9WUT8TIpo/cKw0Knlc81lCrSGNkBwRljuG1sp NZQVDamWXo7KCx84hUkaZzN3wJyPLQwJCL4SDxh1Zth8yzWQ7c9hY5tL93I7/t2a16yg 19QMjAPJhECgS+W43Vf+Xzu+by34FeNraepHlLSpb+xQlDlsSNzwyWaRVijVscCXfPnf aDWA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qKgPLDQd; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68485-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68485-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791053325141027133 X-GMAIL-MSGID: 1791053325141027133 Add support for the A750 GPU found on the SM8650 platform Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++++++-- 4 files changed, 49 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 8c4900444b2c..325881d8ff08 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -842,6 +842,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) */ if (adreno_is_a740(adreno_gpu)) chipid_min = 2; + else if (adreno_is_a750(adreno_gpu)) + chipid_min = 9; else return -EINVAL; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c9c55e2ea584..475b601a48ee 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -961,7 +961,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) unsigned int i; u32 val, clock_cntl_on, cgc_mode; - if (!adreno_gpu->info->hwcg) + if (!(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu))) return; if (adreno_is_a630(adreno_gpu)) @@ -982,6 +982,25 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) state ? 0x5555 : 0); } + if (!adreno_gpu->info->hwcg) { + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); + gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); + + if (state) { + gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); + + if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, + val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { + dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); + return; + } + + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); + } + + return; + } + val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); /* Don't re-program the registers if they are already correct */ @@ -1239,7 +1258,9 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) count = ARRAY_SIZE(a660_protect); count_max = 48; BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); - } else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) { + } else if (adreno_is_a730(adreno_gpu) || + adreno_is_a740(adreno_gpu) || + adreno_is_a750(adreno_gpu)) { regs = a730_protect; count = ARRAY_SIZE(a730_protect); count_max = 48; @@ -2880,7 +2901,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || - config->info->family == ADRENO_7XX_GEN2; + config->info->family == ADRENO_7XX_GEN2 || + config->info->family == ADRENO_7XX_GEN3; a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2ce7d7b1690d..e2582c91d7e7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -522,6 +522,20 @@ static const struct adreno_info gpulist[] = { .zapfw = "a740_zap.mdt", .hwcg = a740_hwcg, .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ + .family = ADRENO_7XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "gen70900_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70900.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "gen70900_zap.mbn", + .address_space_size = SZ_16G, }, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index bc14df96feb0..9e9415df2cea 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -48,6 +48,7 @@ enum adreno_family { ADRENO_6XX_GEN4, /* a660 family */ ADRENO_7XX_GEN1, /* a730 family */ ADRENO_7XX_GEN2, /* a740 family */ + ADRENO_7XX_GEN3, /* a750 family */ }; #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) @@ -423,12 +424,17 @@ static inline int adreno_is_a740(struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x43050a01; } -/* Placeholder to make future diffs smaller */ +static inline int adreno_is_a750(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x43051401; +} + static inline int adreno_is_a740_family(struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return gpu->info->family == ADRENO_7XX_GEN2; + return gpu->info->family == ADRENO_7XX_GEN2 || + gpu->info->family == ADRENO_7XX_GEN3; } static inline int adreno_is_a7xx(struct adreno_gpu *gpu) From patchwork Fri Feb 16 11:03:53 2024 Content-Type: text/plain; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791053347376909608 X-GMAIL-MSGID: 1791053347376909608 Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++++++++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 62e6ae93a9a8..27dcef27b6ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2589,6 +2589,128 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43051401", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-629000000 { + opp-hz = /bits/ 64 <629000000>; + opp-level = ; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = ; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-level = ; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + }; + + opp-231000000 { + opp-hz = /bits/ 64 <231000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = ; + }; + + opp-260000000 { + opp-hz = /bits/ 64 <260000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8650-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -2602,6 +2724,50 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; From patchwork Fri Feb 16 11:03:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 202086 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp435713dyb; Fri, 16 Feb 2024 03:06:17 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVlQno3OvSfyHgDsveeDO0g6mgfz9RwrqkpGItJw+jG6NScjOkg4QjWKHCpsgg4Qi0ivWLJYIULtYHadlnUyABV2uMKSA== X-Google-Smtp-Source: AGHT+IFZ/aHIrUESVAmVTrpUTROpk6oWsYI1zhV/NkO73TYXRoIwtCQeS+Ws4gPwMuEEGh0dJT7x X-Received: by 2002:a0c:e105:0:b0:68f:2b19:5359 with SMTP id w5-20020a0ce105000000b0068f2b195359mr3107456qvk.64.1708081577540; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791053348258220335 X-GMAIL-MSGID: 1791053348258220335 Add path of the GPU firmware for the SM8650-QRD board Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b07cac2e5bc8..dc91f0bf4b8c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -766,6 +766,14 @@ &ipa { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21";