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Signed-off-by: Antonio Borneo Fixes: 046a6ee2343b ("irqchip: Bulk conversion to generic_handle_domain_irq()") --- drivers/irqchip/irq-stm32-exti.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index 971240e2e31b..69982f21126a 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -322,7 +322,7 @@ static void stm32_irq_handler(struct irq_desc *desc) while ((pending = stm32_exti_pending(gc))) { for_each_set_bit(n, &pending, IRQS_PER_BANK) generic_handle_domain_irq(domain, irq_base + n); - } + } } chained_irq_exit(chip, desc); From patchwork Fri Feb 16 09:47:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonio Borneo X-Patchwork-Id: 202024 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp403959dyb; Fri, 16 Feb 2024 01:51:09 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWilgTS/lygrYvGj6sB2UcTs3Ap5detAVzd16ShaTuE8cjwIFsqSChAq/wKUpT2Q1FxC6Hpzm+jIh82a1YBNoktSpXa0w== X-Google-Smtp-Source: AGHT+IFEHahYJSOYQVrKcdea0weZgaqQ3xRDs1P4tHtQlO7E9C7MWBwsjm144GMqa/OFssfONjLL X-Received: by 2002:a17:902:eaca:b0:1d7:4353:aba5 with SMTP id p10-20020a170902eaca00b001d74353aba5mr3999606pld.58.1708077069528; Fri, 16 Feb 2024 01:51:09 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708077069; cv=pass; d=google.com; s=arc-20160816; b=i6hDaUV7H1acQ8ChaEduSj+8UPuM2IU+qeffvVDh70D2ARWnvRHDHnvDrRcOYS+RQL o9P/tNssUt+mS+Y3pDltPgKdewEqaqEmjbFlZf5ZY2ZvI2E7yAocLJqmG2IXOopa6vWI 9vEz9tjP9aJenT6Gy3zl2h+vrYC85Txr8uUGugZazF/xy2IJIrEgHIWR+UdtOA9KLkuR j6fV/LWs34mOm8IkgxvXgcNmNUyL0PZKKxr/WEv2IBRPdLIDmMZw1YN8Z8gAXJ6xi2UM SIUULRrHNtN03WYN/CLtbBe6ja7kyzLOBdPZC2k4MkOlHmH0gkqxgJeRvlYGgGjos+/+ FH5Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=6oy4aiUMKITAZcOmFqBjM6ZnhYNqhJFyPyPaNACQD3I=; fh=zaA9bUHoUhiJg2MlubcoK2u7vo9XLyUWHzXlN8LwtMY=; b=CIbt3WdIr1x3+R3NR0GGkT/x1HPSeMHT06lCW+OIyr9AWN+TvhPVKRBbaIO17T3Vh1 5IO8SuS2tOwLwPuDmQHsq4ipopM2ISJsRhjjB96knwSxazPddtIIeoTPC2wD7SwbsTht whEOIcKLvgz4nSTRafwzoB5tyxJddzolFDm4XAAGRCFIHLNeEYmiK/DtZEOkIosd3Xl5 vBJLc/D2qYO5PA/kvZrW3piWj3i+M//ppSE8Iiy7zBHdZhVKxsBzRZTe8MsUci4GRlSJ H5ZQUfO87mqhkD3L2dX7oUi2S0mdpIPoGde57shwbB/vjUyUfn43M4jD0SgCtn9FyXXN Eo8Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=RbZppuBS; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-68359-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68359-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Fri, 16 Feb 2024 10:49:03 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3D0A8237D75; Fri, 16 Feb 2024 10:48:18 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:48:17 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , , Fabrice Gasnier Subject: [PATCH 02/12] dt-bindings: interrupt-controller: stm32-exti: Add irq nexus child node Date: Fri, 16 Feb 2024 10:47:47 +0100 Message-ID: <20240216094758.916722-3-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791048621300571835 X-GMAIL-MSGID: 1791048621300571835 The mapping of EXTI interrupts to its parent interrupt controller is both SoC and instance dependent. The current implementation requires adding a new table to the driver's code and a new compatible for each new EXTI instance. Add to the binding an interrupt nexus child node that will be used on the new EXTI instances and can be optionally used on the existing instances. The property 'interrupt-map' in the nexus node maps each EXTI interrupt to the parent interrupt. Align #address-cells and #interrupt-cells between the EXTI node and its nexus node. Signed-off-by: Antonio Borneo Signed-off-by: Fabrice Gasnier --- .../interrupt-controller/st,stm32-exti.yaml | 42 ++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml index 00c10a8258f1..1a4cf9537b9e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml @@ -26,6 +26,9 @@ properties: "#interrupt-cells": const: 2 + "#address-cells": + const: 0 + reg: maxItems: 1 @@ -42,6 +45,24 @@ properties: description: Interrupts references to primary interrupt controller + exti-interrupt-map: + type: object + properties: + interrupt-map: true + + interrupt-map-mask: true + + "#interrupt-cells": + const: 2 + + "#address-cells": + const: 0 + + required: + - interrupt-map + - "#interrupt-cells" + - "#address-cells" + required: - "#interrupt-cells" - compatible @@ -89,8 +110,27 @@ examples: reg = <0x5000d000 0x400>; }; + - | //Example 2 - exti2: interrupt-controller@40013c00 { + #include + exti2: interrupt-controller@5000d000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + exti-interrupt-map { + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-map-mask = <0xffffffff 0>; + interrupt-map = + <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + - | + //Example 3 + exti3: interrupt-controller@40013c00 { compatible = "st,stm32-exti"; interrupt-controller; #interrupt-cells = <2>; From patchwork Fri Feb 16 09:47:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonio Borneo X-Patchwork-Id: 202022 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp403904dyb; Fri, 16 Feb 2024 01:50:58 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWW5ORCldy907Nyi51B+tXE542wzqCIbON7OD9Y1tFs4c7Q7ud9mIXPAHdrAvv0oARYWiiiXMZhIx4sGtcTpO9vM87idg== X-Google-Smtp-Source: AGHT+IE1PR7PazEe8Z6hM9Wdb+GG/gKTg93xsaWi/ureGvUUW/ijkWkyKyOSHjPqDPiTkU78nxVD X-Received: by 2002:a17:90b:154b:b0:299:ed7:24fc with SMTP id ig11-20020a17090b154b00b002990ed724fcmr3354588pjb.49.1708077058208; Fri, 16 Feb 2024 01:50:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708077058; cv=pass; d=google.com; s=arc-20160816; b=D6CiYOPX+nMzs0a4YB5MRrQEwfAkWN5x7bpRIcIEXGDCVhErwfyEKK54+EjJsOXunW UZs+ZJfvQVH75JVRus65ljhh8BCEK79i7mn+DC6D1CahwxIDN9V+jZ5/MV8oMSep60DV duFmnHiYkD40FZSOzKf2udYqEfC9AVwCv40pHEFHjNoIcDnAlm1Rv/BD4/95cEkVKeh+ kvc9Ux+njvUXRHIHbuJKhE+NZU5cb2ovZTs/Rw0xy1Ief51aR9JgO24fUd+n9riHeut6 LHhTEBtDZAbE7MdkBkB6e1wwtM4VL9xxMrY8CmrmQEDI6KF4ax8KYNcJ5+gmsABPYCnj isWQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=CQbKI3q6/SH3YpK3aFqJIfLPoWvnVZQLDfz/UiKph8I=; fh=xpn1PluZzGII3Xn6bg0JImd3eiUxde5K1Wn2dsUYIIA=; b=BtpjGpRvzXVFOl9zIc+PAQozsZTu6bxg/KlPbzRfHE0qCnSs4DTdPKA0gcxoAQWNJ0 dBCr88xvzcETpeM7F+yq1VeOOSwTN/ZSMTK5q+Ec1g7tsrzwG2sHK7uTMaKWbRbVcOUz GXBr/2/OsXgkY7CMEse0K49rsmXc9Fv6vn7Km/cMecQcMfvO9/Mg7FxGZ1lSU9x2uNBV afAJYINLcmp1TQlg7tomC5mr/JZzmfItK8zCOmyFPvnVBHKgtBVPQ/bdm+9f7rnhWtAR 1RQlDKspmPzk6+uKaX209hxaKQP+nt/4v0xN2WpGwXf+JMpJQSHpVkK/CauyJt1Tn3rj kH6Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=NxzL8TLZ; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-68358-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68358-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Fri, 16 Feb 2024 10:49:03 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D1539237D79; Fri, 16 Feb 2024 10:48:18 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:48:18 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 03/12] irqchip/stm32-exti: Map interrupts through interrupt nexus node Date: Fri, 16 Feb 2024 10:47:48 +0100 Message-ID: <20240216094758.916722-4-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791048609598103478 X-GMAIL-MSGID: 1791048609598103478 The mapping of EXTI interrupts to its parent interrupt controller is both SoC and instance dependent. The current implementation requires adding a new table to the driver's code and a new compatible for each new EXTI instance. Check for the presence of the optional interrupt nexus child node and use its property 'interrup-map' to map EXTI interrupts to the parent's interrupts. For old DT's without the optional nexus child node, the driver's behavior is unchanged, thus keeps backward compatibility. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index 69982f21126a..95bb3dd10b2c 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -61,6 +61,7 @@ struct stm32_exti_host_data { struct stm32_exti_chip_data *chips_data; const struct stm32_exti_drv_data *drv_data; struct hwspinlock *hwlock; + struct device_node *irq_map_node; }; static struct stm32_exti_host_data *stm32_host_data; @@ -713,8 +714,9 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm, u8 desc_irq; struct irq_fwspec *fwspec = data; struct irq_fwspec p_fwspec; + struct of_phandle_args out_irq; irq_hw_number_t hwirq; - int bank; + int bank, ret; u32 event_trg; struct irq_chip *chip; @@ -731,6 +733,25 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm, irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); + if (host_data->irq_map_node) { + out_irq.np = host_data->irq_map_node; + out_irq.args_count = 2; + out_irq.args[0] = fwspec->param[0]; + out_irq.args[1] = fwspec->param[1]; + + ret = of_irq_parse_raw(NULL, &out_irq); + if (ret) + return ret; + /* we only support one parent, so far */ + if (of_node_to_fwnode(out_irq.np) != dm->parent->fwnode) + return -EINVAL; + + of_phandle_args_to_fwspec(out_irq.np, out_irq.args, + out_irq.args_count, &p_fwspec); + + return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); + } + if (!host_data->drv_data->desc_irqs) return -EINVAL; @@ -908,7 +929,7 @@ static int stm32_exti_probe(struct platform_device *pdev) { int ret, i; struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; + struct device_node *child, *np = dev->of_node; struct irq_domain *parent_domain, *domain; struct stm32_exti_host_data *host_data; const struct stm32_exti_drv_data *drv_data; @@ -976,6 +997,10 @@ static int stm32_exti_probe(struct platform_device *pdev) if (ret) return ret; + child = of_get_child_by_name(np, "exti-interrupt-map"); + if (child && of_property_read_bool(child, "interrupt-map")) + host_data->irq_map_node = child; + stm32_exti_h_syscore_init(host_data); return 0; From patchwork Fri Feb 16 09:47:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonio Borneo X-Patchwork-Id: 202023 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp403913dyb; Fri, 16 Feb 2024 01:50:59 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVB2B0rKJaspaHVeBa5u82G+SWSlB/UWSVMseL2okWiyiIKJDWNANXh6YS9xP6AXqeHjupaYKav8gXgQZCdfm8f/z+JwA== X-Google-Smtp-Source: AGHT+IHumA58U//UX76mX+OqhXvQanAg8DPwNXawWOI/LJhQjUQjHEqZTwDhOhkSEoyCSXVN5nNW X-Received: by 2002:a17:906:46d1:b0:a3d:300d:4f0b with SMTP id k17-20020a17090646d100b00a3d300d4f0bmr3179160ejs.32.1708077059190; Fri, 16 Feb 2024 01:50:59 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708077059; cv=pass; d=google.com; s=arc-20160816; b=Rq8KPPquedomG38dLeF++2iReAuSIxRRKS8nMtIblKtV4XzL9TfSMpfF0II0U0jY5Y MHIc19Muzvd42y25vj9wpvT+KV0O88L07Tq9sRJsUMrhUFMZSCT2493sH2PEKHYZ9jDV lgcc8BSnBY/GWHfRCj4UJ1EIyHMZuqjwa/95jnmo3anIGxebouEVWDlkQFwaU2sOYIxz qaqcRh5kjWmlxRv4jJcIpl9h0GcYnAPbI2Bq22GtA5i/eS39aanytcXFuBLffRx4vTuf aqq89aaAOqmpfys/ti8GgODChWEuiCb+Zt1Y5IHjtPWqbrRVGEFwdyA/3bvLxK5dmvjd 5Nhw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=TGty+ngzeg7A5dCR3wVNlt1JicJKb8JKWR8Q6qrUtAE=; fh=xpn1PluZzGII3Xn6bg0JImd3eiUxde5K1Wn2dsUYIIA=; b=Vt3EQMQMV1MDKHuPaYYOxJMlvNnNfgKmj9MOL8N6hq4f4fiEQCPWIfjkA8zf3kXLnm ekPWvgU974J5mqCzmFi9zehqAoEVoCET8WGnHGHVucuuhUvaeI4qcFg+9nKDuUdSOKdN ASdDb7HEQgt6JSK50dAFuLKmSABaMWf61mQajRPsTncKULQgAL3Ffjx9yKH4/speHieK 9Qcl8rlo3x6GHZ8nQdT4480ykQ4cB0mt3ops5PzMxG354NknfbieBO9SEyPg4Q/0qfb5 QQbJGTY1tUKYR6ZcuMTQcYy9Rxdgk/4IesLOc0z63+bBOylOFfIzlT1PnVnaBFHM0+Ou uSMw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=YVHE4ir1; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-68362-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68362-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Fri, 16 Feb 2024 10:49:03 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 685D2237D77; Fri, 16 Feb 2024 10:48:19 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:48:19 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 04/12] irqchip/stm32-exti: Convert driver to standard PM Date: Fri, 16 Feb 2024 10:47:49 +0100 Message-ID: <20240216094758.916722-5-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791048610368380191 X-GMAIL-MSGID: 1791048610368380191 All driver's dependencies for suspend/resume have been fixed long ago. There are no more reasons to use syscore PM for the part of this driver related to Cortex-A MPU. Switch to standard PM using NOIRQ_SYSTEM_SLEEP_PM_OPS, so all the registers of the interrupt controller get resumed before any irq gets enabled. A side effect of this change is to drop the only global variable 'stm32_host_data', used to keep the driver's data for syscore_ops. This makes the driver ready to support multiple EXTI instances. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 58 ++++++++++---------------------- 1 file changed, 17 insertions(+), 41 deletions(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index 95bb3dd10b2c..de18cddf6b88 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include @@ -64,8 +64,6 @@ struct stm32_exti_host_data { struct device_node *irq_map_node; }; -static struct stm32_exti_host_data *stm32_host_data; - static const struct stm32_exti_bank stm32f4xx_exti_b1 = { .imr_ofst = 0x00, .emr_ofst = 0x04, @@ -622,50 +620,32 @@ static int stm32_exti_h_set_affinity(struct irq_data *d, return IRQ_SET_MASK_OK_DONE; } -static int __maybe_unused stm32_exti_h_suspend(void) +static int stm32_exti_h_suspend(struct device *dev) { + struct stm32_exti_host_data *host_data = dev_get_drvdata(dev); struct stm32_exti_chip_data *chip_data; int i; - for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { - chip_data = &stm32_host_data->chips_data[i]; - raw_spin_lock(&chip_data->rlock); + for (i = 0; i < host_data->drv_data->bank_nr; i++) { + chip_data = &host_data->chips_data[i]; stm32_chip_suspend(chip_data, chip_data->wake_active); - raw_spin_unlock(&chip_data->rlock); } return 0; } -static void __maybe_unused stm32_exti_h_resume(void) +static int stm32_exti_h_resume(struct device *dev) { + struct stm32_exti_host_data *host_data = dev_get_drvdata(dev); struct stm32_exti_chip_data *chip_data; int i; - for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { - chip_data = &stm32_host_data->chips_data[i]; - raw_spin_lock(&chip_data->rlock); + for (i = 0; i < host_data->drv_data->bank_nr; i++) { + chip_data = &host_data->chips_data[i]; stm32_chip_resume(chip_data, chip_data->mask_cache); - raw_spin_unlock(&chip_data->rlock); } -} -static struct syscore_ops stm32_exti_h_syscore_ops = { -#ifdef CONFIG_PM_SLEEP - .suspend = stm32_exti_h_suspend, - .resume = stm32_exti_h_resume, -#endif -}; - -static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data) -{ - stm32_host_data = host_data; - register_syscore_ops(&stm32_exti_h_syscore_ops); -} - -static void stm32_exti_h_syscore_deinit(void) -{ - unregister_syscore_ops(&stm32_exti_h_syscore_ops); + return 0; } static int stm32_exti_h_retrigger(struct irq_data *d) @@ -792,8 +772,6 @@ stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, goto free_chips_data; } - stm32_host_data = host_data; - return host_data; free_chips_data: @@ -919,12 +897,6 @@ static void stm32_exti_remove_irq(void *data) irq_domain_remove(domain); } -static int stm32_exti_remove(struct platform_device *pdev) -{ - stm32_exti_h_syscore_deinit(); - return 0; -} - static int stm32_exti_probe(struct platform_device *pdev) { int ret, i; @@ -938,6 +910,8 @@ static int stm32_exti_probe(struct platform_device *pdev) if (!host_data) return -ENOMEM; + dev_set_drvdata(dev, host_data); + /* check for optional hwspinlock which may be not available yet */ ret = of_hwspin_lock_get_id(np, 0); if (ret == -EPROBE_DEFER) @@ -1001,8 +975,6 @@ static int stm32_exti_probe(struct platform_device *pdev) if (child && of_property_read_bool(child, "interrupt-map")) host_data->irq_map_node = child; - stm32_exti_h_syscore_init(host_data); - return 0; } @@ -1014,12 +986,16 @@ static const struct of_device_id stm32_exti_ids[] = { }; MODULE_DEVICE_TABLE(of, stm32_exti_ids); +static const struct dev_pm_ops stm32_exti_dev_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_exti_h_suspend, stm32_exti_h_resume) +}; + static struct platform_driver stm32_exti_driver = { .probe = stm32_exti_probe, - .remove = stm32_exti_remove, .driver = { .name = "stm32_exti", .of_match_table = stm32_exti_ids, + .pm = &stm32_exti_dev_pm_ops, }, }; From patchwork Fri Feb 16 09:47:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonio Borneo X-Patchwork-Id: 202025 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp404458dyb; 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Fri, 16 Feb 2024 10:50:04 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 38326237D78; Fri, 16 Feb 2024 10:49:22 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:49:21 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 05/12] irqchip/stm32-exti: Skip secure events Date: Fri, 16 Feb 2024 10:47:50 +0100 Message-ID: <20240216094758.916722-6-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791048700966038718 X-GMAIL-MSGID: 1791048700966038718 Secure OS can reserve some EXTI event, marking them as "secure" by setting the corresponding bit in register SECCFGR (aka TZENR). These events cannot be used by Linux. Read the list of reserved events and check it during irq domain allocation. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index de18cddf6b88..85a40e07fbc3 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -36,6 +36,7 @@ struct stm32_exti_bank { u32 rpr_ofst; u32 fpr_ofst; u32 trg_ofst; + u32 seccfgr_ofst; }; #define UNDEF_REG ~0 @@ -54,10 +55,12 @@ struct stm32_exti_chip_data { u32 mask_cache; u32 rtsr_cache; u32 ftsr_cache; + u32 event_reserved; }; struct stm32_exti_host_data { void __iomem *base; + struct device *dev; struct stm32_exti_chip_data *chips_data; const struct stm32_exti_drv_data *drv_data; struct hwspinlock *hwlock; @@ -73,6 +76,7 @@ static const struct stm32_exti_bank stm32f4xx_exti_b1 = { .rpr_ofst = 0x14, .fpr_ofst = UNDEF_REG, .trg_ofst = UNDEF_REG, + .seccfgr_ofst = UNDEF_REG, }; static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { @@ -93,6 +97,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b1 = { .rpr_ofst = 0x88, .fpr_ofst = UNDEF_REG, .trg_ofst = UNDEF_REG, + .seccfgr_ofst = UNDEF_REG, }; static const struct stm32_exti_bank stm32h7xx_exti_b2 = { @@ -104,6 +109,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = { .rpr_ofst = 0x98, .fpr_ofst = UNDEF_REG, .trg_ofst = UNDEF_REG, + .seccfgr_ofst = UNDEF_REG, }; static const struct stm32_exti_bank stm32h7xx_exti_b3 = { @@ -115,6 +121,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = { .rpr_ofst = 0xA8, .fpr_ofst = UNDEF_REG, .trg_ofst = UNDEF_REG, + .seccfgr_ofst = UNDEF_REG, }; static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { @@ -137,6 +144,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = { .rpr_ofst = 0x0C, .fpr_ofst = 0x10, .trg_ofst = 0x3EC, + .seccfgr_ofst = 0x14, }; static const struct stm32_exti_bank stm32mp1_exti_b2 = { @@ -148,6 +156,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = { .rpr_ofst = 0x2C, .fpr_ofst = 0x30, .trg_ofst = 0x3E8, + .seccfgr_ofst = 0x34, }; static const struct stm32_exti_bank stm32mp1_exti_b3 = { @@ -159,6 +168,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b3 = { .rpr_ofst = 0x4C, .fpr_ofst = 0x50, .trg_ofst = 0x3E4, + .seccfgr_ofst = 0x54, }; static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { @@ -707,6 +717,12 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm, bank = hwirq / IRQS_PER_BANK; chip_data = &host_data->chips_data[bank]; + /* Check if event is reserved (Secure) */ + if (chip_data->event_reserved & BIT(hwirq % IRQS_PER_BANK)) { + dev_err(host_data->dev, "event %lu is reserved, secure\n", hwirq); + return -EPERM; + } + event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst); chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? &stm32_exti_h_chip : &stm32_exti_h_chip_direct; @@ -806,6 +822,10 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, if (stm32_bank->emr_ofst != UNDEF_REG) writel_relaxed(0, base + stm32_bank->emr_ofst); + /* reserve Secure events */ + if (stm32_bank->seccfgr_ofst != UNDEF_REG) + chip_data->event_reserved = readl_relaxed(base + stm32_bank->seccfgr_ofst); + pr_info("%pOF: bank%d\n", node, bank_idx); return chip_data; @@ -911,6 +931,7 @@ static int stm32_exti_probe(struct platform_device *pdev) return -ENOMEM; dev_set_drvdata(dev, host_data); + host_data->dev = dev; /* check for optional hwspinlock which may be not available yet */ ret = of_hwspin_lock_get_id(np, 0); From patchwork Fri Feb 16 09:47:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonio Borneo X-Patchwork-Id: 202026 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp404630dyb; Fri, 16 Feb 2024 01:52:54 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVSjwfFxCu4UN8gPoElqbAUiRLi1tr7DTBSpLmXvLQqkBUaNVx7S7m6cYghuJhm5teXF63j6JtrcwII6vX/TpHE7IYvDA== X-Google-Smtp-Source: AGHT+IHpJDpYiy/NLMLjzOO3clxePV1nugWdj5HavO9TmpKfIRuco+q+m7Nfxgv66aUlopZz7bfZ X-Received: by 2002:a05:6402:4306:b0:563:bd85:bc49 with SMTP id m6-20020a056402430600b00563bd85bc49mr3391831edc.12.1708077174085; Fri, 16 Feb 2024 01:52:54 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708077174; cv=pass; d=google.com; s=arc-20160816; b=dy6zgW+Z5SGYKEmpiwNpOsKg1nN7TD2l6a+DlOUSk9pzYU6PLTsQDn7ebV6GcRJSZJ kYjXIma+L7V6iCMWHPrxQUHrG6Gqk6Pk+2CQcP/iM0ET275nYQ9tUgbg6hS0pUMtNZ7B Jhp3verrxoA753OobdgsCnvieh6/k1xIDleBgQ5OGvKFZeliW0CjW5NGqAy3nH5dX0l7 W8bcSOWxJvQzQWalJPuT6hD76lb7fQW4NJ0h/pJBd58emq7BDA83bOUNRL/7elUXM1uA Hx5eDkYZs9LHdX+hsENb2SYjcK8K+QOPxtsY5pYKL4ZfeOdF+DoxvuOxnfBZSsAWTfjS s+AQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=o4W8pQnGZn5dw+D4cNQT9wm6+zlZJlcd/u0mhxC9pWw=; fh=xpn1PluZzGII3Xn6bg0JImd3eiUxde5K1Wn2dsUYIIA=; b=tuu5dyl8Qu/CsWiam91/y98IuA73VC2mXqlfLsV3bDqwLKyKals/6kMwjwQdSKvt2y BXSBsClgNfcAs8jbxAn05zowLANpEkROZK1wyxga0/4qx264HsbgMf+p6zrDCL8m6jIF OESSJ0uNikLbQV2TwYdxXy3WyukGVkMRLSW1ES+zd2a47TDRiXMly+SyWjmNTxY9DeJ9 Q0er77ZRO/9bhJitSPnIQ79yYzVvM28z+ZZoY+WDJSYL3jHuW5ndvyE1ji/FFu91TEBF 08pG8Qw/EIz+Kei5+2ct251cxYoX/xW3cHDzbYmTc7YZElE8VsAmph5LSqMoLV2FK4dp RtBQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=NfDA+JwR; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-68369-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68369-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Fri, 16 Feb 2024 10:50:06 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CF84E237D79; Fri, 16 Feb 2024 10:49:22 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:49:22 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 06/12] irqchip/stm32-exti: Mark events reserved with RIF configuration check Date: Fri, 16 Feb 2024 10:47:51 +0100 Message-ID: <20240216094758.916722-7-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791048730761424463 X-GMAIL-MSGID: 1791048730761424463 EXTI events availability depends on Resource Isolation Framework (RIF) configuration. RIF grants access to buses with Compartment ID (CID) filtering, secure and privilege level. It also assigns EXTI events to one or several processors (CID, Secure, Privilege). EXTI events used by Linux must be CID-filtered (EnCIDCFGR.CFEN=1) and statically assigned to CID1 (EnCIDCFR.CID=CID1). EXTI events not filling these conditions are marked as reserved and can't be used by Linux. Signed-off-by: Antonio Borneo --- drivers/irqchip/irq-stm32-exti.c | 40 ++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index 85a40e07fbc3..68af5fe4764b 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -23,9 +23,22 @@ #include -#define IRQS_PER_BANK 32 +#define IRQS_PER_BANK 32 -#define HWSPNLCK_TIMEOUT 1000 /* usec */ +#define HWSPNLCK_TIMEOUT 1000 /* usec */ + +#define EXTI_EnCIDCFGR(n) (0x180 + (n) * 4) +#define EXTI_HWCFGR1 0x3f0 + +/* Register: EXTI_EnCIDCFGR(n) */ +#define EXTI_CIDCFGR_CFEN_MASK BIT(0) +#define EXTI_CIDCFGR_CID_MASK GENMASK(6, 4) +#define EXTI_CIDCFGR_CID_SHIFT 4 + +/* Register: EXTI_HWCFGR1 */ +#define EXTI_HWCFGR1_CIDWIDTH_MASK GENMASK(27, 24) + +#define EXTI_CID1 1 struct stm32_exti_bank { u32 imr_ofst; @@ -910,6 +923,27 @@ static const struct irq_domain_ops stm32_exti_h_domain_ops = { .xlate = irq_domain_xlate_twocell, }; +static void stm32_exti_check_rif(struct stm32_exti_host_data *host_data) +{ + u32 cid, cidcfgr, hwcfgr1; + unsigned int bank, i, event; + + /* quit on CID not supported */ + hwcfgr1 = readl_relaxed(host_data->base + EXTI_HWCFGR1); + if ((hwcfgr1 & EXTI_HWCFGR1_CIDWIDTH_MASK) == 0) + return; + + for (bank = 0; bank < host_data->drv_data->bank_nr; bank++) { + for (i = 0; i < IRQS_PER_BANK; i++) { + event = bank * IRQS_PER_BANK + i; + cidcfgr = readl_relaxed(host_data->base + EXTI_EnCIDCFGR(event)); + cid = (cidcfgr & EXTI_CIDCFGR_CID_MASK) >> EXTI_CIDCFGR_CID_SHIFT; + if ((cidcfgr & EXTI_CIDCFGR_CFEN_MASK) && cid != EXTI_CID1) + host_data->chips_data[bank].event_reserved |= BIT(i); + } + } +} + static void stm32_exti_remove_irq(void *data) { struct irq_domain *domain = data; @@ -972,6 +1006,8 @@ static int stm32_exti_probe(struct platform_device *pdev) for (i = 0; i < drv_data->bank_nr; i++) stm32_exti_chip_init(host_data, i, np); + stm32_exti_check_rif(host_data); + parent_domain = irq_find_host(of_irq_find_parent(np)); if (!parent_domain) { dev_err(dev, "GIC interrupt-parent not found\n"); From patchwork Fri Feb 16 09:47:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonio Borneo X-Patchwork-Id: 202040 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp406689dyb; Fri, 16 Feb 2024 01:59:15 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVh0AmbvF38UZSQqAf84ImYvVss3I1ZNOM5oXN0A/ATRaBm4XnkEEQYqmOQM3Pv+LhlGs4cpdvP03tOXn0+h9CEfRXuPA== X-Google-Smtp-Source: AGHT+IGrCK8Dxpq/fcwEHOJCSICb+plU13YMEccJjb8anKiaLdYYvsXOP2jtF14qJ4RMdj3QGHxH X-Received: by 2002:a05:6358:70c3:b0:175:fc6d:de7e with SMTP id h3-20020a05635870c300b00175fc6dde7emr4839799rwh.9.1708077555282; Fri, 16 Feb 2024 01:59:15 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708077555; cv=pass; d=google.com; s=arc-20160816; b=Qe/dWGKkgCfQffJAfPvPDphyHNfJQUIw+u8f9+ptY1GHA3rZPcdNg0lrOQjLpfl6Jx GwXBw8/smb3JKWpv9ouj6OhewW7cyUoAlXp5LS015zr0F3sXkNY2zYqsEDdSlQ+TpzJM jWw26JSHJCRIX7MF4+XmYzGWuMotWbql7NRkXqnleJaQPcbatHA+iqnMCI9mTe3FUZfK br6VuLKvdLG5Tkq67CYTwy+Odw/UEa56F4JQ9n/byADwC/h3p1xXrmrNqmyrRIy9jJqF tfoQ9LuBUixBwJ7bj5PkPt2eppXqtivILqyYMvCX2AHaUXGTyOT7En8TWdBMb7pjzYlF Exxw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=hd2MzwoxJbxM/jRYv2mZUqaeQPiVY5o6AngfSGI029A=; fh=xpn1PluZzGII3Xn6bg0JImd3eiUxde5K1Wn2dsUYIIA=; b=RIqGSAlUMBRORz5AHFjbIJH1EYixxDbOW/v0L4SA0q5JF4tM2B4y+quJo5JAY4UQ2r /ld/PFIuhmaUpvpVa2VaACEVdAsoVySiuVKPp0jJOJxq0/a/Jev/KZVVaOkToDOXBGW4 fA+PUIETR0bQvPuerF0Ru1bh8Mpfc0c8/iPSkbkisnzg8+50jm6tuPqPw6OQPdH61EVt JC2kQCgHPI1cheS5O0U6o6JGaL1Lo6qvjc9/Lf0XWlLjFnlwO2swyiM5VX0oJ3nRubsG xSNRSz45pKWCdFlHEEfgOKNGCxD7BLzwFD+Bdhfjdxxf3FrkJMQdD9jjzmrReMlDpd7v s4KA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=8NWxMo7e; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-68367-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68367-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Signed-off-by: Antonio Borneo --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 24335565bad5..19bf58a9d5e1 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -302,6 +302,7 @@ config ARCH_STM32 select GPIOLIB select PINCTRL select PINCTRL_STM32MP257 + select STM32_EXTI select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI From patchwork Fri Feb 16 09:47:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonio Borneo X-Patchwork-Id: 202028 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp404732dyb; Fri, 16 Feb 2024 01:53:16 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUBSbkwfTYeLkWbzLff9NHWHL+HelpOfyqcqmfelKtymTyHTFnso7VFcixEbRtte8pPlBoUIBejuqNynNs7ZSYYI/pnLQ== X-Google-Smtp-Source: AGHT+IEEOYyIJMHTfUud7JGNUwdy84cHnIoR8DyRwSZLXZvir4EWklrLux+2XjYXGlxJURGYxlWK X-Received: by 2002:a0c:e34d:0:b0:68f:30a1:4be6 with SMTP id a13-20020a0ce34d000000b0068f30a14be6mr2209532qvm.30.1708077196302; Fri, 16 Feb 2024 01:53:16 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708077196; cv=pass; d=google.com; s=arc-20160816; b=hxPSGE8JHbdlQEDT1L3DuFSdRSb01X1ajdJzjxjABKhIUp6n37pB2m/BsbpDrByLuo /s4Lh5FcVcH/+IZSUhHsQkWK+AiQ1NTZC2AwwQRNqdyK3fy25x4dfSUS7nEsDYRC2W42 ZoGEXODQkn6j9gtUbsFs1okAv5lYPmZucx0xSacNNtyE91tT1MCgigA3EHrjR58yvht8 Vt6SBYcnjGCjyqpmSj1q13lyxGxnc69Qc31kIINeHeBArQxxKgUfK8zSfbN2jlkwU4m6 YC30w+hJmgw9dBwIVyYiPcFc/vBW5xyBudRg01Hv7hEuVPAqj+I0q8DxYMbkN39GWNQy rKYQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+fxKXdkROzT3M+/iRky170lOst61Y8+W0nzGBLi971o=; fh=xpn1PluZzGII3Xn6bg0JImd3eiUxde5K1Wn2dsUYIIA=; b=c7zbtOXTW7ir4gTdV6b9b2njvB2RdlH24v9YyEfBgf+cVCH/cVZu46o8XlUlNFRT7y QNDP3kpZvvTrOuwIknwNPe3AFLgAW41kbusRIRk55U9bg46GahyR3m//fhzbu86SwV5h auJGlf3ZANeZ3oIjqaCaASHWkjkneO2jDoms4jcFmsKh+dsrwGFerpf0NUCbFnuJ9PhQ 3W4XIFJ+uflwA30hcVWKjZSFShpq1T76pXsF/OWvWH6p6a8Htjuh3ng0UcQJX7o+wzhQ V3paPAWehW1ibfgTkwyGraFA0gto4vjMc6xPSLk8RyMXxrxeeisCsM+dAJxpZFJBMBGf A8kg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=Appw7fH4; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-68371-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68371-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Fri, 16 Feb 2024 10:50:06 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 13158237D7B; Fri, 16 Feb 2024 10:49:24 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:49:23 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 08/12] ARM: dts: stm32: Use exti interrupt-map on stm32mp151 Date: Fri, 16 Feb 2024 10:47:53 +0100 Message-ID: <20240216094758.916722-9-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791048754661742237 X-GMAIL-MSGID: 1791048754661742237 Stop using the internal table of the exti driver and use the more flexible interrupt-map feature in DT. Convert the driver's table for stm32mp151 to the interrupt-map property in DT. Signed-off-by: Antonio Borneo --- arch/arm/boot/dts/st/stm32mp151.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index fa4cbd312e5a..33c460cacb04 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -1223,7 +1223,58 @@ exti: interrupt-controller@5000d000 { compatible = "st,stm32mp1-exti", "syscon"; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; reg = <0x5000d000 0x400>; + + exti-interrupt-map { + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-map-mask = <0xffffffff 0>; + interrupt-map = + <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <12 0 &intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <13 0 &intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <14 0 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <15 0 &intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <16 0 &intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <19 0 &intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <21 0 &intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <22 0 &intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <23 0 &intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <24 0 &intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <25 0 &intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <26 0 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <27 0 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <28 0 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <29 0 &intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <30 0 &intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <31 0 &intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <32 0 &intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <33 0 &intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <46 0 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <47 0 &intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <48 0 &intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <50 0 &intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <52 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <53 0 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <54 0 &intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <61 0 &intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <65 0 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <68 0 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <70 0 &intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <73 0 &intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 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Fri, 16 Feb 2024 10:50:06 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AAE11237D7C; Fri, 16 Feb 2024 10:49:24 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:49:24 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 09/12] ARM: dts: stm32: Use exti interrupt-map on stm32mp131 Date: Fri, 16 Feb 2024 10:47:54 +0100 Message-ID: <20240216094758.916722-10-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791048741098627647 X-GMAIL-MSGID: 1791048741098627647 Stop using the internal table of the exti driver and use the more flexible interrupt-map feature in DT. By switching away from using the internal table, there is no need anymore to use the specific compatible "st,stm32mp13-exti", which was introduced to select the proper internal table. Convert the driver table to interrupt-map property. Switch the compatible string to the generic "st,stm32mp1-exti", in place of the specific "st,stm32mp13-exti". Older DT using compatible "st,stm32mp13-exti" will still work as the driver remains backward compatible. Signed-off-by: Antonio Borneo --- arch/arm/boot/dts/st/stm32mp131.dtsi | 49 +++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index b04d24c939c3..14bd1c9bedd9 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -1093,10 +1093,57 @@ rcc: rcc@50000000 { }; exti: interrupt-controller@5000d000 { - compatible = "st,stm32mp13-exti", "syscon"; + compatible = "st,stm32mp1-exti", "syscon"; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; reg = <0x5000d000 0x400>; + + exti-interrupt-map { + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-map-mask = <0xffffffff 0>; + interrupt-map = + <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <12 0 &intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <13 0 &intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <14 0 &intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <15 0 &intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <16 0 &intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <19 0 &intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <21 0 &intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <22 0 &intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <23 0 &intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <24 0 &intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <25 0 &intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <26 0 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <27 0 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <28 0 &intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <29 0 &intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <30 0 &intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <31 0 &intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <32 0 &intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <33 0 &intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <44 0 &intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <47 0 &intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <48 0 &intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <50 0 &intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <52 0 &intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <53 0 &intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <68 0 &intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <70 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 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Fri, 16 Feb 2024 10:51:08 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7A35522D187; Fri, 16 Feb 2024 10:50:27 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:50:27 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , , Christian Bruel Subject: [PATCH 10/12] arm64: dts: st: Add v2m to GIC node on stm32mp251 Date: Fri, 16 Feb 2024 10:47:55 +0100 Message-ID: <20240216094758.916722-11-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791048865455048220 X-GMAIL-MSGID: 1791048865455048220 From: Christian Bruel The GIC of STM32MP25 includes v2m extension for PCIEe MSI support. Add the v2m sub-node to the GIC interrupt controller and adapt the other properties accordingly. Signed-off-by: Christian Bruel Signed-off-by: Antonio Borneo --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 96859d098ef8..5c9095382cc7 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -81,12 +81,20 @@ scmi_reset: protocol@16 { intc: interrupt-controller@4ac00000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; - #address-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; interrupt-controller; reg = <0x0 0x4ac10000 0x0 0x1000>, <0x0 0x4ac20000 0x0 0x2000>, <0x0 0x4ac40000 0x0 0x2000>, <0x0 0x4ac60000 0x0 0x2000>; + ranges; + + v2m0: v2m@48090000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x0 0x48090000 0x0 0x1000>; + msi-controller; + }; }; psci { From patchwork Fri Feb 16 09:47:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonio Borneo X-Patchwork-Id: 202046 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp408437dyb; Fri, 16 Feb 2024 02:02:23 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU4qSgIjmCT0Uti3DRORkFp/KQfbQ8J1sDt+X5vCAjxtstf6jy6bzH0/49wU2Bg7g0HFLk/T89hVCboZFiDsR8/RXtZjw== X-Google-Smtp-Source: AGHT+IFobdTjVjPiEiZNIw6Clgx3OshwaK58rWNNMymsqeYdEdB99oSPEnHUckROoh9ybmjpZBhH X-Received: by 2002:a17:90a:8c07:b0:299:3720:3ddb with SMTP id a7-20020a17090a8c0700b0029937203ddbmr624719pjo.48.1708077743424; Fri, 16 Feb 2024 02:02:23 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708077743; cv=pass; d=google.com; s=arc-20160816; b=Lgch6Ngxnw/CQUg8EqQTp6QnjHETwkOplskZYayoq8L7+z0RziLD1PUbzTeB+6fOwQ kGrUcRglt2HfEQaMBlJSonPRnDwI/blMXQ78LxF88JYHj4nd1O+XklcWeoTMPD8en9ja RF4C5OoHh/7A+FdexWXUUaLbl6CMtqry24DUH6svEO17FdRrH+sXGg19ysKWR1I752nA drweNf7X8ygltJwZBbA1AvpeQ/Qn5gIMU5JGWCetojKeeWyzKUbhFTha4TiNgIkYv5Oi lOKCxvQI2NSaJJaJNanP9SSu/ZY1Rac2uq32ZFmf+0c4qpQKavdGaOJhVGxpZVqSIBBi Yzzw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=71REGfTc7yoIJymQ9MkGvQ6YZAyCUgLqFHdkGlwLvK4=; fh=xpn1PluZzGII3Xn6bg0JImd3eiUxde5K1Wn2dsUYIIA=; b=QeHKsLggSlVnSnBJ30GH+FTIDGelkPhwGabB6UGv7BZCRnwDdapTEVrVpTVlWmATgl g+9DqL7vbrvNREn1JZR7rLBDecp5c3+FQYHfuvfb0V4FMLVEcmfxa5bqZPzDYNYEvaPy aUCTMZc5pGOQ2W/kD8DFeKFEKSRfQasxe1okRJ2p7YWTei/iCrK+LYcg9o6kpvyaE8ki 6J5MOGJ4Hl5NozfgHakoiWXSCq1gcimJAJuonDjGV8agA5UtHEJecmufZZAFjwWWoOEM DTkA1PgmJFLmq1TA3/AOJeBixOHcOMsvnZ1dAzSzKn5JKG1uNoqNJuSumhn8DNC8G//R o4Eg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=vxMg1fQI; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-68375-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68375-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Fri, 16 Feb 2024 10:51:10 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4952022FA36; Fri, 16 Feb 2024 10:50:28 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:50:27 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 11/12] arm64: dts: st: Add exti1 and exti2 nodes on stm32mp251 Date: Fri, 16 Feb 2024 10:47:56 +0100 Message-ID: <20240216094758.916722-12-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791049327904596166 X-GMAIL-MSGID: 1791049327904596166 Update the device-tree stm32mp251.dtsi by adding the nodes for exti1 and exti2 interrupt controllers. Signed-off-by: Antonio Borneo --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 140 +++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5c9095382cc7..4253f5bcd000 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -164,6 +164,86 @@ package_otp@1e8 { }; }; + exti1: interrupt-controller@44220000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + reg = <0x44220000 0x400>; + + exti-interrupt-map { + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-map-mask = <0xffffffff 0>; + interrupt-map = + <0 0 &intc 0 0 GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &intc 0 0 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &intc 0 0 GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc 0 0 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &intc 0 0 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &intc 0 0 GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &intc 0 0 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &intc 0 0 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &intc 0 0 GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &intc 0 0 GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &intc 0 0 GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &intc 0 0 GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <12 0 &intc 0 0 GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <13 0 &intc 0 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <14 0 &intc 0 0 GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <15 0 &intc 0 0 GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <16 0 &intc 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <17 0 &intc 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <18 0 &intc 0 0 GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <19 0 &intc 0 0 GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <21 0 &intc 0 0 GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <22 0 &intc 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <23 0 &intc 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <24 0 &intc 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <25 0 &intc 0 0 GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <26 0 &intc 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <27 0 &intc 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <28 0 &intc 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <29 0 &intc 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <30 0 &intc 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <31 0 &intc 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <32 0 &intc 0 0 GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <33 0 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <34 0 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <36 0 &intc 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <37 0 &intc 0 0 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <38 0 &intc 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <39 0 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <40 0 &intc 0 0 GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <41 0 &intc 0 0 GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <42 0 &intc 0 0 GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <43 0 &intc 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <44 0 &intc 0 0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <45 0 &intc 0 0 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <46 0 &intc 0 0 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <47 0 &intc 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <48 0 &intc 0 0 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <49 0 &intc 0 0 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <50 0 &intc 0 0 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <59 0 &intc 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <61 0 &intc 0 0 GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <64 0 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <67 0 &intc 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <68 0 &intc 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <70 0 &intc 0 0 GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <72 0 &intc 0 0 GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <73 0 &intc 0 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <74 0 &intc 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <75 0 &intc 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <76 0 &intc 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <77 0 &intc 0 0 GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <78 0 &intc 0 0 GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <79 0 &intc 0 0 GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <83 0 &intc 0 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <84 0 &intc 0 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + syscfg: syscon@44230000 { compatible = "st,stm32mp25-syscfg", "syscon"; reg = <0x44230000 0x10000>; @@ -318,5 +398,65 @@ gpioz: gpio@46200000 { }; }; + + exti2: interrupt-controller@46230000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + reg = <0x46230000 0x400>; + + exti-interrupt-map { + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-map-mask = <0xffffffff 0>; + interrupt-map = + <0 0 &intc 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &intc 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &intc 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &intc 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &intc 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &intc 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &intc 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &intc 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &intc 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &intc 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &intc 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <12 0 &intc 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <13 0 &intc 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <14 0 &intc 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <15 0 &intc 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <16 0 &intc 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <17 0 &intc 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <21 0 &intc 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <22 0 &intc 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <25 0 &intc 0 0 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <26 0 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <27 0 &intc 0 0 GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <29 0 &intc 0 0 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <30 0 &intc 0 0 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <31 0 &intc 0 0 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <33 0 &intc 0 0 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <34 0 &intc 0 0 GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <37 0 &intc 0 0 GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <40 0 &intc 0 0 GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <43 0 &intc 0 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <46 0 &intc 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <48 0 &intc 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <49 0 &intc 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <50 0 &intc 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <51 0 &intc 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <52 0 &intc 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <53 0 &intc 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <61 0 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <62 0 &intc 0 0 GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <64 0 &intc 0 0 GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <65 0 &intc 0 0 GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <66 0 &intc 0 0 GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <67 0 &intc 0 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <70 0 &intc 0 0 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 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Fri, 16 Feb 2024 10:51:11 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D7112229A92; Fri, 16 Feb 2024 10:50:28 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:50:28 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 12/12] arm64: dts: st: Add interrupt parent to pinctrl on stm32mp251 Date: Fri, 16 Feb 2024 10:47:57 +0100 Message-ID: <20240216094758.916722-13-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791048814396732228 X-GMAIL-MSGID: 1791048814396732228 Add exti1 as interrupt parent for the two pin controllers. Add the additional required property st,syscfg. Signed-off-by: Antonio Borneo --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 4253f5bcd000..6d46450afd4d 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -254,6 +254,8 @@ pinctrl: pinctrl@44240000 { #size-cells = <1>; compatible = "st,stm32mp257-pinctrl"; ranges = <0 0x44240000 0xa0400>; + interrupt-parent = <&exti1>; + st,syscfg = <&exti1 0x60 0xff>; pins-are-numbered; gpioa: gpio@44240000 { @@ -383,6 +385,8 @@ pinctrl_z: pinctrl@46200000 { #size-cells = <1>; compatible = "st,stm32mp257-z-pinctrl"; ranges = <0 0x46200000 0x400>; + interrupt-parent = <&exti1>; + st,syscfg = <&exti1 0x60 0xff>; pins-are-numbered; gpioz: gpio@46200000 {