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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:05:59 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 01/12] spi: dt-bindings: introduce FIFO depth properties Date: Fri, 16 Feb 2024 07:05:44 +0000 Message-ID: <20240216070555.2483977-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038300861758593 X-GMAIL-MSGID: 1791038300861758593 There are SPI IPs that can be configured by the integrator with a specific FIFO depth depending on the system's capabilities. For example, the samsung USI SPI IP can be configured by the integrator with a TX/RX FIFO from 8 byte to 256 bytes. Introduce the ``fifo-depth`` property for such instances of IPs where the same FIFO depth is used for both RX and TX. Introduce ``rx-fifo-depth`` and ``tx-fifo-depth`` properties for cases where the RX FIFO depth is different from the TX FIFO depth. Make the dedicated RX/TX properties dependent on each other and mutual exclusive with the other. Reviewed-by: Rob Herring Signed-off-by: Tudor Ambarus Reviewed-by: Conor Dooley --- .../bindings/spi/spi-controller.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml index 524f6fe8c27b..093150c0cb87 100644 --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml @@ -69,6 +69,21 @@ properties: Should be generally avoided and be replaced by spi-cs-high + ACTIVE_HIGH. + fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the RX and TX data FIFOs in bytes. + + rx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the RX data FIFO in bytes. + + tx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the TX data FIFO in bytes. + num-cs: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -116,6 +131,10 @@ patternProperties: - compatible - reg +dependencies: + rx-fifo-depth: [ tx-fifo-depth ] + tx-fifo-depth: [ rx-fifo-depth ] + allOf: - if: not: @@ -129,6 +148,14 @@ allOf: properties: "#address-cells": const: 0 + - not: + required: + - fifo-depth + - rx-fifo-depth + - not: + required: + - fifo-depth + - tx-fifo-depth additionalProperties: true From patchwork Fri Feb 16 07:05:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 201965 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp342984dyb; Thu, 15 Feb 2024 23:07:00 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUja+3V0eYuG7fpxbVAkvsY+JSin6iK+fWWYGnuoouDhxsTo4LeBlzfOn7q+hbwqtB393CWz5ExnXKZRw5N5COv5fETyw== X-Google-Smtp-Source: AGHT+IE7MezdFzmECkjK2xrU5Wz5n3/bE//pF5k0OdL8039farA3FQ00Ttn9FAeV4i98dYsk02EK X-Received: by 2002:a05:622a:154:b0:42d:b714:5607 with SMTP id v20-20020a05622a015400b0042db7145607mr5699883qtw.29.1708067220670; Thu, 15 Feb 2024 23:07:00 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708067220; cv=pass; d=google.com; s=arc-20160816; b=ZHB6RNdmTdkcW/7IIu5vMWVC2oCnrDyCy+7XYQX4dVQMwh+T6LVJTR6qpCq/nl51JS YprDRef1n2Z/7rpphwZG3YQcBt9uBbFAPxPV1eWzPYnQTo1eIhKCtXt/c1KbhSzrCQRN hVnts+Sb69exhT297FLX4DGtpfUu44wMt3xIkUmJCXBOYgjXCkhSMSdX4+2x/cmv2325 TSX7kYR0tARjMEuvHkCqnsONVLDrp7ry9kf9Y4qmSaCvI2UJgr2f8f2hUmDTsUgdmAlB m2riEMqFv+w4SZOo5f1MpMnBHOhv9wicqPQhIDKQpt7897neCHiMvQTx3DONEAWwDmJu fKdQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=B4fweEbO97J5QIjA941SE8yy8/h6DEGER6dvQE2i+PI=; fh=o2loVCl4KxSUI66a/kqdUjVOUPmGp3ze5FEq8QA7Ivs=; b=jdyJjpA2Duir8eyP+OWviIoNDE47n4xXsMLrVobEmgSvLAOjEeemQgBUSZCJRGlIHM OdwY2o2DtkxWINlo5SqZAC92Q0GFdwd9W87KvCRf6uoPDvCc5EQqNRolg/fQ8pqKMyTQ uTvuwXyjIwqIMZxJtbiNjZg5fkP0/nMM2SmppIGX/WguWvUAMjWXIiWpbw4sk/gb/8RS Yd4MuX8AbNviOx1rnHwqqEmi54C2CRwSlpOOChRKI+In7cG0BEkwfRYWhzBcqGvQD93a 2/t0XQK1g9J4NWQ49diSNfkWYn66ZJhP4FQ0lM8qy5L7JEF+J2wqZXC6hHs5kmOcQgCX PIzA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zKJejbt3; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68143-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68143-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:00 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 02/12] spi: s3c64xx: define a magic value Date: Fri, 16 Feb 2024 07:05:45 +0000 Message-ID: <20240216070555.2483977-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038294056659598 X-GMAIL-MSGID: 1791038294056659598 Define a magic value, it will be used in the next patch as well. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 6f29dca68491..6ff3b25b6feb 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -78,6 +78,7 @@ #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) +#define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) @@ -108,7 +109,8 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) +#define TX_FIFO_LVL(v, i) (((v) >> S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT) & \ + FIFO_LVL_MASK(i)) #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ FIFO_LVL_MASK(i)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) From patchwork Fri Feb 16 07:05:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 201967 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp343131dyb; Thu, 15 Feb 2024 23:07:22 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUvl98l0R3RYJRS5f8f6M10XVxNRxIFV6AemBDWUd8/6sgAxuH5eW5nKO0ypNfN/wgZFddDbquO2iRSdL7IJ3pqzfu3RQ== X-Google-Smtp-Source: AGHT+IEgjuIgfo6x3rUP8PWtVhs6eys2cQoMz6YIS0/QjHR/BEAc4irVdrDkmfU9jVlRPRSqSH+7 X-Received: by 2002:a05:6870:65a5:b0:219:88b7:f9cb with SMTP id fp37-20020a05687065a500b0021988b7f9cbmr4891055oab.28.1708067242255; Thu, 15 Feb 2024 23:07:22 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708067242; cv=pass; d=google.com; s=arc-20160816; b=dwiItv6edmt/R9NZjBHZbwcSUvFTaXmUpyv7+NTtpGVcuEOlGPRUinGUAVzU8GpRuX 39TOlDTy5BQz9stsUOHPCOmLdXZpKz0BtcligwTkynpvHTckUYsYBcTxifPbf9N4uTpg eAhhchx6UmMPhyg1FJA4Ue+4nhFOhVYhOPRTcyK/UdjfG1XkX1YPOX0xV0qpGDM/oDnA 68X9o1zGSMc6xuzFSUe2UnIfwreR1Yr6VDnJBo57NLg2UP23a3NSJkbLODs8MzLTZbyf NdkJG/0q7TYzSRJmfCauIukYML+tRw6lZixYZjSFgnb/r4v7CNN/5coRKtsKNhW+44GV 2Kqg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=p90PTqn06M2OMVgm04TULcXmimQydfdnY35+RdZcOWs=; fh=kf4oW9pjS3L4uweLcOrC0oPP5FmIHtlKjgbRp6Q2IfQ=; b=Hs8oJ05qLUt/XHa7N1sF6AowrIJAT4WeQuKmTarEniDBqIQsJRQSfLT/03k32um0Yg +MqeSqJ1v7gog3H/5BNP0Qy1NdQuYouBUTt5B//j/ef2o7gehncdIYo2UVoG1PEngMV6 Svgdg7mOM0+a8YXBZobO8/Buqm061rV353b48kmyOpW34vmLpiQLano9E71ylPKAchP2 H9wfHUCi5R4HO3pZ1p5IacB94FFYPjGcI8gDfD3buaz7+pnd7J/p5R00B9oiOJ3uCtxo 0G2hjtpevY0NznlVpQ9CkhSeP+lu5+zkZwNW6ougLImitEwadov1btxUICDQ3Rk5IHwb WsSA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jyheOQWB; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68144-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68144-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:01 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 03/12] spi: s3c64xx: allow full FIFO masks Date: Fri, 16 Feb 2024 07:05:46 +0000 Message-ID: <20240216070555.2483977-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038316431285819 X-GMAIL-MSGID: 1791038316431285819 The driver is wrong because is using partial register field masks for the SPI_STATUS.{RX, TX}_FIFO_LVL register fields. We see s3c64xx_spi_port_config.fifo_lvl_mask with different values for different instances of the same IP. Take s5pv210_spi_port_config for example, it defines: .fifo_lvl_mask = { 0x1ff, 0x7F }, fifo_lvl_mask is used to determine the FIFO depth of the instance of the IP. In this case, the integrator uses a 256 bytes FIFO for the first SPI instance of the IP, and a 64 bytes FIFO for the second instance. While the first mask reflects the SPI_STATUS.{RX, TX}_FIFO_LVL register fields, the second one is two bits short. Using partial field masks is misleading and can hide problems of the driver's logic. Allow platforms to specify the full FIFO mask, regardless of the FIFO depth. Introduce {rx, tx}_fifomask to represent the SPI_STATUS.{RX, TX}_FIFO_LVL register fields. It's a shifted mask defining the field's length and position. We'll be able to deprecate the use of @rx_lvl_offset, as the shift value can be determined from the mask. The existing compatibles shall start using {rx, tx}_fifomask so that they use the full field mask and to avoid shifting the mask to position, and then shifting it back to zero in the {TX, RX}_FIFO_LVL macros. @rx_lvl_offset will be deprecated in a further patch, after we have the infrastructure to deprecate @fifo_lvl_mask as well. No functional change intended. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 40 +++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 6ff3b25b6feb..338ca3f03ea5 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -3,6 +3,7 @@ // Copyright (c) 2009 Samsung Electronics Co., Ltd. // Jaswinder Singh +#include #include #include #include @@ -109,10 +110,10 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT) & \ - FIFO_LVL_MASK(i)) -#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ - FIFO_LVL_MASK(i)) +#define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \ + __ffs((sdd)->tx_fifomask)) +#define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \ + __ffs((sdd)->rx_fifomask)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff @@ -136,6 +137,10 @@ struct s3c64xx_spi_dma_data { * struct s3c64xx_spi_port_config - SPI Controller hardware info * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. + * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. * @clk_div: Internal clock divider * @quirks: Bitmask of known quirks @@ -154,6 +159,8 @@ struct s3c64xx_spi_dma_data { struct s3c64xx_spi_port_config { int fifo_lvl_mask[MAX_SPI_PORTS]; int rx_lvl_offset; + u32 rx_fifomask; + u32 tx_fifomask; int tx_st_done; int quirks; int clk_div; @@ -184,6 +191,10 @@ struct s3c64xx_spi_port_config { * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data * @port_id: Port identification number + * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. + * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. */ struct s3c64xx_spi_driver_data { void __iomem *regs; @@ -203,6 +214,8 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; + u32 rx_fifomask; + u32 tx_fifomask; }; static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) @@ -1183,6 +1196,23 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; } +static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) +{ + const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; + + if (port_conf->rx_fifomask) + sdd->rx_fifomask = port_conf->rx_fifomask; + else + sdd->rx_fifomask = FIFO_LVL_MASK(sdd) << + port_conf->rx_lvl_offset; + + if (port_conf->tx_fifomask) + sdd->tx_fifomask = port_conf->tx_fifomask; + else + sdd->tx_fifomask = FIFO_LVL_MASK(sdd) << + S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT; +} + static int s3c64xx_spi_probe(struct platform_device *pdev) { struct resource *mem_res; @@ -1231,6 +1261,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } + s3c64xx_spi_set_fifomask(sdd); + sdd->cur_bpw = 8; sdd->tx_dma.direction = DMA_MEM_TO_DEV; From patchwork Fri Feb 16 07:05:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 201968 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp343198dyb; Thu, 15 Feb 2024 23:07:31 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUGbRNo7q3VHih8XfYPrrrwobv+DZ4OxXHmgjZbQmhAEms4inoRktqVgtsUF4iGiY7yz/FM5hjD403Ylww582w3U1bhwg== X-Google-Smtp-Source: AGHT+IF1tGfASt9oEO3LsjVFrsz0k24hX/Igw2TvWoc9uq2ffSwxsSpb/vbER0+5RVeJXeindRMv X-Received: by 2002:a17:906:1d53:b0:a3c:8299:9c5f with SMTP id o19-20020a1709061d5300b00a3c82999c5fmr2566216ejh.75.1708067250950; Thu, 15 Feb 2024 23:07:30 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708067250; cv=pass; d=google.com; s=arc-20160816; b=DdG6c6QBCKRPoDTgc7/UXXwHITOPac+PscvmyTiLfll1QcLBb+alihN2a1kawbmUXm QuV2VMdxr6nUlK5BBMdGEi6Hf9W16ncji4al+ztHCc+nQP0ThX+ic4USuV3XEcMHncB1 bLs7KhygphZSpqc21mnFJN6Iwg1SIqDbdAP8/MQwxElg2ABXXEjs864PFvhiHVZvcoCW A3NmwiRkipk2dyUcbGRZRXuI7jJOWt8Kp3qr4+tuigK+rQyTaRaHPG/ZrUYGXK+cQvtZ 8iLBhVGtMmO1pt19mmsxYaYmd530VruGlb1zOhcdyiquzVUzSYUdRasYZTK5rB9EiJnE RxuA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=i5dQGEaVcg4JepfFOKvtsOuZxWCp+j5PzKY/bMFyTSc=; fh=6+2g2pwV+J/B57TQaXXbwA1FzAYzA0n/QEirTMcm4kQ=; b=VrK1Usm6D62rNx+/3YElL/x3Sp+AMUZGbXG08BVIg0K0+IPtCD3NHsPbCYkLaODgae CV4Frq1cayNyO3KMgNokAQOWUnPTZWDTSFhCz+VJmwuP7ODHFoos04hNTxd2mhBw5HHc LhMlbn1VaG7qIHqJ0av4Lm4NM08qJCjNBwT+LnL+mwNbJV3iIQB8UC4t/mua7XgUup4J FvzOj/W96j/DbcDqZxfX7oy28CWNGT8VoxgZmcvYB5KAmf8CMnLA3t/7242ztdVk7X+I V2u0gwNutZ6ddyHFOvSzJZA4t547qlSThEVHSjkktR6bCuJamX6rMil9sPubVlKW0ypn L8ww==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="YdX/MzSG"; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68145-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68145-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:02 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 04/12] spi: s3c64xx: determine the fifo depth only once Date: Fri, 16 Feb 2024 07:05:47 +0000 Message-ID: <20240216070555.2483977-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038325552031809 X-GMAIL-MSGID: 1791038325552031809 Determine the FIFO depth only once, at probe time. ``sdd->fifo_depth`` can be set later on with the FIFO depth specified in the device tree. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 338ca3f03ea5..72572e23cde5 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -191,6 +191,7 @@ struct s3c64xx_spi_port_config { * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data * @port_id: Port identification number + * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's @@ -214,6 +215,7 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; + unsigned int fifo_depth; u32 rx_fifomask; u32 tx_fifomask; }; @@ -424,7 +426,7 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host, struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); if (sdd->rx_dma.ch && sdd->tx_dma.ch) - return xfer->len > FIFO_DEPTH(sdd); + return xfer->len > sdd->fifo_depth; return false; } @@ -548,7 +550,7 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, void __iomem *regs = sdd->regs; unsigned long val = 1; u32 status; - u32 max_fifo = FIFO_DEPTH(sdd); + u32 max_fifo = sdd->fifo_depth; if (timeout_ms) val = msecs_to_loops(timeout_ms); @@ -655,7 +657,7 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, * For any size less than the fifo size the below code is * executed atleast once. */ - loops = xfer->len / FIFO_DEPTH(sdd); + loops = xfer->len / sdd->fifo_depth; buf = xfer->rx_buf; do { /* wait for data to be received in the fifo */ @@ -792,7 +794,7 @@ static int s3c64xx_spi_transfer_one(struct spi_controller *host, struct spi_transfer *xfer) { struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); - const unsigned int fifo_len = FIFO_DEPTH(sdd); + const unsigned int fifo_len = sdd->fifo_depth; const void *tx_buf = NULL; void *rx_buf = NULL; int target_len = 0, origin_len = 0; @@ -1261,6 +1263,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } + sdd->fifo_depth = FIFO_DEPTH(sdd); + s3c64xx_spi_set_fifomask(sdd); sdd->cur_bpw = 8; @@ -1352,7 +1356,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n", sdd->port_id, host->num_chipselect); dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", - mem_res, FIFO_DEPTH(sdd)); + mem_res, sdd->fifo_depth); pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); From patchwork Fri Feb 16 07:05:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 201969 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp343259dyb; Thu, 15 Feb 2024 23:07:41 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUsJxci7CDJuPfEtD0NOVP6QJthAY6E9gtd4A3MZHUyVTuU3xQcUuzrN6V1x+XzGwldB1i2R+X4w2LQAGShpF6uVhHCVQ== X-Google-Smtp-Source: AGHT+IEb8u2IFUWQ3PBDJR6rfalbhIwEaXt7LK8h7NTVnP0l6tjeBHIJEkGwl8PDxcHWn6Oh8XWt X-Received: by 2002:a05:6402:165a:b0:561:f7da:ee30 with SMTP id s26-20020a056402165a00b00561f7daee30mr2373084edx.42.1708067261535; Thu, 15 Feb 2024 23:07:41 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708067261; cv=pass; d=google.com; s=arc-20160816; b=0Ciex94spsoKhQRy/gAUx3kAuLZ3St8Eml4X4NR+GwCkOkuEK5YVS1V3OEUJRTU25/ DQVTlEMQmv6F0xObIO2Q4dbz+xvUuDzsdiAqDySW2NK6LOlFb4r17e+F2q0Wb9BQLKO/ xTbvx+/pYfma/u/3e3Z0ibyNPv4ZK80ZDZh+UPAQEqB/T+UWolrBiWyfLSbJO7afTXwb cLrntGasz6S63yzo9HH8svshZHjuZ6LNWn6OWbyRKaUC5RHKKboiYT88DrFrw+A0l4Mh h/WBhjtLd52QG0KsCqITk+m2MU3bhwvL36qmixq+THgYTRd4e2gCFthym8cyAn4gCfzD +QFg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=hs676vE1oPrjFgO93552CvPBZ3kPEUhKELlxqPQ87Xc=; fh=oLAz6oHAlburzxXxe0hrXDcZGB3gEV3XK8IK70tX3BY=; b=JP2h5e0QlQL+GwILmWYrAD5/YjoRAQrg7VSmliPth7S6Ge8AYX9+m2Iuv3dFSzetWX M0OHZJJSHPnr1iTBu1RmbCRS/cFENuIpoCxudhOtRUPrSbsOi+TrLxn02xVkiAm777Oi Xab8rUnuGRxXpDubRABPndvAqKn6aEdaIoahIlh+cw0B3+anKdYYc7Gc+navliJTTj8+ S4I6eFnwSllNhqQzFAuQFclpC+cGaI5/FC1gI7wyUXbImDahpBlhwEs4WnxR2fWhdMwf rTawpr+seLQvgi9DZcxlf01qwGuaSIrKjfI5UTqtOMgfC/jJtCOwTv9uOsDei1+y4a4C dsLA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hhhqgbgK; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68146-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68146-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:04 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 05/12] spi: s3c64xx: retrieve the FIFO depth from the device tree Date: Fri, 16 Feb 2024 07:05:48 +0000 Message-ID: <20240216070555.2483977-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038336786670035 X-GMAIL-MSGID: 1791038336786670035 There are SoCs that configure different FIFO depths for their instances of the SPI IP. See the fifo_lvl_mask defined for exynos4_spi_port_config for example: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, The first instance of the IP is configured with 256 bytes FIFOs, whereas the last two are configured with 64 bytes FIFOs. Instead of mangling with the .fifo_lvl_mask and its dependency of the DT alias ID, allow such SoCs to determine the FIFO depth via the ``fifo-depth`` DT property. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 72572e23cde5..b1c63f75021d 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1263,7 +1263,9 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } - sdd->fifo_depth = FIFO_DEPTH(sdd); + if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", + &sdd->fifo_depth)) + sdd->fifo_depth = FIFO_DEPTH(sdd); s3c64xx_spi_set_fifomask(sdd); From patchwork Fri Feb 16 07:05:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 201971 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp343537dyb; Thu, 15 Feb 2024 23:08:24 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUc/0QlCb0CzatQB3wdj5gaKD1iR8FPrNNn/E/4DpSCLhX4QR719A/dIkSzizMA5n32xDsHoK0YBJUOhrDvgomJQc4uKg== X-Google-Smtp-Source: AGHT+IH2C3NKvjpB7Em2VH893FJoErNnmaCB05pFfUwUGuSm+2cnc4cTJgcy0Ui4Z8dcYm0QR8Sp X-Received: by 2002:a05:620a:38a:b0:787:1fa4:98e5 with SMTP id q10-20020a05620a038a00b007871fa498e5mr4931092qkm.32.1708067304603; Thu, 15 Feb 2024 23:08:24 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708067304; cv=pass; d=google.com; s=arc-20160816; b=BTdjVTGLwBf7v/xYc7YcRet/5X8koP3+syKnu1diYvZdsjup7TTTjAQhfqX/mihtER xRm8CMxF4EQNnlgwpHuLASftmPntTRyHPfnWj5CRSukOmxVzJA3iAoQc0favL/KddDZw hjDc4iv6YOlazT61tCUk5MKv4yf3nwOkQXOIxbPOVCh79ozTD32nu6FAqQARm/3aMuX6 hIME6OFwBnLcXCE/6pztAnC508IgvcZ1mgRSok8Y8Kfev+5MwAKyEtHwuG+tkrH/PGri A0aFEfhuFZQ8J+Q3SLepMc4mq3icWaGHTXlOIPmwnfhxnd90XcetqeiTmfzx7TAMd82g s0NA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=hp4R5FqMMv454plXIhV7qJWhdTsbC/ksc+0K6w+UCm0=; fh=Ma21SGjngTjR8lwrD7uToZRcDOGKWObfYfpIikgIWIU=; b=Xfk/3/UksRQtm/nM6uUIkSjHrU2j6/lok5m/Q79OdJfB29FeQVFBQU2RKxIKT28cLu W71buxD8jPMZxjhpx6vg08wntJEn5NJGskVZ+HE6dJV8YOKw0wgjvhJ2vYVmKPzeLrmv pETMwFltxC+ChCv8mb9ygx1qSfsnP2S+NQnv5hq32rZX65wO/Rs3IQRYROFwUqP1mLx9 0ChHHnXpDEnsHoQ2YZYuGDDNbKBKFJrFkCGMa1wqxXiDz1sz3GX8Kt58XOojOG1NcpJH qDslHVx1BjMLM3w1rzHFZkUsPLEIN/044IyijGDvNKW7LvQxNnVY8ygostv+FxdGXeJJ gw0w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i2iFqbvO; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68148-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68148-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:05 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 06/12] spi: s3c64xx: allow FIFO depth to be determined from the compatible Date: Fri, 16 Feb 2024 07:05:49 +0000 Message-ID: <20240216070555.2483977-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038382293662217 X-GMAIL-MSGID: 1791038382293662217 There are SoCs that use the same FIFO depth for all the instances of the SPI IP. See the fifo_lvl_mask defined for gs101 for example: .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, Instead of specifying the FIFO depth with the same value for all 16 nodes in this case, allow such SoCs to infer the FIFO depth from the compatible. There are other SoCs than can benefit of this, see: {gs101, fsd, exynos850, s3c641, s3c2443}_spi_port_config. The FIFO depth inferred from the compatible has a higher precedence than the one that might be specified via device tree, the driver shall know better. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index b1c63f75021d..68f95c04d092 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -137,6 +137,7 @@ struct s3c64xx_spi_dma_data { * struct s3c64xx_spi_port_config - SPI Controller hardware info * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's @@ -159,6 +160,7 @@ struct s3c64xx_spi_dma_data { struct s3c64xx_spi_port_config { int fifo_lvl_mask[MAX_SPI_PORTS]; int rx_lvl_offset; + unsigned int fifo_depth; u32 rx_fifomask; u32 tx_fifomask; int tx_st_done; @@ -1263,8 +1265,10 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } - if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", - &sdd->fifo_depth)) + if (sdd->port_conf->fifo_depth) + sdd->fifo_depth = sdd->port_conf->fifo_depth; + else if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", + &sdd->fifo_depth)) sdd->fifo_depth = FIFO_DEPTH(sdd); s3c64xx_spi_set_fifomask(sdd); From patchwork Fri Feb 16 07:05:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 201970 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp343510dyb; Thu, 15 Feb 2024 23:08:20 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXHmKsJk10q3Dx1ngyM7L4nRciad+IN24BLJ6iXqpn7gsP9qZnFGwjBbtwNFafKWxOSQfULHW7Qrd1y9QLM/VmVZ6dUvA== X-Google-Smtp-Source: AGHT+IHNSnAPyf+DZM2pYal9/Rqg1iow3f6dXpEr4RExpR6CeSxc1RFR+Uc5UTcm1hWbdwlYK6nQ X-Received: by 2002:a05:6808:643:b0:3c0:2bce:7109 with SMTP id z3-20020a056808064300b003c02bce7109mr3883008oih.30.1708067300521; Thu, 15 Feb 2024 23:08:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708067300; cv=pass; d=google.com; s=arc-20160816; b=rN9QJdimWcCYTFFa6oCnrLGDxpP8avAeH/3vFWrksfV44YkBmIDGSYnyBY6a7iqJOw yx9YIv0S6Zft+NgcNLWp58Pe3dTuLLUCTH4AWbbr6FfxrHXBaRdl0FBi3w2RLbBarBN4 J+NRG+7xHez+Pk3g8nVuSgUszyDhDCS83zU0IUy5JfSGMq6egS2UejJyAvGyI3o/yQZG BcWc9A+eyHff4UMa/oJNnsL8nV9hW3Kgkw8UWR19AsHPazZ76xxBz/veaNX0dd/2jZW0 Kz3cR6vEHtYREsyJjTiaNnyV7TOZpQq2gXgicIFSYxRZHBmu/oLYFMG3UslxcZF8EJmX TvmQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=5Le6XNl1MSpW8ND9xafZ+XDYHu2w9i8pp90k+8toYjg=; fh=7URjCeRw5TwAj8cywN1WnO535KOaKyXB77Xv8yQstdc=; b=yb9nVdTbqTkrNoE3uVTRaz05De7t2f593uJGgIs4ioybanXQuQJHsGa7hSr/6t1kIp QpWcyrNoU0DqkOFrtO47WWM8iPYN75DKCmB/oJWyRjE+eLsI+N/60OeijkWyd5+RbXut 02nkbHPSHEvs0ozGb40NQCDaCprPamFpZNvsbkk06vaS9Jit200cmNeeI9PeMS0yETFC JoEOrGJYNQnaRQTJ0qqeUph5qyZIufVIv0yLma9dhl0EIbnw3aoinHI+4B/6QLmY+oJv blNTjiN+6UIn/vghVNI3n2f7Ovm59MHc6O7JZcbdZj7vA4cjgpZfXm1UXRJCs2R4Rj+g Sm0Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nbZDNiHr; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68147-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68147-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:07 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 07/12] spi: s3c64xx: let the SPI core determine the bus number Date: Fri, 16 Feb 2024 07:05:50 +0000 Message-ID: <20240216070555.2483977-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038377954700333 X-GMAIL-MSGID: 1791038377954700333 Let the core determine the bus number, either by getting the alias ID (as the driver forces now), or by allocating a dynamic bus number when the alias is absent. Prepare the driver to allow dt aliases to be absent. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 68f95c04d092..ac47755beb02 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1279,7 +1279,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->rx_dma.direction = DMA_DEV_TO_MEM; host->dev.of_node = pdev->dev.of_node; - host->bus_num = sdd->port_id; + host->bus_num = -1; host->setup = s3c64xx_spi_setup; host->cleanup = s3c64xx_spi_cleanup; host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; @@ -1360,7 +1360,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) } dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n", - sdd->port_id, host->num_chipselect); + host->bus_num, host->num_chipselect); dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", mem_res, sdd->fifo_depth); From patchwork Fri Feb 16 07:05:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 201972 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp343609dyb; Thu, 15 Feb 2024 23:08:35 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVJ+89YmM8i6rpErkR6+LIovW5XOlaytpektdoTCSdLxafVtxcS5ZccBSDKyK/5iSx/ccC1ylt63Epk8MxrynMyNMBkmw== X-Google-Smtp-Source: AGHT+IEs9HgVdl6LPA73vEkqxYKGx6ubNd+CsThjBvleJhly6zc6II7pjVmDC12mDu6L4xrYSEuY X-Received: by 2002:a05:6a00:148a:b0:6e0:ef8f:6bea with SMTP id v10-20020a056a00148a00b006e0ef8f6beamr4969617pfu.4.1708067314981; Thu, 15 Feb 2024 23:08:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708067314; cv=pass; d=google.com; s=arc-20160816; b=nN9BSmp+OfP1vu8qrgpVI1jGv7QEm7PtZDBnLINMVQgwA9NZwCkbRwT4okck2wIN2q /iwcBHYZHmEbpVMyS7qA1s0vOW1TsVj6ZS6lwpCE7DWjMWEiHftOCu48hirvC2LgaTlH 4DvkDdiOH9qkB1DvUi7Hq1FJVx5G3Ct6IM+4hU3rRsAXI6mbNOLtik5YUu13FCQ326ys TenuQMHfgpW6oI06ircnzV0Z5vH6wMXKPgnx9H4aL9DspEP5Ce2H4dXItpamLKIfg04W rQrFv0V2ShRkiYaFFoZK14OfiQfB224trZfmildbMqdFIToh4cvwXVkYrezcb5D6mhvR FSUA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=D6DI6oxyBGAOnmgH57nVgi2YtxfkZy7vqtRyT86aOak=; fh=0pdjQUCr4sGFROgOFKdiVlNx2t7XkEVLvDYryWxRAKA=; b=JCztC9Ldv5aGhX3Xf7hrMggLWfUifgEuoergcZZlQVITzWy7pwNBzeT3mQK3RYqVMh PQxZGReBVBiaDvZEFeVOcsgrAZmYgrXyK+JaYZmcJK45rl73hCrTSt6tjlObxFXJacg4 CSMju6raGbXvQ6molSeJi8fObkguuW6O7/XJYJElzUnQsvHp6BmQZathfbd7e5Um7rYH rPIotEGGFLBehUrPUFDVbWKsrO7VFhQEVEYNb3H/mUJFlw7FqTVwu9XZ065YnNAn/8m4 5nvgIcPrI8ghIwilpqUnLoUObGk+oOGoqB71r1yo9zZb8mH4tBzryVx6GYkBL0koGyUX z+ug==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RY078VYN; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68149-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68149-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:07 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 08/12] spi: s3c64xx: introduce s3c64xx_spi_set_port_id() Date: Fri, 16 Feb 2024 07:05:51 +0000 Message-ID: <20240216070555.2483977-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038392573248818 X-GMAIL-MSGID: 1791038392573248818 Prepare driver to get rid of the of alias ID dependency. Split the port_id logic into a dedicated method. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 37 +++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index ac47755beb02..40de325bd094 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1200,6 +1200,27 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; } +static int s3c64xx_spi_set_port_id(struct platform_device *pdev, + struct s3c64xx_spi_driver_data *sdd) +{ + int ret; + + if (pdev->dev.of_node) { + ret = of_alias_get_id(pdev->dev.of_node, "spi"); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to get alias id\n"); + sdd->port_id = ret; + } else { + if (pdev->id < 0) + return dev_err_probe(&pdev->dev, -EINVAL, + "Negative platform ID is not allowed\n"); + sdd->port_id = pdev->id; + } + + return 0; +} + static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) { const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; @@ -1252,18 +1273,10 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->host = host; sdd->cntrlr_info = sci; sdd->pdev = pdev; - if (pdev->dev.of_node) { - ret = of_alias_get_id(pdev->dev.of_node, "spi"); - if (ret < 0) - return dev_err_probe(&pdev->dev, ret, - "Failed to get alias id\n"); - sdd->port_id = ret; - } else { - if (pdev->id < 0) - return dev_err_probe(&pdev->dev, -EINVAL, - "Negative platform ID is not allowed\n"); - sdd->port_id = pdev->id; - } + + ret = s3c64xx_spi_set_port_id(pdev, sdd); + if (ret) + return ret; if (sdd->port_conf->fifo_depth) sdd->fifo_depth = sdd->port_conf->fifo_depth; From patchwork Fri Feb 16 07:05:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 201973 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp343690dyb; Thu, 15 Feb 2024 23:08:45 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXPGZKCRo+BbQPCTyhEv7tfLd3KNPdpON6KYvUtvO6W7x3yTrup1uSqFjdrjnezZiRsKi37lh9QoGerJl7vuT+QOuPcbQ== X-Google-Smtp-Source: AGHT+IHuV3k54CEtukawMflvEdSqVnY2vDmLOSRQVeNqHsnFiAxdEgXzQhBuKG3vVrB87eGFGbcC X-Received: by 2002:a17:902:d506:b0:1db:5072:c39b with SMTP id b6-20020a170902d50600b001db5072c39bmr4207674plg.21.1708067325697; Thu, 15 Feb 2024 23:08:45 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708067325; cv=pass; d=google.com; s=arc-20160816; b=FmYv3yOGI3lJSk6KSRcg5Pf5nqXCmMABIUJWyTcsUw1WclYA/qI6hUE81CTnjHprY5 /DBl6X5D74uSUTT1LPLnSdeDCok4j8oG1j9ZqIWqXwaAE+GalaR8gezx0kDEJPjn6S7J h+1s1WuAJ7X8odXAFMvQC/KerQ1cDi8AZyozSiMoj709CKkMfr+UtCtxX2LlZHPDVK4Q 6OOkDO8C8gOn1fXnw9E0xrU0bhZRGPgDLUNccUX4L/I5cLj/LbwjQSOZjBbz/zHWXQXa WjkCJAut44Vk4aeL0T6l1jtRay/4CKv/FWa8EvsmApPfobpzVLPMAlMdz5SUnLHgEubL B0cQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=WkqCfr2t33L8Q9VhOTDSxHGDf/6G9Yy8lK28zIkEPyE=; fh=WWsIUrl55f4zngZx4BgnBCCyLHGKDCDAra1Rmn0yXWI=; b=w9Rf3xfkj6A3pScxMDKLbVKnuJWzGozfyKnf1RmYeyQkx92p0tvEE5lYrLUqq0syKn q91x0MiwLqhuUGKJcFEY+SJ6wj1E1JRmXgVeGrLJ8SWwO4zeAZGH60OV86wSl7h4rAV6 EURmDIsk3VGpNsNx2URIsirDs3p0vB1i9n/Jpto8BGeOVQ9ZOAXw4P6Ilkf/xFAIjcw8 oQcD78CN7xOOxGNBjvnMSW2hWdoS7x9TW1Sng54bhHtsRhaA2z6Jpp4GYZNT7IVtlJ4g /hF9ZeUDQSzXX0UmEg7MTtClFQRyTB2W8QvVndrvKdafsKC2AnFh/F0IKM3TODCv2rF+ NzmQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zVWH9mWi; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68150-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68150-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:08 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 09/12] spi: s3c64xx: get rid of the OF alias ID dependency Date: Fri, 16 Feb 2024 07:05:52 +0000 Message-ID: <20240216070555.2483977-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038403978732725 X-GMAIL-MSGID: 1791038403978732725 Compatibles that set ``port_conf->{rx, tx}_fifomask`` are now safe to get rid of the OF alias ID dependency. Let the driver probe even without the alias for these. With this we also protect the FIFO_LVL_MASK calls from s3c64xx_spi_set_fifomask(). Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 40de325bd094..d2d1c9767145 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1203,8 +1203,12 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( static int s3c64xx_spi_set_port_id(struct platform_device *pdev, struct s3c64xx_spi_driver_data *sdd) { + const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; int ret; + if (port_conf->rx_fifomask && port_conf->tx_fifomask) + return 0; + if (pdev->dev.of_node) { ret = of_alias_get_id(pdev->dev.of_node, "spi"); if (ret < 0) From patchwork Fri Feb 16 07:05:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 201975 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp343869dyb; Thu, 15 Feb 2024 23:09:12 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXxMIIEhwDuJrZZwWXGgeYcVw59X3deMdTdGgcOApoG1sTDq8HerUsHyYPufzvlbFRJpMpuPHPtgpNFWXFj4QcLk6SlsQ== X-Google-Smtp-Source: AGHT+IFJx8KrLcbWE3muD1ljrOcS0POJ3jIMb4C6h3OLplXMOiF/ivDnWC+5YOTaVAoQyXoIqFRF X-Received: by 2002:a05:6870:e99d:b0:218:51de:95e8 with SMTP id r29-20020a056870e99d00b0021851de95e8mr3915717oao.14.1708067352667; Thu, 15 Feb 2024 23:09:12 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708067352; cv=pass; d=google.com; s=arc-20160816; b=S8bYlq7l0SwpEKwelaUlbLITlHU3vopfOyTWcZvZehp1d8NWtpFF3w7KTlPDM223gY zBO8/xFrvCU96L3JNwT8IZEv/PBruSDPf8MQEf+fsp0EGHhmQ/lUut6Akpgge+UvxopX h6awDCS0ZdtEJVQoNeFco2xpoko5wxolKRV8XcggFpaavj7iY1HV560ThKiQMOLmgDYI B+tiiaYbG+ZNSDIyd5mAAzVdfRQIaMrycDayLMSC4lGi4LZbzePWssP1AVK8yM8oUAZT g0hO8hXsJfRg3VZ9Vqv4sUMUcLdV+Q9WR+cPhE/SkR5zUrKj+gvWDYKvABQaPgouReoi ZrvQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=dSklTkqrMVAq4VBR2iaN0vU9yUuhpA9uZMhYyUvuCP8=; fh=CghOVzTwAtn7fSJVulUCjaF8HVWOy41iiSDn8g6TsYc=; b=tvp3Xk2spEqqjwFHK4ef8GrlVqCdzn00HBvFMT76htXQL1EqGwA4KXIIfz+pL2zI4D md9lUMGLuL97Wqy4vkMyOtMMfYRnjJpBl2DR75VQzEO1l7gW9OfPvXoOs2910CXk3Wz1 rPy1VEPlSk+i9xkMLGzYQJ7DQDywvVMt/MhkIkBn/nVE9pdIMnQsofLso0EzdF5cYsTM u92rcGzGp1PtO85VX5f9geArEjUC6OxjPrSwq5z+xuoFNGGmyididbzRkHeHrBKoAzdX A2olu+FMuXtVdDVdBd2LQWlprLBBjLhxg0AS4XrYru26x56Mie7yQJCFT9hn5TI9Pe12 DLUQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r513Bqbn; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-68151-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-68151-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:10 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 10/12] spi: s3c64xx: deprecate fifo_lvl_mask, rx_lvl_offset and port_id Date: Fri, 16 Feb 2024 07:05:53 +0000 Message-ID: <20240216070555.2483977-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038432641111064 X-GMAIL-MSGID: 1791038432641111064 Deprecate fifo_lvl_mask, rx_lvl_offset and port_id. One shall use {rx, tx}_fifomask instead. Add messages to each port configuration. Suggested-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index d2d1c9767145..128f4a7c4bd9 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -135,8 +135,8 @@ struct s3c64xx_spi_dma_data { /** * struct s3c64xx_spi_port_config - SPI Controller hardware info - * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. - * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @fifo_lvl_mask: [DEPRECATED] use @{rx, tx}_fifomask instead. + * @rx_lvl_offset: [DEPRECATED] use @{rx,tx}_fifomask instead. * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. @@ -192,7 +192,7 @@ struct s3c64xx_spi_port_config { * @rx_dma: Local receive DMA data (e.g. chan and direction) * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data - * @port_id: Port identification number + * @port_id: [DEPRECATED] use @{rx,tx}_fifomask instead. * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. @@ -1508,7 +1508,9 @@ static const struct dev_pm_ops s3c64xx_spi_pm = { }; static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 13, .tx_st_done = 21, .clk_div = 2, @@ -1516,14 +1518,18 @@ static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { }; static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7F }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 13, .tx_st_done = 21, .clk_div = 2, }; static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7F }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1531,7 +1537,9 @@ static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1541,7 +1549,9 @@ static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1551,7 +1561,9 @@ static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1562,7 +1574,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 4, @@ -1573,8 +1587,10 @@ static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 4, @@ -1586,7 +1602,9 @@ static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { }; static const struct s3c64xx_spi_port_config fsd_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1597,8 +1615,10 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { }; static const struct s3c64xx_spi_port_config gs101_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + /* rx_lvl_offset is deprecated. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:11 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 11/12] spi: s3c64xx: switch gs101 to new port config data Date: Fri, 16 Feb 2024 07:05:54 +0000 Message-ID: <20240216070555.2483977-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038431863412249 X-GMAIL-MSGID: 1791038431863412249 Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port config data. Advantages of the change: - drop dependency on the OF alias ID. - FIFO depth is inferred from the compatible. GS101 integrates 16 SPI IPs, all with 64 bytes FIFO depths. - use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial masks is misleading and can hide problems of the driver logic. S3C64XX_SPI_ST_TX_FIFO_RDY_V2 was defined based on the USI's SPI_VERSION.USI_IP_VERSION register field, which has value 2 at reset. MAX_SPI_PORTS is updated to reflect the maximum number of ports for the rest of the compatibles. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 128f4a7c4bd9..784786407d2e 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -20,7 +20,7 @@ #include #include -#define MAX_SPI_PORTS 16 +#define MAX_SPI_PORTS 12 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) #define AUTOSUSPEND_TIMEOUT 2000 @@ -79,6 +79,8 @@ #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) +#define S3C64XX_SPI_ST_RX_FIFO_RDY_V2 GENMASK(23, 15) +#define S3C64XX_SPI_ST_TX_FIFO_RDY_V2 GENMASK(14, 6) #define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) @@ -1615,11 +1617,9 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { }; static const struct s3c64xx_spi_port_config gs101_spi_port_config = { - /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ - .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, - 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, - /* rx_lvl_offset is deprecated. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id k18-20020a5d66d2000000b0033940016d6esm1298839wrw.93.2024.02.15.23.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 23:06:12 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 12/12] spi: s3c64xx: switch exynos850 to new port config data Date: Fri, 16 Feb 2024 07:05:55 +0000 Message-ID: <20240216070555.2483977-13-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org> References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791038439886487518 X-GMAIL-MSGID: 1791038439886487518 Exynos850 has the same version of USI SPI (v2.1) as GS101. Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port config data. Backward compatibility with DT is not broken because when alises are set: - the SPI core will set the bus number according to the alias ID - the FIFO depth is always the same size for exynos850 (64 bytes) no matter the alias ID number. Advantages of the change: - drop dependency on the OF alias ID. - FIFO depth is inferred from the compatible. Exynos850 integrates 3 SPI IPs, all with 64 bytes FIFO depths. - use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial masks is misleading and can hide problems of the driver logic. Just compiled tested. Signed-off-by: Tudor Ambarus Tested-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 784786407d2e..9fcbe040cb2f 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1576,10 +1576,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { - /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ - .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, - /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ - .rx_lvl_offset = 15, + .fifo_depth = 64, + .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, + .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, .tx_st_done = 25, .clk_div = 4, .high_speed = true,