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Thu, 15 Feb 2024 08:16:19 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 15 Feb 2024 08:16:19 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 8A85D3F708C; Thu, 15 Feb 2024 08:16:17 -0800 (PST) From: Elad Nachman To: , , , , CC: Subject: [PATCH v2 1/2] mmc: xenon: fix PHY init clock stability Date: Thu, 15 Feb 2024 18:16:12 +0200 Message-ID: <20240215161613.1736051-2-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240215161613.1736051-1-enachman@marvell.com> References: <20240215161613.1736051-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: h4iAQVJ_IHC5IlC5Q9j2V_nHadTX6tiG X-Proofpoint-GUID: h4iAQVJ_IHC5IlC5Q9j2V_nHadTX6tiG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_15,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790997986542666116 X-GMAIL-MSGID: 1790997986542666116 From: Elad Nachman Each time SD/mmc phy is initialized, at times, in some of the attempts, phy fails to completes its initialization which results into timeout error. Per the HW spec, it is a pre-requisite to ensure a stable SD clock before a phy initialization is attempted. Signed-off-by: Elad Nachman --- drivers/mmc/host/sdhci-xenon-phy.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c index 8cf3a375de65..c3096230a969 100644 --- a/drivers/mmc/host/sdhci-xenon-phy.c +++ b/drivers/mmc/host/sdhci-xenon-phy.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include "sdhci-pltfm.h" @@ -216,6 +217,19 @@ static int xenon_alloc_emmc_phy(struct sdhci_host *host) return 0; } +static int xenon_check_stability_internal_clk(struct sdhci_host *host) +{ + u32 reg; + int err; + + err = read_poll_timeout(sdhci_readw, reg, reg & SDHCI_CLOCK_INT_STABLE, + 1100, 20000, false, host, SDHCI_CLOCK_CONTROL); + if (err) + dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n"); + + return err; +} + /* * eMMC 5.0/5.1 PHY init/re-init. * eMMC PHY init should be executed after: @@ -232,6 +246,11 @@ static int xenon_emmc_phy_init(struct sdhci_host *host) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; + int ret = xenon_check_stability_internal_clk(host); + + if (ret) + return ret; + reg = sdhci_readl(host, phy_regs->timing_adj); reg |= XENON_PHY_INITIALIZAION; sdhci_writel(host, reg, phy_regs->timing_adj); From patchwork Thu Feb 15 16:16:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 201704 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp47623dyb; Thu, 15 Feb 2024 10:46:36 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVmGDZh+3zjQ9ro71Itj37fEvZ8OXOoNRPQpIj33le2Kr+Gqq1hEcfOj4aIEQmRCKCuOo6cXNeS03U4x8hCk83oSG0QqA== X-Google-Smtp-Source: AGHT+IFO6efxLq4DCaHzn1euvP6aVVnSXfA577EUOKmFAF00IDEiy2AlwcM8/hzY6Tf+qVdv8qg0 X-Received: by 2002:a17:906:d7bb:b0:a3d:704:d688 with SMTP id pk27-20020a170906d7bb00b00a3d0704d688mr1914786ejb.47.1708022795877; Thu, 15 Feb 2024 10:46:35 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708022795; cv=pass; d=google.com; s=arc-20160816; b=giH9PlGfB4oFVNGat0tX8FXXdpxq4HSFupM5n0x0NUmQYDPbWdhcbrhojDz0Z5+Znu P7R6qqDJ4Fyu/DioIxzqfPMdgqbjqdgbCUERTbktJhlCWiJBjopuanLWIHCmryt3T7Me ET8Wv8pi7QJhIQlZzrO8Qsni9GWgAqQO2Oncp0v+P20o4igKFGvc83wZ2msp+1baPbdd tptmHHz7M1ZhINc9qt9NE9OWomwwUpOPmOMn9ZbTd0YEdutbWSfagcXHFDTAhWaGPRw1 QOgVrOwxNVnrF5LMJPbOddQsKGqyZQqiNqmkl2uhPhKWC7kKLBvRBNVaxyqFyihzqRjQ b3uQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=q4P5OHmYn080DFP0oyNUcqHRE5wGOZYP+WFeEgOmAgY=; fh=dQaW+PkpV6B8DsP7Dkb8SMGnouNee2Ymj5fmrjFCZk0=; b=pjTK4trSB68ljC46e5yV7JN5h/FUlw9CN7XpaxqHE3WXTJ9hY6rk7wuXd5pUIlGU1T Xff9tIcy3reEbmASMhzqthjkC/e/XsQTwvFRyq4XgncyMTpTchWqQQDOTvDSGQiFhRNP sU/DTiGsOr+eylQYwO0sHip0VpP6WjyF8oYrksTqZqfk9/I1q1UzQnkgQH+lCNrBFqJn CQq3EHhJPgWShWMFTtkC+InBVbOasMOKQC64DqY7+HdJG4E/gTqgGVSDPpT4agPd6gkX c0LUKJk+iEHR82giAiuRBqcvFQH3jPBKDMz0dY9YF75KUrN4pfGvnXt2r/Pf1BjEzIwG 9H0w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=LGagqFPU; arc=pass (i=1 dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: domain of linux-kernel+bounces-67298-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-67298-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Thu, 15 Feb 2024 08:16:21 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 15 Feb 2024 08:16:21 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 9BD893F7095; Thu, 15 Feb 2024 08:16:19 -0800 (PST) From: Elad Nachman To: , , , , CC: Subject: [PATCH v2 2/2] mmc: xenon: add timeout for PHY init complete Date: Thu, 15 Feb 2024 18:16:13 +0200 Message-ID: <20240215161613.1736051-3-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240215161613.1736051-1-enachman@marvell.com> References: <20240215161613.1736051-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: qAKbCKW2zkABzLMFkT03CAb1U7QXl2UQ X-Proofpoint-ORIG-GUID: qAKbCKW2zkABzLMFkT03CAb1U7QXl2UQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_15,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790991711572416268 X-GMAIL-MSGID: 1790991711572416268 From: Elad Nachman AC5X spec says PHY init complete bit must be polled until zero. We see cases in which timeout can take longer than the standard calculation on AC5X, which is expected following the spec comment above. According to the spec, we must wait as long as it takes for that bit to toggle on AC5X. Cap that with 100 delay loops so we won't get stuck forever. Signed-off-by: Elad Nachman --- drivers/mmc/host/sdhci-xenon-phy.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c index c3096230a969..cc9d28b75eb9 100644 --- a/drivers/mmc/host/sdhci-xenon-phy.c +++ b/drivers/mmc/host/sdhci-xenon-phy.c @@ -110,6 +110,8 @@ #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18) #define XENON_LOGIC_TIMING_VALUE 0x00AA8977 +#define XENON_MAX_PHY_TIMEOUT_LOOPS 100 + /* * List offset of PHY registers and some special register values * in eMMC PHY 5.0 or eMMC PHY 5.1 @@ -278,18 +280,27 @@ static int xenon_emmc_phy_init(struct sdhci_host *host) /* get the wait time */ wait /= clock; wait++; - /* wait for host eMMC PHY init completes */ - udelay(wait); - reg = sdhci_readl(host, phy_regs->timing_adj); - reg &= XENON_PHY_INITIALIZAION; - if (reg) { + /* + * AC5X spec says bit must be polled until zero. + * We see cases in which timeout can take longer + * than the standard calculation on AC5X, which is + * expected following the spec comment above. + * According to the spec, we must wait as long as + * it takes for that bit to toggle on AC5X. + * Cap that with 100 delay loops so we won't get + * stuck here forever: + */ + + ret = read_poll_timeout(sdhci_readl, reg, + !(reg & XENON_PHY_INITIALIZAION), + wait, XENON_MAX_PHY_TIMEOUT_LOOPS * wait, + false, host, phy_regs->timing_adj); + if (ret) dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", - wait); - return -ETIMEDOUT; - } + wait * XENON_MAX_PHY_TIMEOUT_LOOPS); - return 0; + return ret; } #define ARMADA_3700_SOC_PAD_1_8V 0x1