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Use µs as time unit and express it in the name. Signed-off-by: Théo Lebrun Reviewed-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml index 16024415a4a7..e6b95e3765ac 100644 --- a/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml @@ -70,6 +70,10 @@ properties: minimum: 1 maximum: 400000 + timeout-usecs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Timeout on I2C xfers in µs. + required: - compatible - reg @@ -98,6 +102,7 @@ examples: clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; + timeout-usecs = <200000>; }; i2c@101f8000 { From patchwork Thu Feb 15 16:52:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 201647 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp531078dyb; Thu, 15 Feb 2024 08:53:59 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXdPBYChkLXX7BB3vIuJp5PUk8p0GL9HwxSXnhaQWDW5xvaWek97GBZ5+T/l4tWOlUlCrAXXeIfr6v5cVVtJ4OAQhPpCA== X-Google-Smtp-Source: AGHT+IE9ncqP48SAhGO7peQeGGt1qEPxgqDJdfLDZ4d0QVJL21uxikOSFwO5MWguNRX7rqOy/E+o X-Received: by 2002:a05:620a:7f3:b0:785:beaa:de00 with SMTP id k19-20020a05620a07f300b00785beaade00mr1982613qkk.70.1708016039325; Thu, 15 Feb 2024 08:53:59 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708016039; cv=pass; d=google.com; s=arc-20160816; b=D51Y8IVQk6CBCEIdmEpQ820KbYvSmzhFWGuk2M4mTS7h8ZSGHzyE558gfsNBeuh3D7 f4ElZmxGKH5+11Y20aSH9jCbtzn9eILZNvaY4qupwVAw/q2eChZ8+xpi/x8xLuYqQtWw u8ct9vRjRrczkxTdl3e6Ij2e+OwRVnFONkOQvUT1LtjhCHFf0VtudabF5B7qP32Ekcdt DwGCFUIBXrP7MQf1uG3c3ZRGGgAxgivaih5PMsspoaZdmR7LdLlgI4sPBclzRdnSmT1n b5k8cDzU5M5zwYpklWE8lvztK+ecoCIlvLpes5jUuYbwGXI5j8na86oK1qqcB1CVWcMS Ph0Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=7cLPcJTMJ7JxzGdy5rlF5zI68DecSO20reEkIrekyHo=; fh=5JSnMO1qLgeVtLVJilSQcFnAcZn2MWLSM3RnsAdOnEU=; b=FEVMMWGygOqYaREoKqSPqKA5XfPLCtWEaRg3+Jm3vpVyGxClMGaKoSZVwHGtZDIsa9 2dLyyOfnzYaC7ZSUAfXqSxgM6KN/KWTw1i+qqEvhksbaUMGmcgEBBkbb8zme7l/7RSE9 ImAF0IiCPTWYA0eMqHWsuRgsC0Ah6XEUZqvSbSydajEONeTl5FMVh0YryA5GLIoFB2yc 8bozjLycYqJESBfzVGd9p/4kn+zTtI1HX6z7bR62El2qwAdjulWchPEm+3xgGays7bbw hc7JZN3ffGph5At0JENJE6goIUUMwyEPuolEt7FTlUHTL3mVTlpGf/V5om/TzDGpknx4 TTXA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=l50vrPRP; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-67335-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-67335-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Add the two EyeQ5-specific properties behind a conditional. Add an example for this compatible. Signed-off-by: Théo Lebrun --- .../devicetree/bindings/i2c/st,nomadik-i2c.yaml | 44 ++++++++++++++++++++-- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml index e6b95e3765ac..eaade14b6d4c 100644 --- a/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml @@ -14,9 +14,6 @@ description: The Nomadik I2C host controller began its life in the ST maintainers: - Linus Walleij -allOf: - - $ref: /schemas/i2c/i2c-controller.yaml# - # Need a custom select here or 'arm,primecell' will match on lots of nodes select: properties: @@ -24,6 +21,7 @@ select: contains: enum: - st,nomadik-i2c + - mobileye,eyeq5-i2c required: - compatible @@ -39,6 +37,10 @@ properties: - const: stericsson,db8500-i2c - const: st,nomadik-i2c - const: arm,primecell + # The variant found on Mobileye EyeQ5 + - items: + - const: mobileye,eyeq5-i2c + - const: arm,primecell reg: maxItems: 1 @@ -55,7 +57,7 @@ properties: - items: - const: mclk - const: apb_pclk - # Clock name in DB8500 + # Clock name in DB8500 or EyeQ5 - items: - const: i2cclk - const: apb_pclk @@ -83,6 +85,25 @@ required: unevaluatedProperties: false +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + contains: + const: mobileye,eyeq5-i2c + then: + properties: + mobileye,olb: + $ref: /schemas/types.yaml#/definitions/phandle + description: A phandle to the OLB syscon. + mobileye,id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Platform-wide controller ID (integer starting from zero). + required: + - mobileye,olb + - mobileye,id + examples: - | #include @@ -116,5 +137,20 @@ examples: clocks = <&i2c0clk>, <&pclki2c0>; clock-names = "mclk", "apb_pclk"; }; + - | + #include + i2c@300000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0x300000 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c_ser_clk>, <&i2c_clk>; + clock-names = "i2cclk", "apb_pclk"; + mobileye,olb = <&olb>; + mobileye,id = <0>; + }; ... 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708015955; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ribMBPqXMF0NG1bmqS6MEZxQmeMHwKGVz7dwwg0eqZ0=; b=kWG7BC12XnwCMtgu8iNlZZ1k883FJfp/4NLueKs5RUtF4zoIBip8jNQPyQ2nfFyywkg+Ct x7u6YMzdUP7Aek/2T28DCeM7AR36ForU5LFQSzqhztJE5vpTccmvPpLiq3aB7cBPtfghEa RMtYir9OIFLeCD7xfH0ZdyV1Sb5vzqaDOEpGzWBQsL4LxYQfiKaVjSie831y6qQsDCpPXj hnytIyxnYl4hGDJxv9TD+WzkIgC6Du7os7sLCI0BYfGCu6VaPQnYo7qZV0Kskr98lWHwgq m29O/jQMpd0C7GFvFjYv5sUqrYdqGUzuvlUsHky+YcOKJbtHhnq0bUUWksJs6g== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 15 Feb 2024 17:52:10 +0100 Subject: [PATCH 03/13] dt-bindings: hwmon: lm75: add label property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-mbly-i2c-v1-3-19a336e91dca@bootlin.com> References: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> In-Reply-To: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> To: Linus Walleij , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer Cc: linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Gregory Clement , Vladimir Kondratiev , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= , Jean Delvare , Guenter Roeck , linux-hwmon@vger.kernel.org X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790987159645992649 X-GMAIL-MSGID: 1790987159645992649 Declare optional label devicetree property. Show usage in one example with dummy name. To: Jean Delvare To: Guenter Roeck Cc: Signed-off-by: Théo Lebrun Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/hwmon/lm75.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/lm75.yaml b/Documentation/devicetree/bindings/hwmon/lm75.yaml index ed269e428a3d..5ca2c83b413d 100644 --- a/Documentation/devicetree/bindings/hwmon/lm75.yaml +++ b/Documentation/devicetree/bindings/hwmon/lm75.yaml @@ -52,6 +52,9 @@ properties: interrupts: maxItems: 1 + label: + description: user-facing name of the hardware monitor + required: - compatible - reg @@ -83,6 +86,7 @@ examples: compatible = "st,stlm75"; reg = <0x48>; vs-supply = <&vs>; + label = "CPU temp"; }; }; - | From patchwork Thu Feb 15 16:52:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 201653 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp532440dyb; Thu, 15 Feb 2024 08:56:48 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVp5WYpXMKKvRt51OnYc7GHtvoGm69Aksm0mdOkAgJekEY1GUvb85+75Cnxh7qry0kfmLH7l68PJVGUOSsWpkUyGKmmyg== X-Google-Smtp-Source: AGHT+IFPwyzIM7A9AceN1LsrtFsW8RTe//RoBOjmTIYC09zkk8C+24RtUNFwTra8qiCldb5jo0BI X-Received: by 2002:a05:6870:9a0c:b0:21e:2338:ac9d with SMTP id fo12-20020a0568709a0c00b0021e2338ac9dmr2353605oab.39.1708016207819; Thu, 15 Feb 2024 08:56:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708016207; cv=pass; d=google.com; s=arc-20160816; b=d8vpBLK1LsrT77FdX4Rq1KV3ixOn3O/euV6PNePjZ02hE6BUecKkA/LbjwZomosk3S a4r/er2t6uVQN0Q1VYUjQXRHWsMqcXCLuVCXK46EW/EEHVrSygop8aUfsrCEzX62gPGV RWBi+asnzzqDK/xB+Jd3IPdU8qaYXVRHr07gwYqNfymhtf+1G2JMvhU73X2eCDw1YbsY uURez20LW0fROdb9UnxstLtbKQor543mj6ozi4T4RnaCRS4W+5tftt8jON9P6nkoFNPI p5SjwpgsGQO9WwU5rKrhjWCwWjHqBN9YrZpIt4jx6tTZXpLKDlaXKF+9KwKxhaKyPMSN bzOw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=hyH7SfeXxPg/LI+DuoNNLyUBD7ArBeMQtzlwIGbNgAw=; fh=5JSnMO1qLgeVtLVJilSQcFnAcZn2MWLSM3RnsAdOnEU=; b=eJDRFL/KgNQmokc7DPH0EZ9eMJPpiqlCXhKEl8U3s1W6zngErYP05PBNWl7n1ksAwd cV4/5ZSQQstDeAreOu7joIsrX8WXb0Bz+4MSQjNUkvBWcTTIXtspAyDgp6ggrT8u8DOb 1iTr3Tnlcf+UA0Tem7tNycvBFC3vsk991ghwwyrVc9DetUbyJTypxYeEwvqNhO+CuYoj 2+ZuivHYcQrW5grpER06t97Jv0LTIpkK5elmGW8qBEhiqMrxIDGOuBHvkkN5y7jjvxTS LSpnGgA5XgAsE39+ACPfLwMWwjk9wTnaWhcYVS/Z8BabsvJiQPNMJ1sMVIXOzNrldL7L DoQQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=XcCCPME7; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-67338-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-67338-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708015956; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hyH7SfeXxPg/LI+DuoNNLyUBD7ArBeMQtzlwIGbNgAw=; b=XcCCPME7Zq+RNpxDFty9Koiyfd/VyLwkXa2xaZWAF7LABHuKTpaUT9djezrpdaLPGUldFz Px4FJzAlrIXKcv2J78oYomU8lHBUO/EqkUoyJn2cxDw3SHrrAoqdb/cmaxYMH7cC45ufN/ THGlJr/QqYisQg9xUFsJiMkOdKFfLv6aa0TDzftq1gYFf9fBYuuyrfTUhQehOCdgbXiXTl 5x37KB6fgHPEWDLZ2tGVEvWYQYu/1BXd0x1UTvxAKR3phPR5AaTZNmJjGMWmw+aeou1NEi vVpAisTkVWImhzfB6CiZowxTo3jmH00Y4/o0LxttZYVf/wH8NthFdSLVfOwxMA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 15 Feb 2024 17:52:11 +0100 Subject: [PATCH 04/13] i2c: nomadik: rename private struct pointers from dev to priv Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-mbly-i2c-v1-4-19a336e91dca@bootlin.com> References: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> In-Reply-To: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> To: Linus Walleij , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer Cc: linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Gregory Clement , Vladimir Kondratiev , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790984802754435869 X-GMAIL-MSGID: 1790984802754435869 Disambiguate the usage of dev as a variable name; it is usually best to keep it reserved for struct device pointers. Avoid having multiple names for the same struct pointer (previously: dev, nmk, nmk_i2c). Signed-off-by: Théo Lebrun Reviewed-by: Linus Walleij --- drivers/i2c/busses/i2c-nomadik.c | 428 +++++++++++++++++++-------------------- 1 file changed, 214 insertions(+), 214 deletions(-) diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c index b10574d42b7a..cd511c884f99 100644 --- a/drivers/i2c/busses/i2c-nomadik.c +++ b/drivers/i2c/busses/i2c-nomadik.c @@ -206,12 +206,12 @@ static inline void i2c_clr_bit(void __iomem *reg, u32 mask) /** * flush_i2c_fifo() - This function flushes the I2C FIFO - * @dev: private data of I2C Driver + * @priv: private data of I2C Driver * * This function flushes the I2C Tx and Rx FIFOs. It returns * 0 on successful flushing of FIFO */ -static int flush_i2c_fifo(struct nmk_i2c_dev *dev) +static int flush_i2c_fifo(struct nmk_i2c_dev *priv) { #define LOOP_ATTEMPTS 10 int i; @@ -224,19 +224,19 @@ static int flush_i2c_fifo(struct nmk_i2c_dev *dev) * bits, until then no one must access Tx, Rx FIFO and * should poll on these bits waiting for the completion. */ - writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); + writel((I2C_CR_FTX | I2C_CR_FRX), priv->virtbase + I2C_CR); for (i = 0; i < LOOP_ATTEMPTS; i++) { - timeout = jiffies + dev->adap.timeout; + timeout = jiffies + priv->adap.timeout; while (!time_after(jiffies, timeout)) { - if ((readl(dev->virtbase + I2C_CR) & + if ((readl(priv->virtbase + I2C_CR) & (I2C_CR_FTX | I2C_CR_FRX)) == 0) - return 0; + return 0; } } - dev_err(&dev->adev->dev, + dev_err(&priv->adev->dev, "flushing operation timed out giving up after %d attempts", LOOP_ATTEMPTS); @@ -245,45 +245,45 @@ static int flush_i2c_fifo(struct nmk_i2c_dev *dev) /** * disable_all_interrupts() - Disable all interrupts of this I2c Bus - * @dev: private data of I2C Driver + * @priv: private data of I2C Driver */ -static void disable_all_interrupts(struct nmk_i2c_dev *dev) +static void disable_all_interrupts(struct nmk_i2c_dev *priv) { u32 mask = IRQ_MASK(0); - writel(mask, dev->virtbase + I2C_IMSCR); + writel(mask, priv->virtbase + I2C_IMSCR); } /** * clear_all_interrupts() - Clear all interrupts of I2C Controller - * @dev: private data of I2C Driver + * @priv: private data of I2C Driver */ -static void clear_all_interrupts(struct nmk_i2c_dev *dev) +static void clear_all_interrupts(struct nmk_i2c_dev *priv) { u32 mask; mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); - writel(mask, dev->virtbase + I2C_ICR); + writel(mask, priv->virtbase + I2C_ICR); } /** * init_hw() - initialize the I2C hardware - * @dev: private data of I2C Driver + * @priv: private data of I2C Driver */ -static int init_hw(struct nmk_i2c_dev *dev) +static int init_hw(struct nmk_i2c_dev *priv) { int stat; - stat = flush_i2c_fifo(dev); + stat = flush_i2c_fifo(priv); if (stat) goto exit; /* disable the controller */ - i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); + i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE); - disable_all_interrupts(dev); + disable_all_interrupts(priv); - clear_all_interrupts(dev); + clear_all_interrupts(priv); - dev->cli.operation = I2C_NO_OPERATION; + priv->cli.operation = I2C_NO_OPERATION; exit: return stat; @@ -294,15 +294,15 @@ static int init_hw(struct nmk_i2c_dev *dev) /** * load_i2c_mcr_reg() - load the MCR register - * @dev: private data of controller + * @priv: private data of controller * @flags: message flags */ -static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) +static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *priv, u16 flags) { u32 mcr = 0; unsigned short slave_adr_3msb_bits; - mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); + mcr |= GEN_MASK(priv->cli.slave_adr, I2C_MCR_A7, 1); if (unlikely(flags & I2C_M_TEN)) { /* 10-bit address transaction */ @@ -313,7 +313,7 @@ static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) * the extension (MSB bits) of the 7 bit address loaded * in A7 */ - slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7; + slave_adr_3msb_bits = (priv->cli.slave_adr >> 7) & 0x7; mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); } else { @@ -325,40 +325,40 @@ static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) mcr |= GEN_MASK(0, I2C_MCR_SB, 11); /* check the operation, master read/write? */ - if (dev->cli.operation == I2C_WRITE) + if (priv->cli.operation == I2C_WRITE) mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); else mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); /* stop or repeated start? */ - if (dev->stop) + if (priv->stop) mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); else mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); - mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); + mcr |= GEN_MASK(priv->cli.count, I2C_MCR_LENGTH, 15); return mcr; } /** * setup_i2c_controller() - setup the controller - * @dev: private data of controller + * @priv: private data of controller */ -static void setup_i2c_controller(struct nmk_i2c_dev *dev) +static void setup_i2c_controller(struct nmk_i2c_dev *priv) { u32 brcr1, brcr2; u32 i2c_clk, div; u32 ns; u16 slsu; - writel(0x0, dev->virtbase + I2C_CR); - writel(0x0, dev->virtbase + I2C_HSMCR); - writel(0x0, dev->virtbase + I2C_TFTR); - writel(0x0, dev->virtbase + I2C_RFTR); - writel(0x0, dev->virtbase + I2C_DMAR); + writel(0x0, priv->virtbase + I2C_CR); + writel(0x0, priv->virtbase + I2C_HSMCR); + writel(0x0, priv->virtbase + I2C_TFTR); + writel(0x0, priv->virtbase + I2C_RFTR); + writel(0x0, priv->virtbase + I2C_DMAR); - i2c_clk = clk_get_rate(dev->clk); + i2c_clk = clk_get_rate(priv->clk); /* * set the slsu: @@ -373,7 +373,7 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev) * slsu = cycles / (1000000000 / f) + 1 */ ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk); - switch (dev->sm) { + switch (priv->sm) { case I2C_FREQ_MODE_FAST: case I2C_FREQ_MODE_FAST_PLUS: slsu = DIV_ROUND_UP(100, ns); /* Fast */ @@ -388,15 +388,15 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev) } slsu += 1; - dev_dbg(&dev->adev->dev, "calculated SLSU = %04x\n", slsu); - writel(slsu << 16, dev->virtbase + I2C_SCR); + dev_dbg(&priv->adev->dev, "calculated SLSU = %04x\n", slsu); + writel(slsu << 16, priv->virtbase + I2C_SCR); /* * The spec says, in case of std. mode the divider is * 2 whereas it is 3 for fast and fastplus mode of * operation. TODO - high speed support. */ - div = (dev->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2; + div = (priv->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2; /* * generate the mask for baud rate counters. The controller @@ -406,10 +406,10 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev) * so set brcr1 to 0. */ brcr1 = 0 << 16; - brcr2 = (i2c_clk/(dev->clk_freq * div)) & 0xffff; + brcr2 = (i2c_clk / (priv->clk_freq * div)) & 0xffff; /* set the baud rate counter register */ - writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); + writel((brcr1 | brcr2), priv->virtbase + I2C_BRCR); /* * set the speed mode. Currently we support @@ -417,125 +417,124 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev) * TODO - support for fast mode plus (up to 1Mb/s) * and high speed (up to 3.4 Mb/s) */ - if (dev->sm > I2C_FREQ_MODE_FAST) { - dev_err(&dev->adev->dev, + if (priv->sm > I2C_FREQ_MODE_FAST) { + dev_err(&priv->adev->dev, "do not support this mode defaulting to std. mode\n"); brcr2 = i2c_clk / (I2C_MAX_STANDARD_MODE_FREQ * 2) & 0xffff; - writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); + writel((brcr1 | brcr2), priv->virtbase + I2C_BRCR); writel(I2C_FREQ_MODE_STANDARD << 4, - dev->virtbase + I2C_CR); + priv->virtbase + I2C_CR); } - writel(dev->sm << 4, dev->virtbase + I2C_CR); + writel(priv->sm << 4, priv->virtbase + I2C_CR); /* set the Tx and Rx FIFO threshold */ - writel(dev->tft, dev->virtbase + I2C_TFTR); - writel(dev->rft, dev->virtbase + I2C_RFTR); + writel(priv->tft, priv->virtbase + I2C_TFTR); + writel(priv->rft, priv->virtbase + I2C_RFTR); } /** * read_i2c() - Read from I2C client device - * @dev: private data of I2C Driver + * @priv: private data of I2C Driver * @flags: message flags * * This function reads from i2c client device when controller is in * master mode. There is a completion timeout. If there is no transfer * before timeout error is returned. */ -static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) +static int read_i2c(struct nmk_i2c_dev *priv, u16 flags) { int status = 0; u32 mcr, irq_mask; unsigned long timeout; - mcr = load_i2c_mcr_reg(dev, flags); - writel(mcr, dev->virtbase + I2C_MCR); + mcr = load_i2c_mcr_reg(priv, flags); + writel(mcr, priv->virtbase + I2C_MCR); /* load the current CR value */ - writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, - dev->virtbase + I2C_CR); + writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, + priv->virtbase + I2C_CR); /* enable the controller */ - i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); + i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE); - init_completion(&dev->xfer_complete); + init_completion(&priv->xfer_complete); /* enable interrupts by setting the mask */ irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | I2C_IT_MAL | I2C_IT_BERR); - if (dev->stop || !dev->vendor->has_mtdws) + if (priv->stop || !priv->vendor->has_mtdws) irq_mask |= I2C_IT_MTD; else irq_mask |= I2C_IT_MTDWS; irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); - writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, - dev->virtbase + I2C_IMSCR); + writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask, + priv->virtbase + I2C_IMSCR); timeout = wait_for_completion_timeout( - &dev->xfer_complete, dev->adap.timeout); + &priv->xfer_complete, priv->adap.timeout); if (timeout == 0) { /* Controller timed out */ - dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n", - dev->cli.slave_adr); + dev_err(&priv->adev->dev, "read from slave 0x%x timed out\n", + priv->cli.slave_adr); status = -ETIMEDOUT; } return status; } -static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes) +static void fill_tx_fifo(struct nmk_i2c_dev *priv, int no_bytes) { int count; for (count = (no_bytes - 2); (count > 0) && - (dev->cli.count != 0); + (priv->cli.count != 0); count--) { /* write to the Tx FIFO */ - writeb(*dev->cli.buffer, - dev->virtbase + I2C_TFR); - dev->cli.buffer++; - dev->cli.count--; - dev->cli.xfer_bytes++; + writeb(*priv->cli.buffer, priv->virtbase + I2C_TFR); + priv->cli.buffer++; + priv->cli.count--; + priv->cli.xfer_bytes++; } } /** * write_i2c() - Write data to I2C client. - * @dev: private data of I2C Driver + * @priv: private data of I2C Driver * @flags: message flags * * This function writes data to I2C client */ -static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) +static int write_i2c(struct nmk_i2c_dev *priv, u16 flags) { u32 status = 0; u32 mcr, irq_mask; unsigned long timeout; - mcr = load_i2c_mcr_reg(dev, flags); + mcr = load_i2c_mcr_reg(priv, flags); - writel(mcr, dev->virtbase + I2C_MCR); + writel(mcr, priv->virtbase + I2C_MCR); /* load the current CR value */ - writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, - dev->virtbase + I2C_CR); + writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, + priv->virtbase + I2C_CR); /* enable the controller */ - i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); + i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE); - init_completion(&dev->xfer_complete); + init_completion(&priv->xfer_complete); /* enable interrupts by settings the masks */ irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); /* Fill the TX FIFO with transmit data */ - fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD); + fill_tx_fifo(priv, MAX_I2C_FIFO_THRESHOLD); - if (dev->cli.count != 0) + if (priv->cli.count != 0) irq_mask |= I2C_IT_TXFNE; /* @@ -543,23 +542,23 @@ static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) * set the MTDWS bit (Master Transaction Done Without Stop) * to start repeated start operation */ - if (dev->stop || !dev->vendor->has_mtdws) + if (priv->stop || !priv->vendor->has_mtdws) irq_mask |= I2C_IT_MTD; else irq_mask |= I2C_IT_MTDWS; irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); - writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, - dev->virtbase + I2C_IMSCR); + writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask, + priv->virtbase + I2C_IMSCR); timeout = wait_for_completion_timeout( - &dev->xfer_complete, dev->adap.timeout); + &priv->xfer_complete, priv->adap.timeout); if (timeout == 0) { /* Controller timed out */ - dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n", - dev->cli.slave_adr); + dev_err(&priv->adev->dev, "write to slave 0x%x timed out\n", + priv->cli.slave_adr); status = -ETIMEDOUT; } @@ -568,28 +567,28 @@ static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) /** * nmk_i2c_xfer_one() - transmit a single I2C message - * @dev: device with a message encoded into it + * @priv: device with a message encoded into it * @flags: message flags */ -static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags) +static int nmk_i2c_xfer_one(struct nmk_i2c_dev *priv, u16 flags) { int status; if (flags & I2C_M_RD) { /* read operation */ - dev->cli.operation = I2C_READ; - status = read_i2c(dev, flags); + priv->cli.operation = I2C_READ; + status = read_i2c(priv, flags); } else { /* write operation */ - dev->cli.operation = I2C_WRITE; - status = write_i2c(dev, flags); + priv->cli.operation = I2C_WRITE; + status = write_i2c(priv, flags); } - if (status || (dev->result)) { + if (status || priv->result) { u32 i2c_sr; u32 cause; - i2c_sr = readl(dev->virtbase + I2C_SR); + i2c_sr = readl(priv->virtbase + I2C_SR); /* * Check if the controller I2C operation status * is set to ABORT(11b). @@ -597,15 +596,15 @@ static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags) if (((i2c_sr >> 2) & 0x3) == 0x3) { /* get the abort cause */ cause = (i2c_sr >> 4) & 0x7; - dev_err(&dev->adev->dev, "%s\n", + dev_err(&priv->adev->dev, "%s\n", cause >= ARRAY_SIZE(abort_causes) ? "unknown reason" : abort_causes[cause]); } - (void) init_hw(dev); + init_hw(priv); - status = status ? status : dev->result; + status = status ? status : priv->result; } return status; @@ -663,24 +662,24 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, { int status = 0; int i; - struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); + struct nmk_i2c_dev *priv = i2c_get_adapdata(i2c_adap); int j; - pm_runtime_get_sync(&dev->adev->dev); + pm_runtime_get_sync(&priv->adev->dev); /* Attempt three times to send the message queue */ for (j = 0; j < 3; j++) { /* setup the i2c controller */ - setup_i2c_controller(dev); + setup_i2c_controller(priv); for (i = 0; i < num_msgs; i++) { - dev->cli.slave_adr = msgs[i].addr; - dev->cli.buffer = msgs[i].buf; - dev->cli.count = msgs[i].len; - dev->stop = (i < (num_msgs - 1)) ? 0 : 1; - dev->result = 0; + priv->cli.slave_adr = msgs[i].addr; + priv->cli.buffer = msgs[i].buf; + priv->cli.count = msgs[i].len; + priv->stop = (i < (num_msgs - 1)) ? 0 : 1; + priv->result = 0; - status = nmk_i2c_xfer_one(dev, msgs[i].flags); + status = nmk_i2c_xfer_one(priv, msgs[i].flags); if (status != 0) break; } @@ -688,7 +687,7 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, break; } - pm_runtime_put_sync(&dev->adev->dev); + pm_runtime_put_sync(&priv->adev->dev); /* return the no. messages processed */ if (status) @@ -699,14 +698,14 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, /** * disable_interrupts() - disable the interrupts - * @dev: private data of controller + * @priv: private data of controller * @irq: interrupt number */ -static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) +static int disable_interrupts(struct nmk_i2c_dev *priv, u32 irq) { irq = IRQ_MASK(irq); - writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), - dev->virtbase + I2C_IMSCR); + writel(readl(priv->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), + priv->virtbase + I2C_IMSCR); return 0; } @@ -723,17 +722,18 @@ static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) */ static irqreturn_t i2c_irq_handler(int irq, void *arg) { - struct nmk_i2c_dev *dev = arg; + struct nmk_i2c_dev *priv = arg; + struct device *dev = &priv->adev->dev; u32 tft, rft; u32 count; u32 misr, src; /* load Tx FIFO and Rx FIFO threshold values */ - tft = readl(dev->virtbase + I2C_TFTR); - rft = readl(dev->virtbase + I2C_RFTR); + tft = readl(priv->virtbase + I2C_TFTR); + rft = readl(priv->virtbase + I2C_RFTR); /* read interrupt status register */ - misr = readl(dev->virtbase + I2C_MISR); + misr = readl(priv->virtbase + I2C_MISR); src = __ffs(misr); switch ((1 << src)) { @@ -741,20 +741,20 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) /* Transmit FIFO nearly empty interrupt */ case I2C_IT_TXFNE: { - if (dev->cli.operation == I2C_READ) { + if (priv->cli.operation == I2C_READ) { /* * in read operation why do we care for writing? * so disable the Transmit FIFO interrupt */ - disable_interrupts(dev, I2C_IT_TXFNE); + disable_interrupts(priv, I2C_IT_TXFNE); } else { - fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft)); + fill_tx_fifo(priv, (MAX_I2C_FIFO_THRESHOLD - tft)); /* * if done, close the transfer by disabling the * corresponding TXFNE interrupt */ - if (dev->cli.count == 0) - disable_interrupts(dev, I2C_IT_TXFNE); + if (priv->cli.count == 0) + disable_interrupts(priv, I2C_IT_TXFNE); } } break; @@ -768,60 +768,59 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) case I2C_IT_RXFNF: for (count = rft; count > 0; count--) { /* Read the Rx FIFO */ - *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); - dev->cli.buffer++; + *priv->cli.buffer = readb(priv->virtbase + I2C_RFR); + priv->cli.buffer++; } - dev->cli.count -= rft; - dev->cli.xfer_bytes += rft; + priv->cli.count -= rft; + priv->cli.xfer_bytes += rft; break; /* Rx FIFO full */ case I2C_IT_RXFF: for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { - *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); - dev->cli.buffer++; + *priv->cli.buffer = readb(priv->virtbase + I2C_RFR); + priv->cli.buffer++; } - dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; - dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; + priv->cli.count -= MAX_I2C_FIFO_THRESHOLD; + priv->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; break; /* Master Transaction Done with/without stop */ case I2C_IT_MTD: case I2C_IT_MTDWS: - if (dev->cli.operation == I2C_READ) { - while (!(readl(dev->virtbase + I2C_RISR) + if (priv->cli.operation == I2C_READ) { + while (!(readl(priv->virtbase + I2C_RISR) & I2C_IT_RXFE)) { - if (dev->cli.count == 0) + if (priv->cli.count == 0) break; - *dev->cli.buffer = - readb(dev->virtbase + I2C_RFR); - dev->cli.buffer++; - dev->cli.count--; - dev->cli.xfer_bytes++; + *priv->cli.buffer = + readb(priv->virtbase + I2C_RFR); + priv->cli.buffer++; + priv->cli.count--; + priv->cli.xfer_bytes++; } } - disable_all_interrupts(dev); - clear_all_interrupts(dev); + disable_all_interrupts(priv); + clear_all_interrupts(priv); - if (dev->cli.count) { - dev->result = -EIO; - dev_err(&dev->adev->dev, - "%lu bytes still remain to be xfered\n", - dev->cli.count); - (void) init_hw(dev); + if (priv->cli.count) { + priv->result = -EIO; + dev_err(dev, "%lu bytes still remain to be xfered\n", + priv->cli.count); + init_hw(priv); } - complete(&dev->xfer_complete); + complete(&priv->xfer_complete); break; /* Master Arbitration lost interrupt */ case I2C_IT_MAL: - dev->result = -EIO; - (void) init_hw(dev); + priv->result = -EIO; + init_hw(priv); - i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); - complete(&dev->xfer_complete); + i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_MAL); + complete(&priv->xfer_complete); break; @@ -831,13 +830,13 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) * during the transaction. */ case I2C_IT_BERR: - dev->result = -EIO; + priv->result = -EIO; /* get the status */ - if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) - (void) init_hw(dev); + if (((readl(priv->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) + init_hw(priv); - i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); - complete(&dev->xfer_complete); + i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_BERR); + complete(&priv->xfer_complete); break; @@ -847,11 +846,11 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) * the Tx FIFO is full. */ case I2C_IT_TXFOVR: - dev->result = -EIO; - (void) init_hw(dev); + priv->result = -EIO; + init_hw(priv); - dev_err(&dev->adev->dev, "Tx Fifo Over run\n"); - complete(&dev->xfer_complete); + dev_err(dev, "Tx Fifo Over run\n"); + complete(&priv->xfer_complete); break; @@ -863,10 +862,10 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) case I2C_IT_RFSE: case I2C_IT_WTSR: case I2C_IT_STD: - dev_err(&dev->adev->dev, "unhandled Interrupt\n"); + dev_err(dev, "unhandled Interrupt\n"); break; default: - dev_err(&dev->adev->dev, "spurious Interrupt..\n"); + dev_err(dev, "spurious Interrupt..\n"); break; } @@ -893,9 +892,9 @@ static int nmk_i2c_resume_early(struct device *dev) static int nmk_i2c_runtime_suspend(struct device *dev) { struct amba_device *adev = to_amba_device(dev); - struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); + struct nmk_i2c_dev *priv = amba_get_drvdata(adev); - clk_disable_unprepare(nmk_i2c->clk); + clk_disable_unprepare(priv->clk); pinctrl_pm_select_idle_state(dev); return 0; } @@ -903,10 +902,10 @@ static int nmk_i2c_runtime_suspend(struct device *dev) static int nmk_i2c_runtime_resume(struct device *dev) { struct amba_device *adev = to_amba_device(dev); - struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); + struct nmk_i2c_dev *priv = amba_get_drvdata(adev); int ret; - ret = clk_prepare_enable(nmk_i2c->clk); + ret = clk_prepare_enable(priv->clk); if (ret) { dev_err(dev, "can't prepare_enable clock\n"); return ret; @@ -914,9 +913,9 @@ static int nmk_i2c_runtime_resume(struct device *dev) pinctrl_pm_select_default_state(dev); - ret = init_hw(nmk_i2c); + ret = init_hw(priv); if (ret) { - clk_disable_unprepare(nmk_i2c->clk); + clk_disable_unprepare(priv->clk); pinctrl_pm_select_idle_state(dev); } @@ -939,107 +938,108 @@ static const struct i2c_algorithm nmk_i2c_algo = { }; static void nmk_i2c_of_probe(struct device_node *np, - struct nmk_i2c_dev *nmk) + struct nmk_i2c_dev *priv) { /* Default to 100 kHz if no frequency is given in the node */ - if (of_property_read_u32(np, "clock-frequency", &nmk->clk_freq)) - nmk->clk_freq = I2C_MAX_STANDARD_MODE_FREQ; + if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq)) + priv->clk_freq = I2C_MAX_STANDARD_MODE_FREQ; /* This driver only supports 'standard' and 'fast' modes of operation. */ - if (nmk->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) - nmk->sm = I2C_FREQ_MODE_STANDARD; + if (priv->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) + priv->sm = I2C_FREQ_MODE_STANDARD; else - nmk->sm = I2C_FREQ_MODE_FAST; - nmk->tft = 1; /* Tx FIFO threshold */ - nmk->rft = 8; /* Rx FIFO threshold */ - nmk->timeout = 200; /* Slave response timeout(ms) */ + priv->sm = I2C_FREQ_MODE_FAST; + priv->tft = 1; /* Tx FIFO threshold */ + priv->rft = 8; /* Rx FIFO threshold */ + priv->timeout = 200; /* Slave response timeout(ms) */ } static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) { int ret = 0; + struct nmk_i2c_dev *priv; struct device_node *np = adev->dev.of_node; - struct nmk_i2c_dev *dev; + struct device *dev = &adev->dev; struct i2c_adapter *adap; struct i2c_vendor_data *vendor = id->data; u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1; - dev = devm_kzalloc(&adev->dev, sizeof(*dev), GFP_KERNEL); - if (!dev) + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) return -ENOMEM; - dev->vendor = vendor; - dev->adev = adev; - nmk_i2c_of_probe(np, dev); + priv->vendor = vendor; + priv->adev = adev; + nmk_i2c_of_probe(np, priv); - if (dev->tft > max_fifo_threshold) { - dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n", - dev->tft, max_fifo_threshold); - dev->tft = max_fifo_threshold; + if (priv->tft > max_fifo_threshold) { + dev_warn(dev, "requested TX FIFO threshold %u, adjusted down to %u\n", + priv->tft, max_fifo_threshold); + priv->tft = max_fifo_threshold; } - if (dev->rft > max_fifo_threshold) { - dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n", - dev->rft, max_fifo_threshold); - dev->rft = max_fifo_threshold; + if (priv->rft > max_fifo_threshold) { + dev_warn(dev, "requested RX FIFO threshold %u, adjusted down to %u\n", + priv->rft, max_fifo_threshold); + priv->rft = max_fifo_threshold; } - amba_set_drvdata(adev, dev); + amba_set_drvdata(adev, priv); - dev->virtbase = devm_ioremap(&adev->dev, adev->res.start, - resource_size(&adev->res)); - if (!dev->virtbase) + priv->virtbase = devm_ioremap(dev, adev->res.start, + resource_size(&adev->res)); + if (!priv->virtbase) return -ENOMEM; - dev->irq = adev->irq[0]; - ret = devm_request_irq(&adev->dev, dev->irq, i2c_irq_handler, 0, - DRIVER_NAME, dev); + priv->irq = adev->irq[0]; + ret = devm_request_irq(dev, priv->irq, i2c_irq_handler, 0, + DRIVER_NAME, priv); if (ret) - return dev_err_probe(&adev->dev, ret, - "cannot claim the irq %d\n", dev->irq); + return dev_err_probe(dev, ret, + "cannot claim the irq %d\n", priv->irq); - dev->clk = devm_clk_get_enabled(&adev->dev, NULL); - if (IS_ERR(dev->clk)) - return dev_err_probe(&adev->dev, PTR_ERR(dev->clk), + priv->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), "could enable i2c clock\n"); - init_hw(dev); + init_hw(priv); - adap = &dev->adap; + adap = &priv->adap; adap->dev.of_node = np; - adap->dev.parent = &adev->dev; + adap->dev.parent = dev; adap->owner = THIS_MODULE; adap->class = I2C_CLASS_DEPRECATED; adap->algo = &nmk_i2c_algo; - adap->timeout = msecs_to_jiffies(dev->timeout); + adap->timeout = msecs_to_jiffies(priv->timeout); snprintf(adap->name, sizeof(adap->name), "Nomadik I2C at %pR", &adev->res); - i2c_set_adapdata(adap, dev); + i2c_set_adapdata(adap, priv); - dev_info(&adev->dev, + dev_info(dev, "initialize %s on virtual base %p\n", - adap->name, dev->virtbase); + adap->name, priv->virtbase); ret = i2c_add_adapter(adap); if (ret) return ret; - pm_runtime_put(&adev->dev); + pm_runtime_put(dev); return 0; } static void nmk_i2c_remove(struct amba_device *adev) { - struct nmk_i2c_dev *dev = amba_get_drvdata(adev); + struct nmk_i2c_dev *priv = amba_get_drvdata(adev); - i2c_del_adapter(&dev->adap); - flush_i2c_fifo(dev); - disable_all_interrupts(dev); - clear_all_interrupts(dev); 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One masks the top three bits off as reserved, the other one masks the reserved IRQs inside the u32. Get rid of IRQ_MASK and only use the most restrictive mask. Signed-off-by: Théo Lebrun Reviewed-by: Linus Walleij --- drivers/i2c/busses/i2c-nomadik.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c index cd511c884f99..80bdf7e42613 100644 --- a/drivers/i2c/busses/i2c-nomadik.c +++ b/drivers/i2c/busses/i2c-nomadik.c @@ -94,9 +94,6 @@ /* some bits in ICR are reserved */ #define I2C_CLEAR_ALL_INTS 0x131f007f -/* first three msb bits are reserved */ -#define IRQ_MASK(mask) (mask & 0x1fffffff) - /* maximum threshold value */ #define MAX_I2C_FIFO_THRESHOLD 15 @@ -249,8 +246,7 @@ static int flush_i2c_fifo(struct nmk_i2c_dev *priv) */ static void disable_all_interrupts(struct nmk_i2c_dev *priv) { - u32 mask = IRQ_MASK(0); - writel(mask, priv->virtbase + I2C_IMSCR); + writel(0, priv->virtbase + I2C_IMSCR); } /** @@ -259,9 +255,7 @@ static void disable_all_interrupts(struct nmk_i2c_dev *priv) */ static void clear_all_interrupts(struct nmk_i2c_dev *priv) { - u32 mask; - mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); - writel(mask, priv->virtbase + I2C_ICR); + writel(I2C_CLEAR_ALL_INTS, priv->virtbase + I2C_ICR); } /** @@ -468,7 +462,7 @@ static int read_i2c(struct nmk_i2c_dev *priv, u16 flags) else irq_mask |= I2C_IT_MTDWS; - irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); + irq_mask &= I2C_CLEAR_ALL_INTS; writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask, priv->virtbase + I2C_IMSCR); @@ -547,7 +541,7 @@ static int write_i2c(struct nmk_i2c_dev *priv, u16 flags) else irq_mask |= I2C_IT_MTDWS; - irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); + irq_mask &= I2C_CLEAR_ALL_INTS; writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask, priv->virtbase + I2C_IMSCR); @@ -703,8 +697,8 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, */ static int disable_interrupts(struct nmk_i2c_dev *priv, u32 irq) { - irq = IRQ_MASK(irq); - writel(readl(priv->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), + irq &= I2C_CLEAR_ALL_INTS; + writel(readl(priv->virtbase + I2C_IMSCR) & ~irq, priv->virtbase + I2C_IMSCR); return 0; } From patchwork Thu Feb 15 16:52:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 201650 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp531973dyb; Thu, 15 Feb 2024 08:55:51 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWASO67NaVFwaKFJMm1j78apoUvCT9CCYCmGuNLnZHmbPBLplu+ZLQrlaqDzWJemKLUTywU8g1y9WMaL38KJW43mx80mA== X-Google-Smtp-Source: AGHT+IE68jplEyhQdsPbR9BdNnGXfAINySdVGiYr8XuVo40FPriXZtF6IMOi6434Sry6QrSadfAF X-Received: by 2002:a17:906:2514:b0:a38:4c33:cfde with SMTP id i20-20020a170906251400b00a384c33cfdemr1553179ejb.29.1708016151389; Thu, 15 Feb 2024 08:55:51 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708016151; cv=pass; d=google.com; s=arc-20160816; b=pSf8aUmUDpf+W2DniMfa3HNMdSBHO+tASphD8i5G7dZhexrv3ydtQL02I4dcnRoriH KanvLvQAiMVb9TtZqcYdDwxuKj/19X3z6P6uqV/kENFw7yBgCo5YyTV0eYYjmlYoR4Kw KntcjhIP0if4TtfvSxm6VV2vHa8MoZ4rnMKYxzI9yzyVS/iV+Huoby/cDQM94nhpgjuc k+PWkSYFeHiheiEOJ0n/rWwPpjrMfptcdL5RDW2rpfPiE88/WWsgT9HH9bgEgtP6Wf3y 8HiLwDITTg5sB68AVVJTQBNzZS+4BUjeq7gfnfx0GXbQXzkw9Tx23mj0C1+2DMb+5cVb 90nA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=Ch8tjKPy7nBDupOpE8cNjrCAOYNZCyjkUOP1wYjWAEI=; fh=5JSnMO1qLgeVtLVJilSQcFnAcZn2MWLSM3RnsAdOnEU=; b=JF3xFNDpWxdyNfMXzlK2HGLhN00zUVlMhnoCO15u5wL0zIT7wp7THaFSya/oCJEM5Q T5DksomKSTOGfuGfYmkEt6z8JS1xkiwNLeru3DVMBE1CgvRb4sg9y0GzqBu4BBufO2Wf Fblwkl1jv3kX1XOm0vRXboa17xS3bLANgyqavv3kxuEVi5pxh/Mj60q/gas6eIFrBlgs OLApwSXNPuouOATV+LC7zxPKxP4wC+DjnYp8bzts+2gkeUKa6XzhJeLlIFnyoHt1KQr+ emKRk/5XLyXy/bpTxGbe00F3vl2Iiw8nlUu/MRPuUJG5rxm9Q2n3h5Nu3xMPz96nsI6x PvlQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b="VVirSm/5"; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-67339-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-67339-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708015957; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ch8tjKPy7nBDupOpE8cNjrCAOYNZCyjkUOP1wYjWAEI=; b=VVirSm/5GxKXpZJE22DcH0Nr7q0tP0ItL/g2COO4hLKbCUakOI72ciJOJb6n4LTX5WHQEY Y6CCjcskndgXiFrKn8fzmupYoJo4nUTnu6KWCjP6MXaRX3cHj1Zy0my9c1h0LQuhjNbEM5 I6q1o+vrhk1I6vTB41bl46pL0Ha+SEc/iHKBUWdqwNB1fpPRcaE5A7unoIa00lGzTtjrTH LJ/fDgej+wiP09v3pBBDGogbantMurLecZH2xD9Q/eqRfdo5pYkbmWSgBGicYnfiYZoMI4 CWXRJZMHuQk1q1eQi5RNQps1U5Jb2xaQ0x5IWhZmSRc3N1J1/TKrJwRubKWVTA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 15 Feb 2024 17:52:13 +0100 Subject: [PATCH 06/13] i2c: nomadik: use bitops helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-mbly-i2c-v1-6-19a336e91dca@bootlin.com> References: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> In-Reply-To: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> To: Linus Walleij , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer Cc: linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Gregory Clement , Vladimir Kondratiev , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790984743956971735 X-GMAIL-MSGID: 1790984743956971735 Constant register bit fields are declared using hardcoded hex values; replace them by calls to BIT() and GENMASK(). Replace custom GEN_MASK() macro by the generic FIELD_PREP(). Replace manual bit manipulations by the generic FIELD_GET() macro. Signed-off-by: Théo Lebrun Reviewed-by: Linus Walleij --- drivers/i2c/busses/i2c-nomadik.c | 150 ++++++++++++++++++++------------------- 1 file changed, 77 insertions(+), 73 deletions(-) diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c index 80bdf7e42613..aa68ab402b10 100644 --- a/drivers/i2c/busses/i2c-nomadik.c +++ b/drivers/i2c/busses/i2c-nomadik.c @@ -9,6 +9,7 @@ * Author: Srinidhi Kasagar * Author: Sachin Verma */ +#include #include #include #include @@ -42,54 +43,59 @@ #define I2C_ICR (0x038) /* Control registers */ -#define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ -#define I2C_CR_OM (0x3 << 1) /* Operating mode */ -#define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ -#define I2C_CR_SM (0x3 << 4) /* Speed mode */ -#define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ -#define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ -#define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ -#define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ -#define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ -#define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ -#define I2C_CR_LM (0x1 << 12) /* Loopback mode */ -#define I2C_CR_FON (0x3 << 13) /* Filtering on */ -#define I2C_CR_FS (0x3 << 15) /* Force stop enable */ +#define I2C_CR_PE BIT(0) /* Peripheral Enable */ +#define I2C_CR_OM GENMASK(2, 1) /* Operating mode */ +#define I2C_CR_SAM BIT(3) /* Slave addressing mode */ +#define I2C_CR_SM GENMASK(5, 4) /* Speed mode */ +#define I2C_CR_SGCM BIT(6) /* Slave general call mode */ +#define I2C_CR_FTX BIT(7) /* Flush Transmit */ +#define I2C_CR_FRX BIT(8) /* Flush Receive */ +#define I2C_CR_DMA_TX_EN BIT(9) /* DMA Tx enable */ +#define I2C_CR_DMA_RX_EN BIT(10) /* DMA Rx Enable */ +#define I2C_CR_DMA_SLE BIT(11) /* DMA sync. logic enable */ +#define I2C_CR_LM BIT(12) /* Loopback mode */ +#define I2C_CR_FON GENMASK(14, 13) /* Filtering on */ +#define I2C_CR_FS GENMASK(16, 15) /* Force stop enable */ + +/* Slave control register (SCR) */ +#define I2C_SCR_SLSU GENMASK(31, 16) /* Slave data setup time */ /* Master controller (MCR) register */ -#define I2C_MCR_OP (0x1 << 0) /* Operation */ -#define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ -#define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ -#define I2C_MCR_SB (0x1 << 11) /* Extended address */ -#define I2C_MCR_AM (0x3 << 12) /* Address type */ -#define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ -#define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ +#define I2C_MCR_OP BIT(0) /* Operation */ +#define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */ +#define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */ +#define I2C_MCR_SB BIT(11) /* Extended address */ +#define I2C_MCR_AM GENMASK(13, 12) /* Address type */ +#define I2C_MCR_STOP BIT(14) /* Stop condition */ +#define I2C_MCR_LENGTH GENMASK(25, 15) /* Transaction length */ /* Status register (SR) */ -#define I2C_SR_OP (0x3 << 0) /* Operation */ -#define I2C_SR_STATUS (0x3 << 2) /* controller status */ -#define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ -#define I2C_SR_TYPE (0x3 << 7) /* Receive type */ -#define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ +#define I2C_SR_OP GENMASK(1, 0) /* Operation */ +#define I2C_SR_STATUS GENMASK(3, 2) /* controller status */ +#define I2C_SR_CAUSE GENMASK(6, 4) /* Abort cause */ +#define I2C_SR_TYPE GENMASK(8, 7) /* Receive type */ +#define I2C_SR_LENGTH GENMASK(19, 9) /* Transfer length */ + +/* Baud-rate counter register (BRCR) */ +#define I2C_BRCR_BRCNT1 GENMASK(31, 16) /* Baud-rate counter 1 */ +#define I2C_BRCR_BRCNT2 GENMASK(15, 0) /* Baud-rate counter 2 */ /* Interrupt mask set/clear (IMSCR) bits */ -#define I2C_IT_TXFE (0x1 << 0) -#define I2C_IT_TXFNE (0x1 << 1) -#define I2C_IT_TXFF (0x1 << 2) -#define I2C_IT_TXFOVR (0x1 << 3) -#define I2C_IT_RXFE (0x1 << 4) -#define I2C_IT_RXFNF (0x1 << 5) -#define I2C_IT_RXFF (0x1 << 6) -#define I2C_IT_RFSR (0x1 << 16) -#define I2C_IT_RFSE (0x1 << 17) -#define I2C_IT_WTSR (0x1 << 18) -#define I2C_IT_MTD (0x1 << 19) -#define I2C_IT_STD (0x1 << 20) -#define I2C_IT_MAL (0x1 << 24) -#define I2C_IT_BERR (0x1 << 25) -#define I2C_IT_MTDWS (0x1 << 28) - -#define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) +#define I2C_IT_TXFE BIT(0) +#define I2C_IT_TXFNE BIT(1) +#define I2C_IT_TXFF BIT(2) +#define I2C_IT_TXFOVR BIT(3) +#define I2C_IT_RXFE BIT(4) +#define I2C_IT_RXFNF BIT(5) +#define I2C_IT_RXFF BIT(6) +#define I2C_IT_RFSR BIT(16) +#define I2C_IT_RFSE BIT(17) +#define I2C_IT_WTSR BIT(18) +#define I2C_IT_MTD BIT(19) +#define I2C_IT_STD BIT(20) +#define I2C_IT_MAL BIT(24) +#define I2C_IT_BERR BIT(25) +#define I2C_IT_MTDWS BIT(28) /* some bits in ICR are reserved */ #define I2C_CLEAR_ALL_INTS 0x131f007f @@ -284,7 +290,7 @@ static int init_hw(struct nmk_i2c_dev *priv) } /* enable peripheral, master mode operation */ -#define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) +#define DEFAULT_I2C_REG_CR (FIELD_PREP(I2C_CR_OM, 0b01) | I2C_CR_PE) /** * load_i2c_mcr_reg() - load the MCR register @@ -296,41 +302,42 @@ static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *priv, u16 flags) u32 mcr = 0; unsigned short slave_adr_3msb_bits; - mcr |= GEN_MASK(priv->cli.slave_adr, I2C_MCR_A7, 1); + mcr |= FIELD_PREP(I2C_MCR_A7, priv->cli.slave_adr); if (unlikely(flags & I2C_M_TEN)) { /* 10-bit address transaction */ - mcr |= GEN_MASK(2, I2C_MCR_AM, 12); + mcr |= FIELD_PREP(I2C_MCR_AM, 2); /* * Get the top 3 bits. * EA10 represents extended address in MCR. This includes * the extension (MSB bits) of the 7 bit address loaded * in A7 */ - slave_adr_3msb_bits = (priv->cli.slave_adr >> 7) & 0x7; + slave_adr_3msb_bits = FIELD_GET(GENMASK(9, 7), + priv->cli.slave_adr); - mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); + mcr |= FIELD_PREP(I2C_MCR_EA10, slave_adr_3msb_bits); } else { /* 7-bit address transaction */ - mcr |= GEN_MASK(1, I2C_MCR_AM, 12); + mcr |= FIELD_PREP(I2C_MCR_AM, 1); } /* start byte procedure not applied */ - mcr |= GEN_MASK(0, I2C_MCR_SB, 11); + mcr |= FIELD_PREP(I2C_MCR_SB, 0); /* check the operation, master read/write? */ if (priv->cli.operation == I2C_WRITE) - mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); + mcr |= FIELD_PREP(I2C_MCR_OP, I2C_WRITE); else - mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); + mcr |= FIELD_PREP(I2C_MCR_OP, I2C_READ); /* stop or repeated start? */ if (priv->stop) - mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); + mcr |= FIELD_PREP(I2C_MCR_STOP, 1); else - mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); + mcr &= ~FIELD_PREP(I2C_MCR_STOP, 1); - mcr |= GEN_MASK(priv->cli.count, I2C_MCR_LENGTH, 15); + mcr |= FIELD_PREP(I2C_MCR_LENGTH, priv->cli.count); return mcr; } @@ -383,7 +390,7 @@ static void setup_i2c_controller(struct nmk_i2c_dev *priv) slsu += 1; dev_dbg(&priv->adev->dev, "calculated SLSU = %04x\n", slsu); - writel(slsu << 16, priv->virtbase + I2C_SCR); + writel(FIELD_PREP(I2C_SCR_SLSU, slsu), priv->virtbase + I2C_SCR); /* * The spec says, in case of std. mode the divider is @@ -399,8 +406,8 @@ static void setup_i2c_controller(struct nmk_i2c_dev *priv) * plus operation. Currently we do not supprt high speed mode * so set brcr1 to 0. */ - brcr1 = 0 << 16; - brcr2 = (i2c_clk / (priv->clk_freq * div)) & 0xffff; + brcr1 = FIELD_PREP(I2C_BRCR_BRCNT1, 0); + brcr2 = FIELD_PREP(I2C_BRCR_BRCNT2, i2c_clk / (priv->clk_freq * div)); /* set the baud rate counter register */ writel((brcr1 | brcr2), priv->virtbase + I2C_BRCR); @@ -414,12 +421,13 @@ static void setup_i2c_controller(struct nmk_i2c_dev *priv) if (priv->sm > I2C_FREQ_MODE_FAST) { dev_err(&priv->adev->dev, "do not support this mode defaulting to std. mode\n"); - brcr2 = i2c_clk / (I2C_MAX_STANDARD_MODE_FREQ * 2) & 0xffff; + brcr2 = FIELD_PREP(I2C_BRCR_BRCNT2, + i2c_clk / (I2C_MAX_STANDARD_MODE_FREQ * 2)); writel((brcr1 | brcr2), priv->virtbase + I2C_BRCR); - writel(I2C_FREQ_MODE_STANDARD << 4, - priv->virtbase + I2C_CR); + writel(FIELD_PREP(I2C_CR_SM, I2C_FREQ_MODE_STANDARD), + priv->virtbase + I2C_CR); } - writel(priv->sm << 4, priv->virtbase + I2C_CR); + writel(FIELD_PREP(I2C_CR_SM, priv->sm), priv->virtbase + I2C_CR); /* set the Tx and Rx FIFO threshold */ writel(priv->tft, priv->virtbase + I2C_TFTR); @@ -583,13 +591,8 @@ static int nmk_i2c_xfer_one(struct nmk_i2c_dev *priv, u16 flags) u32 cause; i2c_sr = readl(priv->virtbase + I2C_SR); - /* - * Check if the controller I2C operation status - * is set to ABORT(11b). - */ - if (((i2c_sr >> 2) & 0x3) == 0x3) { - /* get the abort cause */ - cause = (i2c_sr >> 4) & 0x7; + if (FIELD_GET(I2C_SR_STATUS, i2c_sr) == I2C_ABORT) { + cause = FIELD_GET(I2C_SR_CAUSE, i2c_sr); dev_err(&priv->adev->dev, "%s\n", cause >= ARRAY_SIZE(abort_causes) ? "unknown reason" : @@ -730,7 +733,7 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) misr = readl(priv->virtbase + I2C_MISR); src = __ffs(misr); - switch ((1 << src)) { + switch (BIT(src)) { /* Transmit FIFO nearly empty interrupt */ case I2C_IT_TXFNE: @@ -824,15 +827,16 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) * during the transaction. */ case I2C_IT_BERR: + { + u32 sr = readl(priv->virtbase + I2C_SR); priv->result = -EIO; - /* get the status */ - if (((readl(priv->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) + if (FIELD_GET(I2C_SR_STATUS, sr) == I2C_ABORT) init_hw(priv); i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_BERR); complete(&priv->xfer_complete); - - break; + } + break; /* * Tx FIFO overrun interrupt. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708015958; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6nKfxjjL9YJKMVRbZ9zGHy5EtFlaaVeaCPp72QOiJ54=; b=CTzkAeoFsqhnE2t41G4MU1FRxz/HQTMRdeIrSrPJhfiG3UcATEK9QuOADFWVMGcp42xO6f WFqCh2y/FWJmwopMpMnLU1Ao6zIBLB+SaGpBLHt+TjnGEjDhgWAh4bZRPjlb6GmGQjqJtg jAK9lQEcnliuJKMAv7/BXefpTwjIqpq6oaY7vwUfDEvb8W4G6y8su2hM5Ox6QL5RSIYUFJ ohzrJzPpDRqK40pAulCl1ytBhhG8LjoCombqJtUxuxMLRW1VR8vdU5kuo/XJcl+wjAqK+Z b32OADQNxnNWfFbf5N5yKLICuWyvK66UPUlQVgzMkaqzAfWMYmsAK+ybICjPyQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 15 Feb 2024 17:52:14 +0100 Subject: [PATCH 07/13] i2c: nomadik: support short xfer timeouts using waitqueue & hrtimer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-mbly-i2c-v1-7-19a336e91dca@bootlin.com> References: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> In-Reply-To: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> To: Linus Walleij , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer Cc: linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Gregory Clement , Vladimir Kondratiev , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790984742721253819 X-GMAIL-MSGID: 1790984742721253819 Replace the completion by a waitqueue for synchronization from IRQ handler to task. For short timeouts, use hrtimers, else use timers. Usecase: avoid blocking the I2C bus for too long when an issue occurs. The threshold picked is one jiffy: if timeout is below that, use hrtimers. This threshold is NOT configurable. Implement behavior but do NOT change fetching of timeout. This means the timeout is unchanged (200ms) and the hrtimer case will never trigger. A waitqueue is used because it supports both desired timeout approaches. See wait_event_timeout() and wait_event_hrtimeout(). An atomic boolean serves as synchronization condition. Signed-off-by: Théo Lebrun Reviewed-by: Linus Walleij --- drivers/i2c/busses/i2c-nomadik.c | 70 +++++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 22 deletions(-) diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c index aa68ab402b10..e68b8e0d7919 100644 --- a/drivers/i2c/busses/i2c-nomadik.c +++ b/drivers/i2c/busses/i2c-nomadik.c @@ -162,10 +162,11 @@ struct i2c_nmk_client { * @clk_freq: clock frequency for the operation mode * @tft: Tx FIFO Threshold in bytes * @rft: Rx FIFO Threshold in bytes - * @timeout: Slave response timeout (ms) + * @timeout_usecs: Slave response timeout * @sm: speed mode * @stop: stop condition. - * @xfer_complete: acknowledge completion for a I2C message. + * @xfer_wq: xfer done wait queue. + * @xfer_done: xfer done boolean. * @result: controller propogated result. */ struct nmk_i2c_dev { @@ -179,10 +180,11 @@ struct nmk_i2c_dev { u32 clk_freq; unsigned char tft; unsigned char rft; - int timeout; + int timeout_usecs; enum i2c_freq_mode sm; int stop; - struct completion xfer_complete; + struct wait_queue_head xfer_wq; + bool xfer_done; int result; }; @@ -434,6 +436,22 @@ static void setup_i2c_controller(struct nmk_i2c_dev *priv) writel(priv->rft, priv->virtbase + I2C_RFTR); } +static bool nmk_i2c_wait_xfer_done(struct nmk_i2c_dev *priv) +{ + if (priv->timeout_usecs < jiffies_to_usecs(1)) { + unsigned long timeout_usecs = priv->timeout_usecs; + ktime_t timeout = ktime_set(0, timeout_usecs * NSEC_PER_USEC); + + wait_event_hrtimeout(priv->xfer_wq, priv->xfer_done, timeout); + } else { + unsigned long timeout = usecs_to_jiffies(priv->timeout_usecs); + + wait_event_timeout(priv->xfer_wq, priv->xfer_done, timeout); + } + + return priv->xfer_done; +} + /** * read_i2c() - Read from I2C client device * @priv: private data of I2C Driver @@ -445,9 +463,9 @@ static void setup_i2c_controller(struct nmk_i2c_dev *priv) */ static int read_i2c(struct nmk_i2c_dev *priv, u16 flags) { - int status = 0; u32 mcr, irq_mask; - unsigned long timeout; + int status = 0; + bool xfer_done; mcr = load_i2c_mcr_reg(priv, flags); writel(mcr, priv->virtbase + I2C_MCR); @@ -459,7 +477,8 @@ static int read_i2c(struct nmk_i2c_dev *priv, u16 flags) /* enable the controller */ i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE); - init_completion(&priv->xfer_complete); + init_waitqueue_head(&priv->xfer_wq); + priv->xfer_done = false; /* enable interrupts by setting the mask */ irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | @@ -475,10 +494,9 @@ static int read_i2c(struct nmk_i2c_dev *priv, u16 flags) writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask, priv->virtbase + I2C_IMSCR); - timeout = wait_for_completion_timeout( - &priv->xfer_complete, priv->adap.timeout); + xfer_done = nmk_i2c_wait_xfer_done(priv); - if (timeout == 0) { + if (!xfer_done) { /* Controller timed out */ dev_err(&priv->adev->dev, "read from slave 0x%x timed out\n", priv->cli.slave_adr); @@ -513,9 +531,9 @@ static void fill_tx_fifo(struct nmk_i2c_dev *priv, int no_bytes) */ static int write_i2c(struct nmk_i2c_dev *priv, u16 flags) { - u32 status = 0; u32 mcr, irq_mask; - unsigned long timeout; + u32 status = 0; + bool xfer_done; mcr = load_i2c_mcr_reg(priv, flags); @@ -528,7 +546,8 @@ static int write_i2c(struct nmk_i2c_dev *priv, u16 flags) /* enable the controller */ i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE); - init_completion(&priv->xfer_complete); + init_waitqueue_head(&priv->xfer_wq); + priv->xfer_done = false; /* enable interrupts by settings the masks */ irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); @@ -554,10 +573,9 @@ static int write_i2c(struct nmk_i2c_dev *priv, u16 flags) writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask, priv->virtbase + I2C_IMSCR); - timeout = wait_for_completion_timeout( - &priv->xfer_complete, priv->adap.timeout); + xfer_done = nmk_i2c_wait_xfer_done(priv); - if (timeout == 0) { + if (!xfer_done) { /* Controller timed out */ dev_err(&priv->adev->dev, "write to slave 0x%x timed out\n", priv->cli.slave_adr); @@ -807,7 +825,9 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) priv->cli.count); init_hw(priv); } - complete(&priv->xfer_complete); + priv->xfer_done = true; + wake_up(&priv->xfer_wq); + break; @@ -817,7 +837,9 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) init_hw(priv); i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_MAL); - complete(&priv->xfer_complete); + priv->xfer_done = true; + wake_up(&priv->xfer_wq); + break; @@ -834,7 +856,9 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) init_hw(priv); i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_BERR); - complete(&priv->xfer_complete); + priv->xfer_done = true; + wake_up(&priv->xfer_wq); + } break; @@ -848,7 +872,9 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg) init_hw(priv); dev_err(dev, "Tx Fifo Over run\n"); - complete(&priv->xfer_complete); + priv->xfer_done = true; + wake_up(&priv->xfer_wq); + break; @@ -949,7 +975,7 @@ static void nmk_i2c_of_probe(struct device_node *np, priv->sm = I2C_FREQ_MODE_FAST; priv->tft = 1; /* Tx FIFO threshold */ priv->rft = 8; /* Rx FIFO threshold */ - priv->timeout = 200; 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708015959; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5W2sSL7KXTa75TLd1u49SS6u6N4gKtVqD7M4RKYa2bU=; b=dIxHuc+q76e9Fo3tmpFDzwS3cGp4P0feO83Vi9KUPUUJCSaPlNMCIY0cNUIxKQr0bIc1Sn bXtUYDJs4Y+ZW9cILDmc4atXws9VkQ82t2IxUVlbTKGbdUXLmqZ9M96uzRZk753owpssG6 kAqWRvnh7b9Atpw6YwozbTkGZ3T5i9QZ3QriHJ19lIElgeJwdsey20ZbOp3q4FTsXwpXUB YiJ1gUavaooMS4VFu7kVZAfrPyAB5PDK+pcKQmVsFrUoYeyPlZpcfH+/aWhOUwJOn3eLwW ZeZVhbkdNQr2PLYoWVTJjMIVw0A5yDRWukutqJHs+QbSWnSRZBmlsOT7eVQICw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 15 Feb 2024 17:52:15 +0100 Subject: [PATCH 08/13] i2c: nomadik: replace jiffies by ktime for FIFO flushing timeout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-mbly-i2c-v1-8-19a336e91dca@bootlin.com> References: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> In-Reply-To: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> To: Linus Walleij , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer Cc: linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Gregory Clement , Vladimir Kondratiev , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790984838847983335 X-GMAIL-MSGID: 1790984838847983335 The FIFO flush function uses a jiffies amount to detect timeouts as the flushing is async. Replace with ktime to get more accurate precision and support short timeouts. Signed-off-by: Théo Lebrun Reviewed-by: Linus Walleij --- drivers/i2c/busses/i2c-nomadik.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c index e68b8e0d7919..afd54999bbbb 100644 --- a/drivers/i2c/busses/i2c-nomadik.c +++ b/drivers/i2c/busses/i2c-nomadik.c @@ -219,8 +219,8 @@ static inline void i2c_clr_bit(void __iomem *reg, u32 mask) static int flush_i2c_fifo(struct nmk_i2c_dev *priv) { #define LOOP_ATTEMPTS 10 + ktime_t timeout; int i; - unsigned long timeout; /* * flush the transmit and receive FIFO. The flushing @@ -232,9 +232,9 @@ static int flush_i2c_fifo(struct nmk_i2c_dev *priv) writel((I2C_CR_FTX | I2C_CR_FRX), priv->virtbase + I2C_CR); for (i = 0; i < LOOP_ATTEMPTS; i++) { - timeout = jiffies + priv->adap.timeout; + timeout = ktime_add_us(ktime_get(), priv->timeout_usecs); - while (!time_after(jiffies, timeout)) { + while (ktime_after(timeout, ktime_get())) { if ((readl(priv->virtbase + I2C_CR) & (I2C_CR_FTX | I2C_CR_FRX)) == 0) return 0; From patchwork Thu Feb 15 16:52:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 201672 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp3580dyb; Thu, 15 Feb 2024 09:34:47 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUOQagCezB8YvbPiujxHSToHBuroodsdL7XpT/n5SaFv6fqHmkD8mePBeFh+qK/qrmzJI3hde4RpYKg33w2ym5dNqNMGA== X-Google-Smtp-Source: AGHT+IHvi1oE22j85IKkDPrDo6uqjoJFGil1mag67Gmflp+ORqOJT/BqLo8zgGuW/pIZCJK4ZoNo X-Received: by 2002:a17:902:d48e:b0:1db:403c:68b5 with SMTP id c14-20020a170902d48e00b001db403c68b5mr2665479plg.12.1708018487648; Thu, 15 Feb 2024 09:34:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708018487; cv=pass; d=google.com; s=arc-20160816; b=Z2vWrxHi7wFhQFdOgTzR8jnCe/9YOq9RCGm+clJBj3uXLgDNznCD5rj+GwiJk0baIl VRS1D2WwFCSHr1INArt5XJoiw/uBDj7Zhc3GpaNy+QcN73OG0ioyFVXBUzcSdM9K7AAN soRfeVvgwZ4dWOd1bYfoNXbq4EGGtohp0yndj82Z2iVEfWxOzpR13PtVNqYLUk1ix/hS IOZnHcBD6R6oY8fZ1FPlutVv9C88ZEl68xgxn8csm1xvicqvIEF6UG1NoVx8E0Af3m1f WnaCgwNcDtOrqTbuarAT+XO5AGyH9TwDSOqpETwdgBOGFKBSxKEks3Kuoyh6XZ/cY+uw jpXA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=UI781RDrcik2RYtu08sBCE4vst1s92iXfDeWJ+Uj5KU=; fh=5JSnMO1qLgeVtLVJilSQcFnAcZn2MWLSM3RnsAdOnEU=; b=zmb5UwoQhbAhkOMV8qCtfEWcQhkBgfllUsgnER0XhuDH1qU/X8BXumEBakSEYAjZOR pCGAxm7H6zStbnDEYnm9pGN0CzsI/ifcthIFqvI1nMpwahlqonTIEYnRDaMzpTqyddb1 I7PbVA0rj+bBdpd4ek1E7G/2HWpM8+vCyvIluKnTutTG7XecQYbpgp1nliyHdGQQP0a7 Q58ttxCrMn/Bn1cbjOa9ZZw0KVK8iq93S5X26SRy7eufoNvmsYAtpgExIGMDF5fyyLpr B6xgxEKTjEAYw3H7uOu0vsBxsWKFBb3IR05QjB2SOTG4bN65jesCeG+1vDSkiw0iB4+P Rd5Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=X05Jz2dA; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-67341-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-67341-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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The i2c_adapter->timeout field is an unaccurate jiffies amount; i2c-nomadik uses hrtimers for timeouts below one jiffy. Signed-off-by: Théo Lebrun Reviewed-by: Linus Walleij --- drivers/i2c/busses/i2c-nomadik.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c index afd54999bbbb..23e12c570457 100644 --- a/drivers/i2c/busses/i2c-nomadik.c +++ b/drivers/i2c/busses/i2c-nomadik.c @@ -964,6 +964,8 @@ static const struct i2c_algorithm nmk_i2c_algo = { static void nmk_i2c_of_probe(struct device_node *np, struct nmk_i2c_dev *priv) { + u32 timeout_usecs; + /* Default to 100 kHz if no frequency is given in the node */ if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq)) priv->clk_freq = I2C_MAX_STANDARD_MODE_FREQ; @@ -975,7 +977,12 @@ static void nmk_i2c_of_probe(struct device_node *np, priv->sm = I2C_FREQ_MODE_FAST; priv->tft = 1; /* Tx FIFO threshold */ priv->rft = 8; /* Rx FIFO threshold */ - priv->timeout_usecs = 200 * USEC_PER_MSEC; /* Slave response timeout */ + + /* Slave response timeout */ + if (!of_property_read_u32(np, "timeout-usecs", &timeout_usecs)) + priv->timeout_usecs = timeout_usecs; + else + priv->timeout_usecs = 200 * USEC_PER_MSEC; } static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) From patchwork Thu Feb 15 16:52:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 201651 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp532141dyb; Thu, 15 Feb 2024 08:56:12 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXxG0prH/lUNxY/fwowK6v9VU7C/f9wb3N/5hgoWQBsmmqknluRAiMLq9UkIluqdmpmutZYAmbo8BIsgZbvDLBoWf16PQ== X-Google-Smtp-Source: AGHT+IGEO/+OWEj0kymzdy/kaIyOOCOShTKSGs6brgnEybQx1yuOy2outTReuXGUnmW1wNhuuvBL X-Received: by 2002:a05:622a:194:b0:42c:67f9:4cff with SMTP id s20-20020a05622a019400b0042c67f94cffmr2915468qtw.48.1708016171964; Thu, 15 Feb 2024 08:56:11 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708016171; cv=pass; d=google.com; s=arc-20160816; b=EmGs1oHXe6KPgUsIYr6VL+iDxG+y3Y3TYPBct2nTjiN6Nw+2vCcBgdqlowSR+qAHZe eTzUsUlNT18LuOf5HmEOpvGA55WPAFtQlwHmptcvhfFVV+U4/Bf7Ie3LiiSUEXCaBUhI v97U8CbvOQ9nMHcmYX1deTNiuE/xQWO3tVHqwJPC4xmBlFRnAFKY7Vd58TL0fTmQCo6J 5m1vbOUckUS8qAwJmy6fEovMN2E43iL3mOjVgbeZKIhAI0IjZCDzVar4LdZ5P+R7QDVM Miyujj+7oA0pl3hEwWI7o7y/AuVSvlzDQsdgiYR4cAoN8vwiSEWNvfc8c6ap06cX3kwe GtlQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=ksC5z+uQT8JX7fjtCfLqhFUJQnwzz+zL0ZliTFb1W/U=; fh=5JSnMO1qLgeVtLVJilSQcFnAcZn2MWLSM3RnsAdOnEU=; b=A9we6TudYc7schyqcbyHOs4PEqr2jnRaRLaZaom8YeXFkMpzO/3Fhx3Yb6+KHUEvDn Gpt/Qv7DYrrEXZNKwQUvBWbhXcxBO/tbrvCswSbELWYoQaQbCHVInqwapiwxkfFtbgqc VfSymZFgjICN/o0zZmHQvHNFjLnWhmgR20+6Al3JNxywNOjUgH8d9zvSMzexerVcG2im IrjvY1XawFWxSTBOpT7Fxp1EH95fH8HQ0DFNSThHunul0XhfxV4j70janmSe1D9RJ+ue A2gD8YxSwvg+JyVkgtgmB0SSFHwbI4N8KiofgxTt1j05ZltNjXE682oq/DaMR7uik8Ul wSVQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=lBMzkyOp; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-67342-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-67342-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708015960; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ksC5z+uQT8JX7fjtCfLqhFUJQnwzz+zL0ZliTFb1W/U=; b=lBMzkyOpDFvlhrVZrgierYbgIjaKk8uYd4Mg6POWHhf/fvmgCtVRID1T9hvMb8s+IAHMmY xDAgXA/XlkTZBq4VP1D5awK7LcvdC74dpMM5d+Bc2udUBfbHgXecGw3n0MPBaMWfQ7Mmbu NQvVrWFckor5TXHzty4x2nQOI4RKQ0umi1KuE2MF/xA+Qo/oXbEvxoC2RvpLjFOHpGZ+8e +UrKiwSg46JtzA7H8LsgtYqpGRdSCRjM2gpz+jcKEzZjzLBQth4DuO/5U4kTUIXVfdXv1C 123wEjBROkK8w7ya6cAIHPD14OqCB1lqq6+nQYyYCb/pc4QwHYoh62wKaXKr3g== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 15 Feb 2024 17:52:17 +0100 Subject: [PATCH 10/13] i2c: nomadik: support Mobileye EyeQ5 I2C controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-mbly-i2c-v1-10-19a336e91dca@bootlin.com> References: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> In-Reply-To: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> To: Linus Walleij , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer Cc: linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Gregory Clement , Vladimir Kondratiev , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790984765427026854 X-GMAIL-MSGID: 1790984765427026854 Add compatible for the integration of the same DB8500 IP block into the Mobileye EyeQ5 platform. Two quirks are present: - The memory bus only supports 32-bit accesses. One writeb() is done to fill the Tx FIFO which we replace with a writel(). - A register must be configured for the I2C speed mode; it is located in a shared register region called OLB. We access that memory region using a syscon & regmap that gets passed as a phandle (mobileye,olb). A two-bit enum per controller is written into the register; that requires us to know the global index of the I2C controller (mobileye,id). We add #include and and sort headers. Signed-off-by: Théo Lebrun --- drivers/i2c/busses/i2c-nomadik.c | 79 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 71 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c index 23e12c570457..eb076419dfa8 100644 --- a/drivers/i2c/busses/i2c-nomadik.c +++ b/drivers/i2c/busses/i2c-nomadik.c @@ -6,22 +6,30 @@ * I2C master mode controller driver, used in Nomadik 8815 * and Ux500 platforms. * + * The Mobileye EyeQ5 platform is also supported; it uses + * the same Ux500/DB8500 IP block with two quirks: + * - The memory bus only supports 32-bit accesses. + * - A register must be configured for the I2C speed mode; + * it is located in a shared register region called OLB. + * * Author: Srinidhi Kasagar * Author: Sachin Verma */ +#include #include +#include +#include +#include #include -#include -#include -#include #include -#include -#include -#include #include -#include +#include +#include #include #include +#include +#include +#include #define DRIVER_NAME "nmk-i2c" @@ -110,6 +118,10 @@ enum i2c_freq_mode { I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */ }; +/* Mobileye EyeQ5 offset into a shared register region (called OLB) */ +#define NMK_I2C_EYEQ5_OLB_IOCR2 0x0B8 +#define NMK_I2C_EYEQ5_OLB_IOCR2_SHIFT(id) (4 + 2 * (id)) + /** * struct i2c_vendor_data - per-vendor variations * @has_mtdws: variant has the MTDWS bit @@ -168,6 +180,7 @@ struct i2c_nmk_client { * @xfer_wq: xfer done wait queue. * @xfer_done: xfer done boolean. * @result: controller propogated result. + * @has_32b_bus: controller is on a bus that only supports 32-bit accesses. */ struct nmk_i2c_dev { struct i2c_vendor_data *vendor; @@ -186,6 +199,7 @@ struct nmk_i2c_dev { struct wait_queue_head xfer_wq; bool xfer_done; int result; + bool has_32b_bus; }; /* controller's abort causes */ @@ -514,7 +528,10 @@ static void fill_tx_fifo(struct nmk_i2c_dev *priv, int no_bytes) (priv->cli.count != 0); count--) { /* write to the Tx FIFO */ - writeb(*priv->cli.buffer, priv->virtbase + I2C_TFR); + if (priv->has_32b_bus) + writel(*priv->cli.buffer, priv->virtbase + I2C_TFR); + else + writeb(*priv->cli.buffer, priv->virtbase + I2C_TFR); priv->cli.buffer++; priv->cli.count--; priv->cli.xfer_bytes++; @@ -985,6 +1002,43 @@ static void nmk_i2c_of_probe(struct device_node *np, priv->timeout_usecs = 200 * USEC_PER_MSEC; } +static int nmk_i2c_eyeq5_probe(struct nmk_i2c_dev *priv) +{ + struct device *dev = &priv->adev->dev; + struct device_node *np = dev->of_node; + unsigned int shift, speed_mode; + struct regmap *olb; + int ret; + u32 id; + + priv->has_32b_bus = true; + + olb = syscon_regmap_lookup_by_phandle(np, "mobileye,olb"); + if (IS_ERR_OR_NULL(olb)) { + if (!olb) + olb = ERR_PTR(-ENOENT); + return dev_err_probe(dev, PTR_ERR(olb), + "failed OLB lookup: %lu\n", PTR_ERR(olb)); + } + + ret = of_property_read_u32(np, "mobileye,id", &id); + if (ret) + return dev_err_probe(dev, ret, "failed ID lookup: %d\n", ret); + + if (priv->clk_freq <= 400000) + speed_mode = 0b00; + else if (priv->clk_freq <= 1000000) + speed_mode = 0b01; + else + speed_mode = 0b10; + + shift = NMK_I2C_EYEQ5_OLB_IOCR2_SHIFT(id); + regmap_update_bits(olb, NMK_I2C_EYEQ5_OLB_IOCR2, + 0b11 << shift, speed_mode << shift); + + return 0; +} + static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) { int ret = 0; @@ -1001,8 +1055,17 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) priv->vendor = vendor; priv->adev = adev; + priv->has_32b_bus = false; nmk_i2c_of_probe(np, priv); + if (of_device_is_compatible(np, "mobileye,eyeq5-i2c")) { + ret = nmk_i2c_eyeq5_probe(priv); + if (ret) { + dev_info(dev, "%s: %d: %d\n", __func__, __LINE__, ret); + return ret; + } + } + if (priv->tft > max_fifo_threshold) { dev_warn(dev, "requested TX FIFO threshold %u, adjusted down to %u\n", priv->tft, max_fifo_threshold); From patchwork Thu Feb 15 16:52:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 201654 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp532590dyb; Thu, 15 Feb 2024 08:57:06 -0800 (PST) X-Forwarded-Encrypted: i=3; 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Use a default bus frequency of 400kHz. They are AMBA devices that are matched on PeriphID. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 70 ++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 8d4f65ec912d..d27e164f0fc1 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -70,6 +70,76 @@ soc: soc { ranges; compatible = "simple-bus"; + i2c0: i2c@300000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0 0x300000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clock-frequency = <400000>; /* Fast mode */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c_ser_clk>, <&i2c_clk>; + clock-names = "i2cclk", "apb_pclk"; + mobileye,olb = <&olb>; + mobileye,id = <0>; + }; + + i2c1: i2c@400000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0 0x400000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clock-frequency = <400000>; /* Fast mode */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c_ser_clk>, <&i2c_clk>; + clock-names = "i2cclk", "apb_pclk"; + mobileye,olb = <&olb>; + mobileye,id = <1>; + }; + + i2c2: i2c@500000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0 0x500000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clock-frequency = <400000>; /* Fast mode */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c_ser_clk>, <&i2c_clk>; + clock-names = "i2cclk", "apb_pclk"; + mobileye,olb = <&olb>; + mobileye,id = <2>; + }; + + i2c3: i2c@600000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0 0x600000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clock-frequency = <400000>; /* Fast mode */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c_ser_clk>, <&i2c_clk>; + clock-names = "i2cclk", "apb_pclk"; + mobileye,olb = <&olb>; + mobileye,id = <3>; + }; + + i2c4: i2c@700000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0 0x700000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clock-frequency = <400000>; /* Fast mode */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c_ser_clk>, <&i2c_clk>; + clock-names = "i2cclk", "apb_pclk"; + mobileye,olb = <&olb>; + mobileye,id = <4>; + }; + uart0: serial@800000 { compatible = "arm,pl011", "arm,primecell"; reg = <0 0x800000 0x0 0x1000>; From patchwork Thu Feb 15 16:52:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 201652 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp532151dyb; Thu, 15 Feb 2024 08:56:13 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVPLlksno5Gz94iZfLoS2g10IkOKUobtPT2kHjMfyBelYj5btY8NI0S8eca5aOB3/RLe/tUPFyeEul2gAfbMYXpYhkA2A== X-Google-Smtp-Source: AGHT+IGSKvooF1oHbqy8D0fYC/wIfy7g7i7icnOsvbQ6Uzjchk2NkjmnvppP9nP3sejB0JKvubgD X-Received: by 2002:a05:620a:a17:b0:787:389c:fc36 with SMTP id i23-20020a05620a0a1700b00787389cfc36mr1621916qka.8.1708016172849; Thu, 15 Feb 2024 08:56:12 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708016172; cv=pass; d=google.com; s=arc-20160816; b=mm3WNpZI6RQpUfLsvSs/GM2c+faPjw4HRlXL9enNK9OF4eiEKPvuDhYBjNrdgdk1cV qbTbVbCzsRX9Fkk640tvMamSPbkR7O0YPCLsuxjMDZoBF74XrbdRNFxPyh6JGoxfV2zt IWpk/zkktkAAQiaksTJryfsgOleoivHAVIMlNDMEWB6cOq2UcFbb6nTbdmS3DpOXTpS1 vheRnEWisE4CcCNMKDfpchoCyxYdZoyeQO46q9cqVIGVh/RR/FTsNxN34jkvSOvI+/Jl qGPELc7tUdSAFdKKdgl61n76O3mhofhJUb8yd2eKq8PLZVVhg2+xtlZd4gMwmqpKzgOJ 7nMg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=6EzCLVk/9qpcEHez24XKqzeEBqgcss734Jz91cHBP7g=; fh=5JSnMO1qLgeVtLVJilSQcFnAcZn2MWLSM3RnsAdOnEU=; b=SSdF8InVxYlDfWQfLhjrDOPuApjb2b1l9IbA2Ecr3LlWJofgBc3SttmBoJwukmqk5h 63C+r5EmSqCshyARNTXBqKj96TaufAC6gh6qrwphpICy4nBZcHC2CGIjrEk+80JPmonA v+G5O/OnRX0fFDvL2H1IiJ4YeTocthp66M67Ix/jkqdLwHLkAM6sUPetG87ClkvYt0v2 BQsbWgb3+4Wkq77bwZcU0xh84b/NH4W50BfV9n/9v5inFww8koCdTpTSqdsxWZqgCrxO 573YzQItf8i6lBidIOsxVqJIuDo7frMiXUQ37JZraz9r9Wb+IL/AvCkxF5T+p2BvoFhB sM+w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=can24Pun; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-67344-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-67344-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Its label is the schematics identifier. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts index 6898b2d8267d..1f8549acd40d 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts +++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts @@ -21,3 +21,11 @@ memory@0 { <0x8 0x02000000 0x0 0x7E000000>; }; }; + +&i2c2 { + tmp112@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + label = "U60"; + }; +}; From patchwork Thu Feb 15 16:52:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 201673 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:c619:b0:108:e6aa:91d0 with SMTP id hn25csp4487dyb; Thu, 15 Feb 2024 09:36:28 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXtasK7QViTZ+P1Q0uuKOR5U+99MUPFPV46O3FiuxBaoWAtMSVyoMYaPpF96PGBsfB/kjkUq+ABkT7QAl4jpQlGR4pqYQ== X-Google-Smtp-Source: AGHT+IG5FeedMzj6pEEjq1p6YXTFJT5AHYVI7rt2DZHJ2YsSgCSVnXhJku6jSgvCh+/+y/mdKthS X-Received: by 2002:a17:902:c408:b0:1d9:7039:3519 with SMTP id k8-20020a170902c40800b001d970393519mr2381989plk.2.1708018588810; Thu, 15 Feb 2024 09:36:28 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708018588; cv=pass; d=google.com; s=arc-20160816; b=eM0unt6xzsY/FaWSW+fqQ0H7YtAv8JyvoXOvjCwDIo5IPQOln3TfJ8GMwG0kWCxTy5 MneRRDwezezqgzrW/Y5ly6dV1R7QLceODJZRic62BQ+FaaWT4DD5mq+OuNtYG4GyHqlv P81H86T5QaCOyjrso91Rbw89F+P+OFVaVbzCiGTbNVXUvcynQb+/vlYF3PcGxK5W8VVr wJ7Ms2pnjD9luV53Oa4vJ1mOf4MB4zAmS6mXFq3+sbzMEOCGpYRoyXWkjN3C2KjXUu3h LCrQg187TIt5SfCMpY885G2fzh1xLMpwTGq2m2stKTm+At/3HJdDTpOd8CvCc7ynGeMz 8GjA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=GiFCwkZp1j+zGkHFn7RNrGArILflr3YrUZ1AXzVuNHk=; fh=5JSnMO1qLgeVtLVJilSQcFnAcZn2MWLSM3RnsAdOnEU=; b=sUBU66layJfPBMDBDMFkVE3LKJts+WUBEksc4SiIUXySM/nvYbjYaP23A83Aj/uil+ e1G+XMXW7D3npPRQ6XXF70LUCZ8u8FfA4O2Uh0k9lrXrygy5mbcfAaYTgU/GERiaYnE6 t1Z+CIzjxqOdVViVqmI4p+g9V1FE6uac285gD0tC+vcts0iyQRvcSLDJaqscTgt0wDQF 1D2pVlHeg6qvR1ttZRkbBOk28rpSrEm4f/1J/GJ2k1AQxW1pmp0RtK8Hjs2o8z2b/BuO GjUXnaPZsbG1UrgY2KogT83+Wi2OSVupdWoqmQQp0YUIpuN4XE8LZyBIptT6rDnwOuhq VjOg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=Puy0rwxW; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-67345-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-67345-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [147.75.48.161]) by mx.google.com with ESMTPS id u1-20020a170902e5c100b001d9004b68f2si1488528plf.239.2024.02.15.09.36.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 09:36:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-67345-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=Puy0rwxW; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-67345-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-67345-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id F10ACB26FBF for ; Thu, 15 Feb 2024 16:56:37 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7064B13B7AA; Thu, 15 Feb 2024 16:52:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Puy0rwxW" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6710F13A245; Thu, 15 Feb 2024 16:52:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708015966; cv=none; b=PCwmYLHbQRdjLo2pIL7TV3NIueQI0MmZgCsEJ/8uHHkFr63/hJXDyAWOmqOXUbJ7V8PBXgaEsMQCmykcZv5s7jjzHIt1/MSSXq+mc8+W5spREaZZlYraoY/8POXj3a9M0mLaKiETH9yVJhVdEZnmweq2WCpp6SJH/dktrKwWlAc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708015966; c=relaxed/simple; bh=UvJih+xma5Rq5UrC8pGOHSo+fikaNT91p0IHc5YM7jc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fOyVhhTZemAXwFId7x/eLtHh+6PVhrL/7vIi8mC0NmyuYJTJ2ZMuz/e77+0iTgzVD1rDPd+4XdlNRUZJa5LNCMQ9uOxmuECvh8B9hKx/Bicbdi+j1u4Za25YKJ2hRUS24t7eFQv7LMW9h6AGL+Qu3mcBMGceYlFlrxI/YtFKixA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Puy0rwxW; arc=none smtp.client-ip=217.70.183.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id EA1E9E0015; Thu, 15 Feb 2024 16:52:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708015962; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GiFCwkZp1j+zGkHFn7RNrGArILflr3YrUZ1AXzVuNHk=; b=Puy0rwxWjmDTOBKb2sbGV5fyIc7/74RRKyfDEgEOtMZjdNSJQ2WyY1gl1DXzAwex5mPdl3 QacCUNY23/JCxMcdT2UXKpoTV4B8dO9OsLu+CnNdAiOvBF8bqodVIf9f+1wIvDh+oZr/Lb 3PVbqKj8FyTFPRN0sQW1MqBc443CBD8wy3gnce+N+g7kWWOvnUS5KVIUG+Cvmt7Dpp5Amk pOlISBbrivjhkjen8z7ieN07ncee27jTekI5xQSkYvkQlFXtF30ObTZnKhnqS/HlJ0UL2D tYa1JOjSwvUj2FaPQKG0S2AMA1PSTK5JPxcI/BjXz7G1oyYuTy0sF+km1tvdwA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Thu, 15 Feb 2024 17:52:20 +0100 Subject: [PATCH 13/13] MIPS: mobileye: eyeq5: add resets to I2C controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-mbly-i2c-v1-13-19a336e91dca@bootlin.com> References: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> In-Reply-To: <20240215-mbly-i2c-v1-0-19a336e91dca@bootlin.com> To: Linus Walleij , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer Cc: linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Gregory Clement , Vladimir Kondratiev , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790987299870984629 X-GMAIL-MSGID: 1790987299870984629 Add resets properties to each I2C controller. This depends on the reset-eyeq5 platform reset controller driver. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index d27e164f0fc1..c0842836fcc8 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -80,6 +80,7 @@ i2c0: i2c@300000 { #size-cells = <0>; clocks = <&i2c_ser_clk>, <&i2c_clk>; clock-names = "i2cclk", "apb_pclk"; + resets = <&reset 0 13>; mobileye,olb = <&olb>; mobileye,id = <0>; }; @@ -94,6 +95,7 @@ i2c1: i2c@400000 { #size-cells = <0>; clocks = <&i2c_ser_clk>, <&i2c_clk>; clock-names = "i2cclk", "apb_pclk"; + resets = <&reset 0 14>; mobileye,olb = <&olb>; mobileye,id = <1>; }; @@ -108,6 +110,7 @@ i2c2: i2c@500000 { #size-cells = <0>; clocks = <&i2c_ser_clk>, <&i2c_clk>; clock-names = "i2cclk", "apb_pclk"; + resets = <&reset 0 15>; mobileye,olb = <&olb>; mobileye,id = <2>; }; @@ -122,6 +125,7 @@ i2c3: i2c@600000 { #size-cells = <0>; clocks = <&i2c_ser_clk>, <&i2c_clk>; clock-names = "i2cclk", "apb_pclk"; + resets = <&reset 0 16>; mobileye,olb = <&olb>; mobileye,id = <3>; }; @@ -136,6 +140,7 @@ i2c4: i2c@700000 { #size-cells = <0>; clocks = <&i2c_ser_clk>, <&i2c_clk>; clock-names = "i2cclk", "apb_pclk"; + resets = <&reset 0 17>; mobileye,olb = <&olb>; mobileye,id = <4>; };