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Thu, 15 Feb 2024 15:58:28 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:28 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 01/14] s390: Lower severity of assembler syntax errors from fatal to error Date: Thu, 15 Feb 2024 16:58:08 +0100 Message-Id: <20240215155821.4065623-2-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: BLREV9FBOYg7Rk-xABLZh17BPzA2nAsi X-Proofpoint-ORIG-GUID: BLREV9FBOYg7Rk-xABLZh17BPzA2nAsi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 spamscore=0 mlxlogscore=396 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981261970572404 X-GMAIL-MSGID: 1790981261970572404 Report s390 assembler syntax errors as error instead of fatal error. This allows the assembler to continue and potentially report further syntax errors in the source. This should not cause syntax errors to be erroneously accepted, as both error and fatal error cause the assembler to return with a non-zero return code. The following syntax errors are changed from fatal to error: - invalid length field specified - odd numbered general purpose register specified as register pair - invalid floating point register pair. Valid fp register pair operands are 0, 1, 4, 5, 8, 9, 12 or 13. gas/ * config/tc-s390.c: Lower severity of assembler syntax errors from fatal to error. * testsuite/gas/s390/zarch-z9-109-err.l: Likewise. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/config/tc-s390.c | 12 ++++++------ gas/testsuite/gas/s390/zarch-z9-109-err.l | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 09a903aea2db..1b7935a848d0 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -1346,7 +1346,7 @@ md_gather_operands (char *str, { if ((operand->flags & S390_OPERAND_LENGTH) && ex.X_op != O_constant) - as_fatal (_("invalid length field specified")); + as_bad (_("invalid length field specified")); if ((operand->flags & S390_OPERAND_INDEX) && ex.X_add_number == 0 && warn_areg_zero) @@ -1358,17 +1358,17 @@ md_gather_operands (char *str, if ((operand->flags & S390_OPERAND_GPR) && (operand->flags & S390_OPERAND_REG_PAIR) && (ex.X_add_number & 1)) - as_fatal (_("odd numbered general purpose register specified as " - "register pair")); + as_bad (_("odd numbered general purpose register specified as " + "register pair")); if ((operand->flags & S390_OPERAND_FPR) && (operand->flags & S390_OPERAND_REG_PAIR) && ex.X_add_number != 0 && ex.X_add_number != 1 && ex.X_add_number != 4 && ex.X_add_number != 5 && ex.X_add_number != 8 && ex.X_add_number != 9 && ex.X_add_number != 12 && ex.X_add_number != 13) - as_fatal (_("invalid floating point register pair. Valid fp " - "register pair operands are 0, 1, 4, 5, 8, 9, " - "12 or 13.")); + as_bad (_("invalid floating point register pair. Valid fp " + "register pair operands are 0, 1, 4, 5, 8, 9, " + "12 or 13.")); s390_insert_operand (insn, operand, ex.X_add_number, NULL, 0); } } diff --git a/gas/testsuite/gas/s390/zarch-z9-109-err.l b/gas/testsuite/gas/s390/zarch-z9-109-err.l index 1b06f93441a0..84d294de960a 100644 --- a/gas/testsuite/gas/s390/zarch-z9-109-err.l +++ b/gas/testsuite/gas/s390/zarch-z9-109-err.l @@ -1,2 +1,2 @@ .*: Assembler messages: -.*:3: Fatal error: odd numbered general purpose register specified as register pair +.*:3: Error: odd numbered general purpose register specified as register pair From patchwork Thu Feb 15 15:58:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 201596 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp494486dyb; Thu, 15 Feb 2024 07:58:47 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWekLSGlr0jn9RgdVBjtZpx9PvidujciKhjhiu4DpI+b9W/ZbVuO85fwXIOquNOqVZSe1ZPnpHZ6crVctZScYM8xxjFEg== X-Google-Smtp-Source: AGHT+IGPGXMv7XlA/07gOpPvSnXHLzv7PAHf34OwbWo3D5ou+tzSmmWN3ZMIFR3ktQQEmVd7amP7 X-Received: by 2002:a0d:eb12:0:b0:5ff:956d:8b7f with SMTP id u18-20020a0deb12000000b005ff956d8b7fmr2382782ywe.10.1708012727188; Thu, 15 Feb 2024 07:58:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708012727; cv=pass; d=google.com; s=arc-20160816; b=m4KWxR3KYYF7gYV64WgmEG4Wq2yR+NqQ5OJhH8AoWtHB6+MZieFmRi+2p4424hOQgv bw7if7Fqe/5uk9UxlDQbPfMku9/81MZUsmpTrak5ACm3CG3fZUJIuQfih3/pVa0LZ5UH F5pclrUbosLcJU7kZJ4ZCtbT8QrThT93gkG5b2hbg7Gclid0pVwED77dkJO8kIqH3H6b nR9pkDoN9EJ9UE6u73y279/ww/WHE63TcnMEwa/QLyc0/lsyOXRwcFtYFRJ/eQUK/bBW ZaHraEPr4j4XYu80BEAE9cw71auERLlLE0HBc/qCYeuv5uA1aBRVNEe94z827/r5LSwn yA4Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=t29p69KQvmUf/Q7aoDfolskMbsCvwAKRjaZTpY76bUA=; fh=6sWHPsCQUoLz5ZcbqIohOjwdU7jjRT/citiAJwaEf0c=; b=HNWo21j1oijhcLf3Q2CjbWKhjTNT4qmlAdbqhgC4Y9VEpA27VRN80OzGiccYkxGBWL o/q+eLgwx/j+O+kcoLgWOY3QjaYAuE3h2VtzD7VXLPB4/XZUdVP+xYOsT68hd6Mf/ZDs P28AT+v8bhP1jU7Gt05WzKV4lWp9dC6EpzwijRxH3jN4phb5/yxg2N+FZbC5emQtPRyR Z0Ukh5KSS6GWq7fI/b+HXDURAS2LpY/Uub/H27P/zgJX7vG87fD4CcgrKTNaxWdxo6R6 wDfWkSvFvOZkwjsHA+blj/QVxBRV1qGLkw0c/WTKb/riLH4ibAHbUGOUjuqdWgQid3Mp b5aQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b="ePqv/KKz"; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. 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Thu, 15 Feb 2024 15:58:28 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:28 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 02/14] s390: Enhance handling of syntax errors in assembler Date: Thu, 15 Feb 2024 16:58:09 +0100 Message-Id: <20240215155821.4065623-3-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: XcdEt99SUqj4h6gzgvtq78xpdMrT5d4T X-Proofpoint-GUID: XcdEt99SUqj4h6gzgvtq78xpdMrT5d4T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 bulkscore=0 clxscore=1011 phishscore=0 priorityscore=1501 mlxlogscore=758 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981153096112737 X-GMAIL-MSGID: 1790981153096112737 Do not consume any unexpected character including newline ('\n') when detecting a syntax error when parsing an operand block with parenthesis. This resolves the unfavorable assembler messages from the example below, including consuming the newline at the end of the current statement and reporting the next statement as junk. While at it change the only pre-increment of the current instruction string pointer into a post-increment to align with the other instances. Example assembler source: mvi 16(),32 # syntax error a %r1,16(%r2 # syntax error a %r1,16(%r2) mvc 16(1,),32(%r2) # syntax error mvc 16(1,%r1,32(%r2 # syntax error Assembler messages without commit: 1: Error: bad expression 1: Error: syntax error; missing ')' after base register 1: Error: syntax error; expected ',' 1: Error: junk at end of line: `32' 2: Error: syntax error; missing ')' after base register 2: Error: junk at end of line: `a %r1,16(%r2)' 4: Error: bad expression 4: Error: syntax error; missing ')' after base register 4: Error: syntax error; expected ',' 4: Error: operand out of range (32 is not between 0 and 15) 4: Error: syntax error; missing ')' after base register 4: Error: junk at end of line: `%r2)' 5: Error: syntax error; missing ')' after base register 5: Error: syntax error; expected ',' 5: Error: operand out of range (32 is not between 0 and 15) 5: Error: syntax error; missing ')' after base register 5: Error: junk at end of line: `%r2' Assembler messages with commit: 1: Error: bad expression 1: Error: syntax error; missing ')' after base register 2: Error: syntax error; missing ')' after base register 4: Error: bad expression 4: Error: syntax error; missing ')' after base register 5: Error: syntax error; missing ')' after base register 5: Error: syntax error; missing ')' after base register gas/ * config/tc-s390.c: Do not erroneously consume newline when parsing an addressing operand with parentheses. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/config/tc-s390.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 1b7935a848d0..019f26b2f4ab 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -1526,8 +1526,10 @@ md_gather_operands (char *str, else if (operand->flags & S390_OPERAND_BASE) { /* After the base register the parenthesised block ends. */ - if (*str++ != ')') + if (*str != ')') as_bad (_("syntax error; missing ')' after base register")); + else + str++; skip_optional = 0; if (*str == '\0' && skip_optargs_p (opcode->flags, &opindex_ptr[1])) @@ -1584,7 +1586,7 @@ md_gather_operands (char *str, } while (ISSPACE (*str)) - ++str; + str++; /* Check for tls instruction marker. */ reloc = s390_tls_suffix (&str, &ex); From patchwork Thu Feb 15 15:58:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 201597 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp494491dyb; Thu, 15 Feb 2024 07:58:48 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVVaqxwwXYsCU3M3ClX2RSKjJ0StvfUXyNrwVilGbsWjgLGz3g3LJNGduIISbUqMUwDkCtixA7YrnOmTf3DJs1IdMf3yQ== X-Google-Smtp-Source: AGHT+IHyARA1V/P21vsbtDwcWGuESxfVY+4Kj3zdAmpB+N7h4Y+OD6FjykyTr8hgG5z2E132tyLf X-Received: by 2002:a05:620a:55a3:b0:787:240f:f438 with SMTP id vr3-20020a05620a55a300b00787240ff438mr2055017qkn.22.1708012727830; Thu, 15 Feb 2024 07:58:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708012727; cv=pass; d=google.com; s=arc-20160816; b=j3LPVHeKuyxcxt4cNa9zud5TKXl1+w4EvulJN+U7ABerygO/rwKMTIQgRkoN4OTAxs Hqg3f92rUINUk8MRF4GEYfSWrIp1PdAxfGNYnyCgW1vgtZ0hDPkLEbBI5YcK36QVcrSu LrbjwTtb54fHBZX27zchIrnpNOqYBsW6gAEUynPfseK9McsJIpdXfpJ4Yjlssx46L92q PlQw8xTA5pehQ0flQBeQs5G80GtdIH+QSY9CI5bnle9/XwdkiOHFxY29ijz8DEz4FGUr HwqYdkyR2eDr5aPXjqX+vqUoO1zIpPsvXrVc1SCcbsPc/NUjXk01lpJQ/EfbjJXmbZ06 sv3w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=Z5LLdPo92KfTyd92D8AUwdm6aKFRzO9h1MK17wCqVsA=; fh=6sWHPsCQUoLz5ZcbqIohOjwdU7jjRT/citiAJwaEf0c=; b=Lb3wEJkU03JLKz8X94QKIfQ89pRmESRTXuZ7u+EtcJ2iPh/3uZLASeeo5xrsEDp59W trJGkrCcn/OBif+vpHabu+fLLb+pCSOKNuoi1XxyuzDuaebsP7G0xto/DiHAq9dejAy2 EmQYzi9eotkFoYm+TMRrJ2l54I1Kl4xO4U5+Vf8xv5imJrbbwQlzFvS+wNWeeqDbAf6W IJBkl3e99okHXIIo6J9GJmsvkLRrcAMxdKl1tsYkXbVrzeJ8V1m7cZTy1Jcz+nNjHYSA G5DSzmiB0gJIvatKRonopwjjhz6TrRheHZdrvQwIfIS5/xfzXiegaHlfK3DLKbZVld4C wB7A==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=sg+wFQdR; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. 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Thu, 15 Feb 2024 15:58:28 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:28 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 03/14] s390: Do not erroneously use base operand value for length operand Date: Thu, 15 Feb 2024 16:58:10 +0100 Message-Id: <20240215155821.4065623-4-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: QIlDxuu0ykqEMF1ZojTDPd5LGxlDcKDu X-Proofpoint-GUID: QIlDxuu0ykqEMF1ZojTDPd5LGxlDcKDu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 phishscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 malwarescore=0 spamscore=0 impostorscore=0 mlxlogscore=978 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981154274351508 X-GMAIL-MSGID: 1790981154274351508 The base register operand B may optionally be omitted in D(B) by coding D and in D(L,B) by coding D(L). The index register operand X may optionally be omitted in D(X,B) by coding D(,B) or D(B). Both base and index register operands may optionally be omitted in D(X,B) by coding D. In any case the omitted base and/or index register operand value defaults to zero. When parsing an erroneously omitted length L operand in D(L,B) by coding D(,B) the base register operand B was erroneously consumed as length operand. When using a register name for the base register operand this was detected and reported as error. But when not using a register name the base register operand value was erroneously used as length operand value. Correct the parsing of an omitted optional base or index register to not erroneously use the base register operand value as length, when erroneously omitting the length operand. While at it rename the variable used to remember whether the base or index register operand was omitted to enhance code readability. Additionally add test cases for the optional omission of base and/or index register operands. Example assembler source: mvc 16(1,%r1),32(%r2) mvc 16(1),32(%r2) mvc 16(,1),32(%r2) # undetected syntax error Disassembly of bad assembly without commit shows the base register operand value was erroneously used as length operand value: 0: d2 00 10 10 20 20 mvc 16(1,%r1),32(%r2) 6: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2) c: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2) Assembler messages with commit: 3: Error: operand 1: missing operand gas/ * config/tc-s390.c: Correct parsing of omitted base register. * testsuite/gas/s390/s390.exp: Add test cases for omitted base and/or index register. * testsuite/gas/s390/zarch-omitted-base-index.s: Test cases for omitted optional base or index register. * testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. * testsuite/gas/s390/zarch-omitted-base-index-err.s: Test cases for omitted base and/or index register. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/config/tc-s390.c | 35 ++++++++++--------- gas/testsuite/gas/s390/s390.exp | 2 ++ .../gas/s390/zarch-omitted-base-index-err.l | 24 +++++++++++++ .../gas/s390/zarch-omitted-base-index-err.s | 20 +++++++++++ .../gas/s390/zarch-omitted-base-index.d | 22 ++++++++++++ .../gas/s390/zarch-omitted-base-index.s | 24 +++++++++++++ 6 files changed, 110 insertions(+), 17 deletions(-) create mode 100644 gas/testsuite/gas/s390/zarch-omitted-base-index-err.l create mode 100644 gas/testsuite/gas/s390/zarch-omitted-base-index-err.s create mode 100644 gas/testsuite/gas/s390/zarch-omitted-base-index.d create mode 100644 gas/testsuite/gas/s390/zarch-omitted-base-index.s diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 019f26b2f4ab..cfe98b5e94be 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -1268,16 +1268,15 @@ md_gather_operands (char *str, expressionS ex; elf_suffix_type suffix; bfd_reloc_code_real_type reloc; - int skip_optional; + int omitted_base_or_index; char *f; int fc, i; while (ISSPACE (*str)) str++; - skip_optional = 0; - /* Gather the operands. */ + omitted_base_or_index = 0; /* Whether B in D(L,B) or X in D(X,B) were omitted. */ fc = 0; for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) { @@ -1294,13 +1293,13 @@ md_gather_operands (char *str, break; } - if (skip_optional && (operand->flags & S390_OPERAND_INDEX)) + if (omitted_base_or_index && (operand->flags & S390_OPERAND_INDEX)) { - /* We do an early skip. For D(X,B) constructions the index - register is skipped (X is optional). For D(L,B) the base - register will be the skipped operand, because L is NOT - optional. */ - skip_optional = 0; + /* Skip omitted optional index register operand in D(X,B) due to + D(,B) or D(B). Skip comma, if D(,B). */ + if (*str == ',') + str++; + omitted_base_or_index = 0; continue; } @@ -1510,17 +1509,19 @@ md_gather_operands (char *str, for (f = str; *f != '\0'; f++) if (*f == ',' || *f == ')') break; - /* If there is no comma until the closing parentheses OR - there is a comma right after the opening parentheses, - we have to skip optional operands. */ + /* If there is no comma until the closing parenthesis ')' or + there is a comma right after the opening parenthesis '(', + we have to skip the omitted optional index or base register + operand: + - Index X in D(X,B), when D(,B) or D(B) + - Base B in D(L,B), when D(L) */ if (*f == ',' && f == str) { - /* comma directly after '(' ? */ - skip_optional = 1; - str++; + /* Comma directly after opening parenthesis '(' ? */ + omitted_base_or_index = 1; } else - skip_optional = (*f != ','); + omitted_base_or_index = (*f != ','); } } else if (operand->flags & S390_OPERAND_BASE) @@ -1530,7 +1531,7 @@ md_gather_operands (char *str, as_bad (_("syntax error; missing ')' after base register")); else str++; - skip_optional = 0; + omitted_base_or_index = 0; if (*str == '\0' && skip_optargs_p (opcode->flags, &opindex_ptr[1])) continue; diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp index 86e2dd492cd1..7fbc7f8a7515 100644 --- a/gas/testsuite/gas/s390/s390.exp +++ b/gas/testsuite/gas/s390/s390.exp @@ -44,4 +44,6 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { run_list_test "machine-parsing-4" "" run_list_test "machine-parsing-5" "" run_list_test "machine-parsing-6" "" + run_dump_test "zarch-omitted-base-index" "{as -m64}" + run_list_test "zarch-omitted-base-index-err" "" } diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l new file mode 100644 index 000000000000..fe13f95d3174 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l @@ -0,0 +1,24 @@ +.*: Assembler messages: +.*:5: Error: bad expression +.*:5: Error: syntax error; missing '\)' after base register +.*:8: Error: bad expression +.*:8: Error: syntax error; missing '\)' after base register +.*:9: Error: bad expression +.*:9: Error: syntax error; missing '\)' after base register +.*:12: Error: bad expression +.*:12: Error: syntax error; missing '\)' after base register +.*:13: Error: bad expression +.*:13: Error: syntax error; missing '\)' after base register +.*:16: Error: missing operand +.*:17: Error: missing operand +.*:18: Error: invalid length field specified +.*:19: Error: bad expression +.*:19: Error: operand out of range \(0 is not between 1 and 256\) +.*:19: Error: operand out of range \(32 is not between 0 and 15\) +.*:19: Error: syntax error; missing '\)' after base register +.*:19: Error: syntax error; expected ',' +.*:19: Error: bad expression +.*:19: Error: found 'r', expected: '\)' +.*:19: Error: syntax error; missing '\)' after base register +.*:19: Error: junk at end of line: `r2\)' +.*:20: Error: syntax error; missing '\(' after displacement diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s new file mode 100644 index 000000000000..65ad739d02c6 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s @@ -0,0 +1,20 @@ +.text +foo: + +# R1,D2(B2) + clm %r1,0b1000,16() + +# R1,D2(X2,B2) + a %r1,16(%r2,) + a %r1,16() + +# V1,D2(VX2,B2),M3 + vgef %v1,16(%v2,),0 + vgef %v1,16(),0 + +# D1(L1,B1),D2(B2) + mvc 16(,%r1),32(%r2) + mvc 16(,1),32(%r2) + mvc 16(%r1),32(%r2) + mvc 16(),32(%r2) + mvc 16,32(%r2) diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index.d b/gas/testsuite/gas/s390/zarch-omitted-base-index.d new file mode 100644 index 000000000000..b2ff292628b1 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index.d @@ -0,0 +1,22 @@ +#name: s390x omit base/index register +#objdump: -dr + +.*: +file format .* + +Disassembly of section .text: + +.* : +.*: bd 18 20 10 [ ]*clm %r1,8,16\(%r2\) +.*: bd 18 00 10 [ ]*clm %r1,8,16 +.*: 5a 12 30 10 [ ]*a %r1,16\(%r2,%r3\) +.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) +.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) +.*: 5a 10 00 10 [ ]*a %r1,16 +.*: e7 12 30 10 00 13 [ ]*vgef %v1,16\(%v2,%r3\),0 +.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 +.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 +.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 +.*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\) +.*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index.s b/gas/testsuite/gas/s390/zarch-omitted-base-index.s new file mode 100644 index 000000000000..8381319068bc --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index.s @@ -0,0 +1,24 @@ +.text +foo: + +# R1,D2(B2) + clm %r1,0b1000,16(%r2) + clm %r1,0b1000,16 + +# R1,D1(X2,B2) + a %r1,16(%r2,%r3) + a %r1,16(,%r3) + a %r1,16(%r3) + a %r1,16 + +# V1,D2(VX2,B2),M3 + vgef %v1,16(%v2,%r3),0 + vgef %v1,16(,%r3),0 + vgef %v1,16(%r3),0 + vgef %v1,16,0 + +# D1(L1,B1),D2(B2) + mvc 16(1,%r1),32(%r2) + mvc 16(1,%r1),32 + mvc 16(1),32(%r2) + mvc 16(1),32 From patchwork Thu Feb 15 15:58:11 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 15:58:28 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:28 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 04/14] s390: Correct setting of highgprs flag in ELF output Date: Thu, 15 Feb 2024 16:58:11 +0100 Message-Id: <20240215155821.4065623-5-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: c9bsX4KSYzCWFLSHRyq_eiNXo7ZX1dnD X-Proofpoint-GUID: c9bsX4KSYzCWFLSHRyq_eiNXo7ZX1dnD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 phishscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 malwarescore=0 spamscore=0 impostorscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981162549867051 X-GMAIL-MSGID: 1790981162549867051 The combination of an architecture size of 32 bits and z/Architecture mode requires the highgprs flag to be set in the ELF output. It causes the high-halves of the general purpose registers (GPRs) to be preserved at run-time, so that the code can use 64-bit GPRs. The architecture size of 32 bits can either be the default in case of a default architecture name of "s390" or due to specification of the option -m31 (to generate the 31-bit file format). The z/Architecture mode can either be the default or due to specification of the option -mzarch (to assemble for z/Architecture mode). It can also be selected using the pseudo commands ".machinemode zarch" and ".machinemode zarch_nohighgprs". The latter not causing the highgprs flag to be set. The highgprs flag was only set when the following s390-specific assembler options were given in the following specific order: "-m31 -mzarch". The highgprs flag was erroneously not set when: - the order of above options was inverse (i.e. "-mzarch -m31"), - the architecture mode defaulted to z/Architecture mode and option "-m31" was specified, - the architecture size defaulted to 32 bits due to a default architecture name of "s390" and option -mzarch was specified, - the architecture size defaulted to 32 bits and the architecture mode defaulted to z/Architecture due to the specified processor (e.g. "-march=z900" or follow-on processor). Determine whether to set the highgprs flag in init_default_arch() after having processed all assembler options in md_parse_option(). This ensures the flag is set in all of the above cases it was erroneously not set. Add test cases for highgprs flag, including ones that use .machinemode to switch the architecture mode. gas/ * config/tc-s390.c: Correct setting of highgprs flag in ELF output. * testsuite/gas/s390/s390.exp: Add test cases for highgprs flag. * testsuite/gas/s390/blank.s: Empty assembler source used in test cases for "highgprs" flag. * testsuite/gas/s390/esa-highgprs-0.d: Add test case for highgprs flag. * testsuite/gas/s390/zarch-highgprs-0.d: Likewise. * testsuite/gas/s390/zarch-highgprs-1.d: Likewise. * testsuite/gas/s390/esa-highgprs-machinemode-0.s: Add test case for highgprs flag when using .machinemode to switch architecture mode. * testsuite/gas/s390/esa-highgprs-machinemode-0.d: Likewise. * testsuite/gas/s390/esa-highgprs-machinemode-1.s: Likewise. * testsuite/gas/s390/esa-highgprs-machinemode-1.d: Likewise. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/config/tc-s390.c | 14 ++++++----- gas/testsuite/gas/s390/blank.s | 0 gas/testsuite/gas/s390/esa-highgprs-0.d | 24 +++++++++++++++++++ .../gas/s390/esa-highgprs-machinemode-0.d | 23 ++++++++++++++++++ .../gas/s390/esa-highgprs-machinemode-0.s | 2 ++ .../gas/s390/esa-highgprs-machinemode-1.d | 23 ++++++++++++++++++ .../gas/s390/esa-highgprs-machinemode-1.s | 3 +++ gas/testsuite/gas/s390/s390.exp | 12 ++++++++++ gas/testsuite/gas/s390/zarch-highgprs-0.d | 24 +++++++++++++++++++ gas/testsuite/gas/s390/zarch-highgprs-1.d | 24 +++++++++++++++++++ 10 files changed, 143 insertions(+), 6 deletions(-) create mode 100644 gas/testsuite/gas/s390/blank.s create mode 100644 gas/testsuite/gas/s390/esa-highgprs-0.d create mode 100644 gas/testsuite/gas/s390/esa-highgprs-machinemode-0.d create mode 100644 gas/testsuite/gas/s390/esa-highgprs-machinemode-0.s create mode 100644 gas/testsuite/gas/s390/esa-highgprs-machinemode-1.d create mode 100644 gas/testsuite/gas/s390/esa-highgprs-machinemode-1.s create mode 100644 gas/testsuite/gas/s390/zarch-highgprs-0.d create mode 100644 gas/testsuite/gas/s390/zarch-highgprs-1.d diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index cfe98b5e94be..55a5873edc18 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -47,7 +47,7 @@ static unsigned int current_flags = S390_INSTR_FLAG_FACILITY_MASK; static unsigned int current_mode_mask = 0; /* Set to TRUE if the highgprs flag in the ELF header needs to be set - for the output file. */ + for the output file. The default is picked in init_default_arch(). */ static bool set_highgprs_p = false; /* Whether to use user friendly register names. Default is TRUE. */ @@ -221,6 +221,7 @@ size_t md_longopts_size = sizeof (md_longopts); static void init_default_arch (void) { + /* Default architecture size. */ if (strcmp (default_arch, "s390") == 0) { if (s390_arch_size == 0) @@ -234,6 +235,7 @@ init_default_arch (void) else as_fatal (_("Invalid default architecture, broken assembler.")); + /* Default current architecture mode. */ if (current_mode_mask == 0) { /* Default to z/Architecture mode if the CPU supports it. */ @@ -242,6 +244,10 @@ init_default_arch (void) else current_mode_mask = 1 << S390_OPCODE_ZARCH; } + + /* Determine whether the highgprs flag in the ELF header needs to be set. */ + if ((s390_arch_size == 32) && (current_mode_mask & (1 << S390_OPCODE_ZARCH))) + set_highgprs_p = true; } /* Called by TARGET_FORMAT. */ @@ -419,11 +425,7 @@ md_parse_option (int c, const char *arg) current_mode_mask = 1 << S390_OPCODE_ESA; else if (arg != NULL && strcmp (arg, "zarch") == 0) - { - if (s390_arch_size == 32) - set_highgprs_p = true; - current_mode_mask = 1 << S390_OPCODE_ZARCH; - } + current_mode_mask = 1 << S390_OPCODE_ZARCH; else if (arg != NULL && startswith (arg, "arch=")) { diff --git a/gas/testsuite/gas/s390/blank.s b/gas/testsuite/gas/s390/blank.s new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/gas/testsuite/gas/s390/esa-highgprs-0.d b/gas/testsuite/gas/s390/esa-highgprs-0.d new file mode 100644 index 000000000000..aa9eff70cfeb --- /dev/null +++ b/gas/testsuite/gas/s390/esa-highgprs-0.d @@ -0,0 +1,24 @@ +#name: s390 highgprs 0 +#source: blank.s +#readelf: -h + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: IBM S/390 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: 164 \(bytes into file\) + Flags: 0x0 + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 7 + Section header string table index: 6 diff --git a/gas/testsuite/gas/s390/esa-highgprs-machinemode-0.d b/gas/testsuite/gas/s390/esa-highgprs-machinemode-0.d new file mode 100644 index 000000000000..483342f3f8bd --- /dev/null +++ b/gas/testsuite/gas/s390/esa-highgprs-machinemode-0.d @@ -0,0 +1,23 @@ +#name: s390 highgprs machinemode 0 +#readelf: -h + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: IBM S/390 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: 164 \(bytes into file\) + Flags: 0x0 + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 7 + Section header string table index: 6 diff --git a/gas/testsuite/gas/s390/esa-highgprs-machinemode-0.s b/gas/testsuite/gas/s390/esa-highgprs-machinemode-0.s new file mode 100644 index 000000000000..60d9e3f56781 --- /dev/null +++ b/gas/testsuite/gas/s390/esa-highgprs-machinemode-0.s @@ -0,0 +1,2 @@ +.text + .machinemode zarch_nohighgprs diff --git a/gas/testsuite/gas/s390/esa-highgprs-machinemode-1.d b/gas/testsuite/gas/s390/esa-highgprs-machinemode-1.d new file mode 100644 index 000000000000..c1adc1603b23 --- /dev/null +++ b/gas/testsuite/gas/s390/esa-highgprs-machinemode-1.d @@ -0,0 +1,23 @@ +#name: s390 highgprs machinemode 1 +#readelf: -h + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: IBM S/390 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: 164 \(bytes into file\) + Flags: 0x1, highgprs + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 7 + Section header string table index: 6 diff --git a/gas/testsuite/gas/s390/esa-highgprs-machinemode-1.s b/gas/testsuite/gas/s390/esa-highgprs-machinemode-1.s new file mode 100644 index 000000000000..c46b95b7e95d --- /dev/null +++ b/gas/testsuite/gas/s390/esa-highgprs-machinemode-1.s @@ -0,0 +1,3 @@ +.text + .machinemode zarch + .machinemode esa diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp index 7fbc7f8a7515..b63c09e40324 100644 --- a/gas/testsuite/gas/s390/s390.exp +++ b/gas/testsuite/gas/s390/s390.exp @@ -12,6 +12,16 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { run_dump_test "esa-z9-109" "{as -m31} {as -march=z9-109}" run_dump_test "esa-reloc" "{as -m31}" run_dump_test "esa-operands" "{as -m31}" + run_dump_test "esa-highgprs-0" "{as -m31} {as -mesa}" + run_dump_test "esa-highgprs-0" "{as -mesa} {as -m31}" + run_dump_test "esa-highgprs-0" "{as -m31} {as -march=g5}" + run_dump_test "zarch-highgprs-1" "{as -m31} {as -mzarch}" + run_dump_test "zarch-highgprs-1" "{as -mzarch} {as -m31}" + run_dump_test "zarch-highgprs-1" "{as -m31} {as -march=z900}" + run_dump_test "esa-highgprs-machinemode-0" "{as -m31} {as -mesa}" + run_dump_test "esa-highgprs-machinemode-0" "{as -mesa} {as -m31}" + run_dump_test "esa-highgprs-machinemode-1" "{as -m31} {as -mesa}" + run_dump_test "esa-highgprs-machinemode-1" "{as -mesa} {as -m31}" } # # PIC is only supported on ELF targets. @@ -44,6 +54,8 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { run_list_test "machine-parsing-4" "" run_list_test "machine-parsing-5" "" run_list_test "machine-parsing-6" "" + run_dump_test "zarch-highgprs-0" "{as -m64} {as -mzarch}" + run_dump_test "zarch-highgprs-0" "{as -mzarch} {as -m64}" run_dump_test "zarch-omitted-base-index" "{as -m64}" run_list_test "zarch-omitted-base-index-err" "" } diff --git a/gas/testsuite/gas/s390/zarch-highgprs-0.d b/gas/testsuite/gas/s390/zarch-highgprs-0.d new file mode 100644 index 000000000000..53cc3e057652 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-highgprs-0.d @@ -0,0 +1,24 @@ +#name: s390x highgprs 0 +#source: blank.s +#readelf: -h + +ELF Header: + Magic: 7f 45 4c 46 02 02 01 00 00 00 00 00 00 00 00 00 + Class: ELF64 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: IBM S/390 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: 208 \(bytes into file\) + Flags: 0x0 + Size of this header: 64 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 64 \(bytes\) + Number of section headers: 7 + Section header string table index: 6 diff --git a/gas/testsuite/gas/s390/zarch-highgprs-1.d b/gas/testsuite/gas/s390/zarch-highgprs-1.d new file mode 100644 index 000000000000..d351032fbc47 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-highgprs-1.d @@ -0,0 +1,24 @@ +#name: s390x highgprs 0 +#source: blank.s +#readelf: -h + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: IBM S/390 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: 164 \(bytes into file\) + Flags: 0x1, highgprs + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 7 + Section header string table index: 6 From patchwork Thu Feb 15 15:58:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 201599 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp494962dyb; Thu, 15 Feb 2024 07:59:42 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXmRAV5FoxTXUlO/V/fVo+8J6XzaYrlGXdNOcRS0w/V3a56ltI0sm1qLW+LRe2uBCbT2NDVZ2vHbOjhNWKyLg3sT9hYlQ== X-Google-Smtp-Source: AGHT+IGxiZMY/br1tycJWXo82ptLx9rZypfSGIkrm1x3MXLlwZiFgd+ayybF6G6Cv5RbBMUAEm+3 X-Received: by 2002:a67:ee56:0:b0:46d:2f1e:3d15 with SMTP id g22-20020a67ee56000000b0046d2f1e3d15mr1810421vsp.35.1708012781897; Thu, 15 Feb 2024 07:59:41 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708012781; cv=pass; d=google.com; s=arc-20160816; b=cvTzn55hOrKVOcfvC0n6gRvLa97m9wlBnJXi0kPBSsO817c1gp4pYp+VXSWjetfFxL jZMbzpUqQLg0PvDnPy+q4Ce19XTpzkgYOwWz3mqP5FCUIdIAxYUGPyCNMB9kSe7t3rvk Xc+QDxJCrX4FZ5LPiqYmnete7HRip6IlBOuHCkpnjGA+ZwpsugrNnWhTHRsy7BC6v54V zGLPg0ITgF0TORRZkO5dG+zQhXy1i5+gq0WhIOaMPFiBfggLiZIfGEBKfpkqBeefzqoc 1eUavlLHdZu4rri+0vJVkZq08ZPXsCrdGZxQnXybblnXPtqsydPmzajK021mCYCXJzKp H4+g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=A5px2oi50Axq5EbVtBndjIsKGOaCJ3UgpZ6lbjQvPro=; fh=6sWHPsCQUoLz5ZcbqIohOjwdU7jjRT/citiAJwaEf0c=; b=QAMcDPBmQSNInRRlm6ceVUrr8GbrxxD0qztfyIRNLQ5WOif80w/QsFrG344TCXU+MQ T0/G5Pm08SHn3unmszBaKgCTOqrVvYTML/i4ejHJcRODwfHyI6OKux3n679dRX8oH4zS ZjeIMD7kb2P93xUdw1w0E9BBFfNp3gU5Nesb9N7To/8/9fuuJtSV/wBTlHCGJDqhW5q4 0k792VwwXjIg1pjlgY2G3m+FxaP2etuiEmGMEcJlT465MKBLUhHIjjXmg/ESRtnrhaYy Zp9/h8ixPeAD++gEzI3KeNSc8PD0C6LdoEXpHB2dfD8itBiNH++eugr5M95eTigzY1Hf f2bQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=KiXPC+nU; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. 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Thu, 15 Feb 2024 15:58:28 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:28 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 05/14] s390: Assemble processor specific test cases for their processor Date: Thu, 15 Feb 2024 16:58:12 +0100 Message-Id: <20240215155821.4065623-6-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: QR6-lDc2ozNmAMZLhf1DO8wuYNzW_UZO X-Proofpoint-ORIG-GUID: QR6-lDc2ozNmAMZLhf1DO8wuYNzW_UZO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=519 impostorscore=0 adultscore=0 spamscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 malwarescore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981210753979560 X-GMAIL-MSGID: 1790981210753979560 Assemble the esa-g5 test case with -march=g5. Assemble the zarch-z900 test case with -march=z900. gas/ * testsuite/gas/s390/s390.exp: Assemble processor specific test cases for their respective processor (-march=). Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/testsuite/gas/s390/s390.exp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp index b63c09e40324..ddba9f99f4a9 100644 --- a/gas/testsuite/gas/s390/s390.exp +++ b/gas/testsuite/gas/s390/s390.exp @@ -6,7 +6,7 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { # s390x-ibm-tpf target does not support a 32-bit target. if { ! [istarget "s390x-*-tpf*"] } then { - run_dump_test "esa-g5" "{as -m31}" + run_dump_test "esa-g5" "{as -m31} {as -march=g5}" run_dump_test "esa-z900" "{as -m31} {as -march=z900}" run_dump_test "esa-z990" "{as -m31} {as -march=z990}" run_dump_test "esa-z9-109" "{as -m31} {as -march=z9-109}" @@ -29,7 +29,7 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { # run_dump_test "s390pic" # } - run_dump_test "zarch-z900" "{as -m64}" + run_dump_test "zarch-z900" "{as -m64} {as -march=z900}" run_list_test "zarch-z900-err" "-march=z900" run_dump_test "zarch-z990" "{as -m64} {as -march=z990}" run_list_test "zarch-z990-symbol-lay" "-m64 -march=z990" From patchwork Thu Feb 15 15:58:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 201603 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp495885dyb; Thu, 15 Feb 2024 08:00:49 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWnDPYDc5ltcjSh/o8l3yzrVo7zfp7OfOMrAtSnpLfWhxIw/7ExqO1Gowmdcl6miU6USGcKGDsjtqW+xd+KugfnmC1d5w== X-Google-Smtp-Source: AGHT+IHY4OHwRZAzJ4+tVuWyeCbMuuba0CLuUFlQcfUcFq2jt91ywW1X3+LiEJ9nZPHv9XUEul8s X-Received: by 2002:a25:874a:0:b0:dc6:d738:1fa6 with SMTP id e10-20020a25874a000000b00dc6d7381fa6mr2295345ybn.6.1708012849016; Thu, 15 Feb 2024 08:00:49 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708012849; cv=pass; d=google.com; s=arc-20160816; b=OZtyLENX13lRfpFwz9qLe6zGynGFQhZ4ZH/JoJc9Q9P2eYGgYUzfYpKcnqbQC622dy T29YEUbIKWSeExz0nyrGAoVtlDgFAR0AqWL0WNtDfCbeAMqSf4fwhj90XV9PNdllRZlu CtPgshNEx3VdH/bjoq41AG1aErKvqg6f2WLj5XfPayyFAnSDVtKkp9PYJFiV1YMoUVVk RU+MAN0wGCainD34dWkCQzWdNPaw+Uc+NhuZwskesPo/EZ1pr+YUCKkSNwUCj0zg8cux uOcE7RKZPfMgZi5X5AfsszKafNQ7LgXGoQpJnfbSUGhwF3g6suzi9H/1EZpbs/7kp+Gc 0uCA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=vFsEejuF/rrpUdROhAO3WlRaZPB/xaNO0kTVHocH+p8=; fh=6sWHPsCQUoLz5ZcbqIohOjwdU7jjRT/citiAJwaEf0c=; b=NmCcEt0+tZRBVdkneckfadLa0+mO+P9ttFl4MBmxAbMyKjQ+M+sakF6XbprCiGKqpJ JDjzlRN0jfqy84apL1KiD58Sr6HjvmSOCODa//zWtWAaqVSvqIAXAG/5vE6U5k3fL99W 3Uts63kKQ74mBERXEoCMglGnvOKfwz6MBb+LTZnNz4uk3Y9TntaYPD5zjkI6tFlfwX3N 9WH8lHLT6JCHTeMqwcUt/oNmlfOvUfW9qN3coTmJfvRREaafPXSfErUo4mctE6+t3GP3 KVTTS5vl3IrVQNxPT0AAzoGmBucy4xhL+LFG1284c0RCslUko6j6jXQydLnH2I7dYoWz D63Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=YZgQmfAG; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. 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Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/config/tc-s390.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 55a5873edc18..9aebd8ca91e5 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -1474,9 +1474,10 @@ md_gather_operands (char *str, /* After a displacement a block in parentheses can start. */ if (*str != '(') { - /* Check if parenthesized block can be skipped. If the next - operand is neither an optional operand nor a base register - then we have a syntax error. */ + /* There is no opening parentheses. Check if operands of + parenthesized block can be skipped. Only index and base + register operands as well as optional operands may be + skipped. A length operand may not be skipped. */ operand = s390_operands + *(++opindex_ptr); if (!(operand->flags & (S390_OPERAND_INDEX|S390_OPERAND_BASE))) as_bad (_("syntax error; missing '(' after displacement")); @@ -1485,6 +1486,8 @@ md_gather_operands (char *str, while (!(operand->flags & S390_OPERAND_BASE)) operand = s390_operands + *(++opindex_ptr); + /* If there is no further input and the remaining operands are + optional then have these optional operands processed. */ if (*str == '\0' && skip_optargs_p (opcode->flags, &opindex_ptr[1])) continue; @@ -1493,6 +1496,7 @@ md_gather_operands (char *str, { if (*str != ',') { + /* There is no comma. Skip all operands and stop. */ while (opindex_ptr[1] != '\0') { operand = s390_operands + *(++opindex_ptr); @@ -1501,7 +1505,10 @@ md_gather_operands (char *str, } } else - str++; + { + /* Comma. */ + str++; + } } } else @@ -1535,6 +1542,8 @@ md_gather_operands (char *str, str++; omitted_base_or_index = 0; + /* If there is no further input and the remaining operands are + optional then have these optional operands processed. */ if (*str == '\0' && skip_optargs_p (opcode->flags, &opindex_ptr[1])) continue; @@ -1543,6 +1552,7 @@ md_gather_operands (char *str, { if (*str != ',') { + /* There is no comma. Skip all operands and stop. */ while (opindex_ptr[1] != '\0') { operand = s390_operands + *(++opindex_ptr); @@ -1551,7 +1561,10 @@ md_gather_operands (char *str, } } else - str++; + { + /* Comma. */ + str++; + } } } else @@ -1567,6 +1580,8 @@ md_gather_operands (char *str, str++; } + /* If there is no further input and the remaining operands are + optional then have these optional operands processed. */ if (*str == '\0' && skip_optargs_p (opcode->flags, &opindex_ptr[1])) continue; @@ -1575,6 +1590,7 @@ md_gather_operands (char *str, { if (*str != ',') { + /* There is no comma. Skip all operands and stop. */ while (opindex_ptr[1] != '\0') { operand = s390_operands + *(++opindex_ptr); @@ -1583,7 +1599,10 @@ md_gather_operands (char *str, } } else - str++; + { + /* Comma. */ + str++; + } } } } From patchwork Thu Feb 15 15:58:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 201601 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp495650dyb; Thu, 15 Feb 2024 08:00:33 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVy38R3b/bAcTuUlv4+AsKrLKgclMIHC+m9A5bdpFk4lJhk0XmNlF6QJO/Ky0KYLtm1LBYWwBjVLUu+AHgOTWVtxsT8Iw== X-Google-Smtp-Source: AGHT+IGtSOkYhGE3AjS+fK/iyml8Bxh6CL2JqJIR2CXDbNF4pWpUPCx05voKLXanE8xDGgi8ZwuJ X-Received: by 2002:a05:6870:9a1d:b0:219:dff0:ffbb with SMTP id fo29-20020a0568709a1d00b00219dff0ffbbmr1921168oab.54.1708012833193; Thu, 15 Feb 2024 08:00:33 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708012833; cv=pass; d=google.com; s=arc-20160816; b=NyeR77Mh4zLI6KiTpQFjQMwPmF/o5Hz9h6t1INaBUwQrjkI+33M8uCAJV4mT15zRHE XXCquD3cFbYiKKX0t9iGQCUsTOJq34Pum9sbYQAO97Euonn2To7iKBw7BXbiaBFJsFfC Ed1QlQ2XfZxw47TLR1+atY962ngzZBh0Ul7vfwgFIWoFNplfNFrZMdTFB5kHECC/go86 P+YvZVpEN6t/ldQsLxVLmzKTW766TY/zk58XzOrH7IS8HeubE7VOc16qBBtNthiUT3Lm tzaQA3WCTyKQtLNVrzpnPsk6X3pyEitufnD/npFfKsZROwAsID8rP/MBwwfm/Y/gfHuf MYnQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=0p4P5dYJxbBWHyzFhRw+4YBCZgmvVWCnCQrwjbwxiYM=; fh=6sWHPsCQUoLz5ZcbqIohOjwdU7jjRT/citiAJwaEf0c=; b=a+jGTseDPO67zNGQwl60RRzMbamx85yafJIhPrGCdXhZuVvRWhm5IPLtCi04dMTUsA sth1ZAZzZUOvNrgNwF276x4w6ovikCJnCBIn0oZYuBpcP3oy2zGKXK0KBP1pMFDjkSXJ vLpxx9VNQ5JrHchp670IszDp7nbvP+57ywXNfvczkZONvDlj1Xl+ABffFgnjy16udj4/ LpCGWOirenjXGK+VEBgtNLyWbU7Yy2tz+LMT48DopA9/IqSLM3cJlsy3pdp+G5FUPkoa InzHL69M1rNeNJePUITvgqVmTen2e59zFIV02pSTnKic/xktAF7/rAX3I4b25eSDGWFn OsqA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=iwRz95Rd; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. 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Thu, 15 Feb 2024 15:58:29 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:29 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 07/14] s390: Add test cases for base/index register 0 Date: Thu, 15 Feb 2024 16:58:14 +0100 Message-Id: <20240215155821.4065623-8-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: JiJXSn2ZC5rmmJBdEvQMboOOmwiSMNR9 X-Proofpoint-GUID: JiJXSn2ZC5rmmJBdEvQMboOOmwiSMNR9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 mlxlogscore=877 bulkscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981264167320994 X-GMAIL-MSGID: 1790981264167320994 While at it add comments to logic to omit base and/or index register 0 in s390 disassembly. opcodes/ * s390-dis.c: Add comments related to omitting base and/or index register 0 in disassembly. gas/ * testsuite/gas/s390/s390.exp: Add test cases for base and/or index register 0. * testsuite/gas/s390/zarch-base-index-0.s: Add test cases for base and/or index register 0. * testsuite/gas/s390/zarch-base-index-0.d: Likewise. * testsuite/gas/s390/zarch-base-index-0-err.s: Add error test cases for base and/or index register 0. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/testsuite/gas/s390/s390.exp | 2 + .../gas/s390/zarch-base-index-0-err.l | 126 ++++++++++++++++++ .../gas/s390/zarch-base-index-0-err.s | 66 +++++++++ gas/testsuite/gas/s390/zarch-base-index-0.d | 84 ++++++++++++ gas/testsuite/gas/s390/zarch-base-index-0.s | 116 ++++++++++++++++ opcodes/s390-dis.c | 5 +- 6 files changed, 397 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/s390/zarch-base-index-0-err.l create mode 100644 gas/testsuite/gas/s390/zarch-base-index-0-err.s create mode 100644 gas/testsuite/gas/s390/zarch-base-index-0.d create mode 100644 gas/testsuite/gas/s390/zarch-base-index-0.s diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp index ddba9f99f4a9..f5798b4778e1 100644 --- a/gas/testsuite/gas/s390/s390.exp +++ b/gas/testsuite/gas/s390/s390.exp @@ -58,4 +58,6 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { run_dump_test "zarch-highgprs-0" "{as -mzarch} {as -m64}" run_dump_test "zarch-omitted-base-index" "{as -m64}" run_list_test "zarch-omitted-base-index-err" "" + run_dump_test "zarch-base-index-0" "{as -m64}" + run_list_test "zarch-base-index-0-err" "" } diff --git a/gas/testsuite/gas/s390/zarch-base-index-0-err.l b/gas/testsuite/gas/s390/zarch-base-index-0-err.l new file mode 100644 index 000000000000..1762b6ec0813 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-base-index-0-err.l @@ -0,0 +1,126 @@ +.*: Assembler messages: +.*:5: Error: bad expression +.*:5: Error: syntax error; missing '\)' after base register +.*:8: Error: bad expression +.*:8: Error: syntax error; missing '\)' after base register +.*:9: Error: bad expression +.*:9: Error: syntax error; missing '\)' after base register +.*:10: Error: bad expression +.*:10: Error: syntax error; missing '\)' after base register +.*:11: Error: bad expression +.*:11: Error: syntax error; missing '\)' after base register +.*:12: Error: bad expression +.*:12: Error: syntax error; missing '\)' after base register +.*:15: Error: bad expression +.*:15: Error: syntax error; missing '\)' after base register +.*:16: Error: bad expression +.*:16: Error: syntax error; missing '\)' after base register +.*:17: Error: bad expression +.*:17: Error: syntax error; missing '\)' after base register +.*:18: Error: bad expression +.*:18: Error: syntax error; missing '\)' after base register +.*:19: Error: bad expression +.*:19: Error: syntax error; missing '\)' after base register +.*:20: Error: bad expression +.*:20: Error: syntax error; missing '\)' after base register +.*:21: Error: bad expression +.*:21: Error: syntax error; missing '\)' after base register +.*:21: Error: bad expression +.*:21: Error: syntax error; missing '\)' after base register +.*:22: Error: bad expression +.*:22: Error: syntax error; missing '\)' after base register +.*:23: Error: bad expression +.*:23: Error: syntax error; missing '\)' after base register +.*:24: Error: operand out of range \(0 is not between 1 and 256\) +.*:25: Error: missing operand +.*:26: Error: missing operand +.*:27: Error: missing operand +.*:27: Error: bad expression +.*:27: Error: syntax error; missing '\)' after base register +.*:28: Error: bad expression +.*:28: Error: operand out of range \(0 is not between 1 and 256\) +.*:28: Error: operand out of range \(32 is not between 0 and 15\) +.*:28: Error: syntax error; missing '\)' after base register +.*:28: Error: syntax error; expected ',' +.*:28: Error: bad expression +.*:28: Error: found 'r', expected: '\)' +.*:28: Error: syntax error; missing '\)' after base register +.*:28: Error: junk at end of line: `r2\)' +.*:29: Error: syntax error; missing '\(' after displacement +.*:30: Error: invalid length field specified +.*:33: Error: bad expression +.*:33: Error: syntax error; missing '\)' after base register +.*:34: Error: bad expression +.*:34: Error: syntax error; missing '\)' after base register +.*:35: Error: bad expression +.*:35: Error: syntax error; missing '\)' after base register +.*:36: Error: bad expression +.*:36: Error: syntax error; missing '\)' after base register +.*:37: Error: bad expression +.*:37: Error: syntax error; missing '\)' after base register +.*:38: Error: bad expression +.*:38: Error: syntax error; missing '\)' after base register +.*:39: Error: bad expression +.*:39: Error: syntax error; missing '\)' after base register +.*:39: Error: bad expression +.*:39: Error: syntax error; missing '\)' after base register +.*:40: Error: bad expression +.*:40: Error: syntax error; missing '\)' after base register +.*:41: Error: bad expression +.*:41: Error: syntax error; missing '\)' after base register +.*:42: Error: operand out of range \(0 is not between 1 and 16\) +.*:43: Error: missing operand +.*:44: Error: missing operand +.*:45: Error: missing operand +.*:45: Error: bad expression +.*:45: Error: syntax error; missing '\)' after base register +.*:46: Error: bad expression +.*:46: Error: operand out of range \(0 is not between 1 and 16\) +.*:46: Error: operand out of range \(32 is not between 0 and 15\) +.*:46: Error: syntax error; missing '\)' after base register +.*:46: Error: syntax error; expected ',' +.*:46: Error: found ',', expected: '\)' +.*:47: Error: syntax error; missing '\(' after displacement +.*:48: Error: operand out of range \(0 is not between 1 and 16\) +.*:49: Error: missing operand +.*:50: Error: missing operand +.*:51: Error: missing operand +.*:51: Error: bad expression +.*:51: Error: syntax error; missing '\)' after base register +.*:52: Error: bad expression +.*:52: Error: operand out of range \(0 is not between 1 and 16\) +.*:52: Error: syntax error; expected ',' +.*:53: Error: syntax error; missing '\(' after displacement +.*:54: Error: operand out of range \(0 is not between 1 and 16\) +.*:54: Error: operand out of range \(0 is not between 1 and 16\) +.*:55: Error: missing operand +.*:55: Error: missing operand +.*:56: Error: missing operand +.*:56: Error: missing operand +.*:57: Error: missing operand +.*:57: Error: bad expression +.*:57: Error: syntax error; missing '\)' after base register +.*:57: Error: missing operand +.*:57: Error: bad expression +.*:57: Error: syntax error; missing '\)' after base register +.*:58: Error: bad expression +.*:58: Error: operand out of range \(0 is not between 1 and 16\) +.*:58: Error: operand out of range \(32 is not between 0 and 15\) +.*:58: Error: syntax error; missing '\)' after base register +.*:58: Error: syntax error; expected ',' +.*:58: Error: bad expression +.*:58: Error: missing '\)' +.*:58: Error: operand out of range \(0 is not between 1 and 16\) +.*:58: Error: syntax error; expected ',' +.*:59: Error: syntax error; missing '\(' after displacement +.*:59: Error: syntax error; missing '\(' after displacement +.*:62: Error: bad expression +.*:62: Error: syntax error; missing '\)' after base register +.*:63: Error: bad expression +.*:63: Error: syntax error; missing '\)' after base register +.*:64: Error: bad expression +.*:64: Error: syntax error; missing '\)' after base register +.*:65: Error: bad expression +.*:65: Error: syntax error; missing '\)' after base register +.*:66: Error: bad expression +.*:66: Error: syntax error; missing '\)' after base register diff --git a/gas/testsuite/gas/s390/zarch-base-index-0-err.s b/gas/testsuite/gas/s390/zarch-base-index-0-err.s new file mode 100644 index 000000000000..175cc90b2699 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-base-index-0-err.s @@ -0,0 +1,66 @@ +.text +foo: + +# D1(B1),I2 + mvi 16(),32 # syntax error: empty parentheses + +# R1,D2(X2,B2) + a %r1,16(%r2,) # syntax error: explicitly omitted base + a %r1,16(%r0,) # syntax error: explicitly omitted base + a %r1,16(0,) # syntax error: explicitly omitted base + a %r1,16(,) # syntax error: explicitly omitted index & base + a %r1,16() # syntax error: empty parentheses + +# D1(L1,B1),D2(B2) + mvc 16(1,),32(%r2) # syntax error: explicitly omitted base + mvc 16(1,%r1),32() # syntax error: empty parentheses + mvc 16(1,%r0),32() # syntax error: empty parentheses + mvc 16(1,0),32() # syntax error: empty parentheses + mvc 16(1,),32(%r0) # syntax error: explicitly omitted base + mvc 16(1,),32(0) # syntax error: explicitly omitted base + mvc 16(1,),32() # syntax error: explicitly omitted base & empty parentheses + mvc 16(1,),32 # syntax error: explicitly omitted base + mvc 16(1),32() # syntax error: empty parentheses + mvc 16(0,%r1),32(%r2) # syntax error: length 0 + mvc 16(,%r1),32(%r2) # syntax error: explicitly omitted length + mvc 16(,1),32(%r2) # syntax error: explicitly omitted length + mvc 16(,),32(%r2) # syntax error: explicitly omitted length & base + mvc 16(),32(%r2) # syntax error: empty parenthesis + mvc 16,32(%r2) # syntax error: missing length + mvc 16(%r1),32(%r2) # syntax error: omitted length + +# D1(L1,B1),D2(L2,B2) + unpk 16(1,),32(2,%r2) # syntax error: explicitly omitted base + unpk 16(1,%r1),32(2,) # syntax error: explicitly omitted base + unpk 16(1,%r0),32(2,) # syntax error: explicitly omitted base + unpk 16(1,0),32(2,) # syntax error: explicitly omitted base + unpk 16(1,),32(2,%r0) # syntax error: explicitly omitted base + unpk 16(1,),32(2,0) # syntax error: explicitly omitted base + unpk 16(1,),32(2,) # syntax error: explicitly omitted base + unpk 16(1,),32(2) # syntax error: explicitly omitted base + unpk 16(1),32(2,) # syntax error: explicitly omitted base + unpk 16(0,%r1),32(2,%r2) # syntax error: length 0 + unpk 16(,%r1),32(2,%r2) # syntax error: explicitly omitted length + unpk 16(,1),32(2,%r2) # syntax error: explicitly omitted length + unpk 16(,),32(2,%r2) # syntax error: explicitly omitted length & base + unpk 16(),32(2,%r2) # syntax error: empty parenthesis + unpk 16,32(2,%r2) # syntax error: missing length + unpk 16(1,%r1),32(0,%r2) # syntax error: length 0 + unpk 16(1,%r1),32(,%r2) # syntax error: explicitly omitted length + unpk 16(1,%r1),32(,2) # syntax error: explicitly omitted length + unpk 16(1,%r1),32(,) # syntax error: explicitly omitted length & base + unpk 16(1,%r1),32() # syntax error: empty parenthesis + unpk 16(1,%r1),32 # syntax error: missing length + unpk 16(0,%r1),32(0,%r2) # syntax error: lengths 0 + unpk 16(,%r1),32(,%r2) # syntax error: explicitly omitted length + unpk 16(,1),32(,2) # syntax error: explicitly omitted length + unpk 16(,),32(,) # syntax error: explicitly omitted length & base + unpk 16(),32() # syntax error: empty parentheses + unpk 16,32 # syntax error: missing lengths + +# V1,D2(VX2,B2),M3 + vgef %v1,16(%v2,),0 # syntax error: explicitly omitted base + vgef %v1,16(%v0,),0 # syntax error: explicitly omitted base + vgef %v1,16(0,),0 # syntax error: explicitly omitted base + vgef %v1,16(,),0 # syntax error: explicitly omitted index & base + vgef %v1,16(),0 # syntax error: empty parentheses diff --git a/gas/testsuite/gas/s390/zarch-base-index-0.d b/gas/testsuite/gas/s390/zarch-base-index-0.d new file mode 100644 index 000000000000..e6266040c8e7 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-base-index-0.d @@ -0,0 +1,84 @@ +#name: s390x base/index register 0 +#objdump: -dr + +.*: +file format .* + +Disassembly of section .text: + +.* : +.*: 92 20 10 10 [ ]*mvi 16\(%r1\),32 +.*: 92 20 00 10 [ ]*mvi 16,32 +.*: 92 20 00 10 [ ]*mvi 16,32 +.*: 92 20 00 10 [ ]*mvi 16,32 +.*: 92 20 00 00 [ ]*mvi 0,32 +.*: 92 00 00 00 [ ]*mvi 0,0 +.*: 5a 12 30 10 [ ]*a %r1,16\(%r2,%r3\) +.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) +.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) +.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) +.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\) +.*: 5a 10 00 10 [ ]*a %r1,16 +.*: 5a 10 00 10 [ ]*a %r1,16 +.*: 5a 10 00 10 [ ]*a %r1,16 +.*: 5a 10 00 10 [ ]*a %r1,16 +.*: 5a 10 00 10 [ ]*a %r1,16 +.*: 5a 10 00 10 [ ]*a %r1,16 +.*: 5a 10 00 10 [ ]*a %r1,16 +.*: 5a 10 00 10 [ ]*a %r1,16 +.*: 5a 10 00 00 [ ]*a %r1,0 +.*: 5a 00 00 00 [ ]*a %r0,0 +.*: 5a 00 00 00 [ ]*a %r0,0 +.*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) +.*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 +.*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 +.*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,%r0\),0 +.*: f3 01 10 10 20 20 [ ]*unpk 16\(1,%r1\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) +.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,%r0\),0\(2,%r0\) +.*: e7 12 30 10 00 13 [ ]*vgef %v1,16\(%v2,%r3\),0 +.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 +.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 +.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 +.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0 +.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 +.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 +.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 +.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 +.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 +.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 +.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 +.*: e7 00 00 10 00 13 [ ]*vgef %v0,16,0 +.*: e7 00 00 10 00 13 [ ]*vgef %v0,16,0 +.*: e7 00 00 00 00 13 [ ]*vgef %v0,0,0 +.*: 07 07 [ ]*nopr %r7 diff --git a/gas/testsuite/gas/s390/zarch-base-index-0.s b/gas/testsuite/gas/s390/zarch-base-index-0.s new file mode 100644 index 000000000000..15c792d776fa --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-base-index-0.s @@ -0,0 +1,116 @@ +.text +foo: + +# D1(B1),I2 + mvi 16(%r1),32 + mvi 16(%r0),32 + mvi 16(0),32 +# mvi 16(),32 # syntax error: empty parentheses + mvi 16,32 + mvi 0,32 + mvi 0,0 + +# R1,D2(X2,B2) + a %r1,16(%r2,%r3) + a %r1,16(%r0,%r3) + a %r1,16(0,%r3) + a %r1,16(,%r3) + a %r1,16(%r3) + a %r1,16(%r2,%r0) + a %r1,16(%r2,0) +# a %r1,16(%r2,) # syntax error: explicitly omitted base + a %r1,16(%r0,%r0) + a %r1,16(%r0,0) +# a %r1,16(%r0,) # syntax error: explicitly omitted base + a %r1,16(0,%r0) + a %r1,16(0,0) +# a %r1,16(0,) # syntax error: explicitly omitted base + a %r1,16(0,%r0) + a %r1,16(,%r0) + a %r1,16(,0) +# a %r1,16(,) # syntax error: explicitly omitted index & base +# a %r1,16() # syntax error: empty parentheses + a %r1,16 + a %r1,0 + a %r0,0 + a 0,0 + +# D1(L1,B1),D2(B2) + mvc 16(1,%r1),32(%r2) + mvc 16(1,%r0),32(%r2) + mvc 16(1,0),32(%r2) +# mvc 16(1,),32(%r2) # syntax error: explicitly omitted base + mvc 16(1),32(%r2) + mvc 16(1,%r1),32(%r0) + mvc 16(1,%r1),32(0) +# mvc 16(1,%r1),32() # syntax error: empty parentheses + mvc 16(1,%r1),32 + mvc 16(1,%r0),32(%r0) + mvc 16(1,%r0),32(0) +# mvc 16(1,%r0),32() # syntax error: empty parentheses + mvc 16(1,%r0),32 + mvc 16(1,0),32(%r0) + mvc 16(1,0),32(0) +# mvc 16(1,0),32() # syntax error: empty parentheses + mvc 16(1,0),32 +# mvc 16(1,),32(%r0) # syntax error: explicitly omitted base +# mvc 16(1,),32(0) # syntax error: explicitly omitted base +# mvc 16(1,),32() # syntax error: explicitly omitted base & empty parentheses +# mvc 16(1,),32 # syntax error: explicitly omitted base + mvc 16(1),32(%r0) + mvc 16(1),32(0) +# mvc 16(1),32() # syntax error: empty parentheses + mvc 16(1),32 + mvc 0(1),0 + +# D1(L1,B1),D2(L2,B2) + unpk 16(1,%r1),32(2,%r2) + unpk 16(1,%r0),32(2,%r2) + unpk 16(1,0),32(2,%r2) +# unpk 16(1,),32(2,%r2) # syntax error: explicitly omitted base + unpk 16(1),32(2,%r2) + unpk 16(1,%r1),32(2,%r0) + unpk 16(1,%r1),32(2,0) +# unpk 16(1,%r1),32(2,) # syntax error: explicitly omitted base + unpk 16(1,%r1),32(2) + unpk 16(1,%r0),32(2,%r0) + unpk 16(1,%r0),32(2,0) +# unpk 16(1,%r0),32(2,) # syntax error: explicitly omitted base + unpk 16(1,%r0),32(2) + unpk 16(1,0),32(2,%r0) + unpk 16(1,0),32(2,0) +# unpk 16(1,0),32(2,) # syntax error: explicitly omitted base + unpk 16(1,0),32(2) +# unpk 16(1,),32(2,%r0) # syntax error: explicitly omitted base +# unpk 16(1,),32(2,0) # syntax error: explicitly omitted base +# unpk 16(1,),32(2,) # syntax error: explicitly omitted base +# unpk 16(1,),32(2) # syntax error: explicitly omitted base + unpk 16(1),32(2,%r0) + unpk 16(1),32(2,0) +# unpk 16(1),32(2,) # syntax error: explicitly omitted base + unpk 16(1),32(2) + unpk 0(1),0(2) + +# V1,D2(VX2,B2),M3 + vgef %v1,16(%v2,%r3),0 + vgef %v1,16(%v0,%r3),0 + vgef %v1,16(0,%r3),0 + vgef %v1,16(,%r3),0 + vgef %v1,16(%r3),0 + vgef %v1,16(%v2,%r0),0 + vgef %v1,16(%v2,0),0 +# vgef %v1,16(%v2,),0 # syntax error: explicitly omitted base + vgef %v1,16(%v0,%r0),0 + vgef %v1,16(%v0,0),0 +# vgef %v1,16(%v0,),0 # syntax error: explicitly omitted base + vgef %v1,16(0,%r0),0 + vgef %v1,16(0,0),0 +# vgef %v1,16(0,),0 # syntax error: explicitly omitted base + vgef %v1,16(,%r0),0 + vgef %v1,16(,0),0 +# vgef %v1,16(,),0 # syntax error: explicitly omitted index & base +# vgef %v1,16(),0 # syntax error: empty parentheses + vgef %v1,16,0 + vgef %v0,16,0 + vgef 0,16,0 + vgef 0,0,0 diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c index 0db4158262f3..a4cba77c6aeb 100644 --- a/opcodes/s390-dis.c +++ b/opcodes/s390-dis.c @@ -204,10 +204,11 @@ s390_print_insn_with_opcode (bfd_vma memaddr, union operand_value val = s390_extract_operand (buffer, operand); unsigned long flags = operand->flags; + /* Omit index register 0. */ if ((flags & S390_OPERAND_INDEX) && val.u == 0) continue; - if ((flags & S390_OPERAND_BASE) && - val.u == 0 && separator == '(') + /* Omit base register 0, if no or omitted index register 0. */ + if ((flags & S390_OPERAND_BASE) && val.u == 0 && separator == '(') { separator = ','; continue; From patchwork Thu Feb 15 15:58:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 201607 Return-Path: Delivered-To: ouuuleilei@gmail.com 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Thu, 15 Feb 2024 15:58:29 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:29 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 08/14] s390: Add test case for disassembler option warn-areg-zero Date: Thu, 15 Feb 2024 16:58:15 +0100 Message-Id: <20240215155821.4065623-9-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4N9yhqdt62M9qPkAcycVoRjYPYJdBiRh X-Proofpoint-ORIG-GUID: 4N9yhqdt62M9qPkAcycVoRjYPYJdBiRh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 spamscore=0 mlxlogscore=588 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981407425761390 X-GMAIL-MSGID: 1790981407425761390 gas/ * testsuite/gas/s390/s390.exp: Add test cases for s390-specific assembler option "warn-areg-zero". * testsuite/gas/s390/zarch-warn-areg-zero.s: Likewise. * testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/testsuite/gas/s390/s390.exp | 1 + gas/testsuite/gas/s390/zarch-warn-areg-zero.l | 65 ++++++++++ gas/testsuite/gas/s390/zarch-warn-areg-zero.s | 116 ++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 gas/testsuite/gas/s390/zarch-warn-areg-zero.l create mode 100644 gas/testsuite/gas/s390/zarch-warn-areg-zero.s diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp index f5798b4778e1..613487fc453c 100644 --- a/gas/testsuite/gas/s390/s390.exp +++ b/gas/testsuite/gas/s390/s390.exp @@ -60,4 +60,5 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { run_list_test "zarch-omitted-base-index-err" "" run_dump_test "zarch-base-index-0" "{as -m64}" run_list_test "zarch-base-index-0-err" "" + run_list_test "zarch-warn-areg-zero" "-m64 -mwarn-areg-zero" } diff --git a/gas/testsuite/gas/s390/zarch-warn-areg-zero.l b/gas/testsuite/gas/s390/zarch-warn-areg-zero.l new file mode 100644 index 000000000000..decf896aecc7 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-warn-areg-zero.l @@ -0,0 +1,65 @@ +.*: Assembler messages: +.*:6: Warning: base register specified but zero +.*:7: Warning: base register specified but zero +.*:15: Warning: index register specified but zero +.*:16: Warning: index register specified but zero +.*:19: Warning: base register specified but zero +.*:20: Warning: base register specified but zero +.*:22: Warning: index register specified but zero +.*:22: Warning: base register specified but zero +.*:23: Warning: index register specified but zero +.*:23: Warning: base register specified but zero +.*:25: Warning: index register specified but zero +.*:25: Warning: base register specified but zero +.*:26: Warning: index register specified but zero +.*:26: Warning: base register specified but zero +.*:28: Warning: index register specified but zero +.*:28: Warning: base register specified but zero +.*:29: Warning: base register specified but zero +.*:30: Warning: base register specified but zero +.*:40: Warning: base register specified but zero +.*:41: Warning: base register specified but zero +.*:44: Warning: base register specified but zero +.*:45: Warning: base register specified but zero +.*:48: Warning: base register specified but zero +.*:48: Warning: base register specified but zero +.*:49: Warning: base register specified but zero +.*:49: Warning: base register specified but zero +.*:51: Warning: base register specified but zero +.*:52: Warning: base register specified but zero +.*:52: Warning: base register specified but zero +.*:53: Warning: base register specified but zero +.*:53: Warning: base register specified but zero +.*:55: Warning: base register specified but zero +.*:60: Warning: base register specified but zero +.*:61: Warning: base register specified but zero +.*:68: Warning: base register specified but zero +.*:69: Warning: base register specified but zero +.*:72: Warning: base register specified but zero +.*:73: Warning: base register specified but zero +.*:76: Warning: base register specified but zero +.*:76: Warning: base register specified but zero +.*:77: Warning: base register specified but zero +.*:77: Warning: base register specified but zero +.*:79: Warning: base register specified but zero +.*:80: Warning: base register specified but zero +.*:80: Warning: base register specified but zero +.*:81: Warning: base register specified but zero +.*:81: Warning: base register specified but zero +.*:83: Warning: base register specified but zero +.*:88: Warning: base register specified but zero +.*:89: Warning: base register specified but zero +.*:96: Warning: index register specified but zero +.*:97: Warning: index register specified but zero +.*:100: Warning: base register specified but zero +.*:101: Warning: base register specified but zero +.*:103: Warning: index register specified but zero +.*:103: Warning: base register specified but zero +.*:104: Warning: index register specified but zero +.*:104: Warning: base register specified but zero +.*:106: Warning: index register specified but zero +.*:106: Warning: base register specified but zero +.*:107: Warning: index register specified but zero +.*:107: Warning: base register specified but zero +.*:109: Warning: base register specified but zero +.*:110: Warning: base register specified but zero diff --git a/gas/testsuite/gas/s390/zarch-warn-areg-zero.s b/gas/testsuite/gas/s390/zarch-warn-areg-zero.s new file mode 100644 index 000000000000..15c792d776fa --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-warn-areg-zero.s @@ -0,0 +1,116 @@ +.text +foo: + +# D1(B1),I2 + mvi 16(%r1),32 + mvi 16(%r0),32 + mvi 16(0),32 +# mvi 16(),32 # syntax error: empty parentheses + mvi 16,32 + mvi 0,32 + mvi 0,0 + +# R1,D2(X2,B2) + a %r1,16(%r2,%r3) + a %r1,16(%r0,%r3) + a %r1,16(0,%r3) + a %r1,16(,%r3) + a %r1,16(%r3) + a %r1,16(%r2,%r0) + a %r1,16(%r2,0) +# a %r1,16(%r2,) # syntax error: explicitly omitted base + a %r1,16(%r0,%r0) + a %r1,16(%r0,0) +# a %r1,16(%r0,) # syntax error: explicitly omitted base + a %r1,16(0,%r0) + a %r1,16(0,0) +# a %r1,16(0,) # syntax error: explicitly omitted base + a %r1,16(0,%r0) + a %r1,16(,%r0) + a %r1,16(,0) +# a %r1,16(,) # syntax error: explicitly omitted index & base +# a %r1,16() # syntax error: empty parentheses + a %r1,16 + a %r1,0 + a %r0,0 + a 0,0 + +# D1(L1,B1),D2(B2) + mvc 16(1,%r1),32(%r2) + mvc 16(1,%r0),32(%r2) + mvc 16(1,0),32(%r2) +# mvc 16(1,),32(%r2) # syntax error: explicitly omitted base + mvc 16(1),32(%r2) + mvc 16(1,%r1),32(%r0) + mvc 16(1,%r1),32(0) +# mvc 16(1,%r1),32() # syntax error: empty parentheses + mvc 16(1,%r1),32 + mvc 16(1,%r0),32(%r0) + mvc 16(1,%r0),32(0) +# mvc 16(1,%r0),32() # syntax error: empty parentheses + mvc 16(1,%r0),32 + mvc 16(1,0),32(%r0) + mvc 16(1,0),32(0) +# mvc 16(1,0),32() # syntax error: empty parentheses + mvc 16(1,0),32 +# mvc 16(1,),32(%r0) # syntax error: explicitly omitted base +# mvc 16(1,),32(0) # syntax error: explicitly omitted base +# mvc 16(1,),32() # syntax error: explicitly omitted base & empty parentheses +# mvc 16(1,),32 # syntax error: explicitly omitted base + mvc 16(1),32(%r0) + mvc 16(1),32(0) +# mvc 16(1),32() # syntax error: empty parentheses + mvc 16(1),32 + mvc 0(1),0 + +# D1(L1,B1),D2(L2,B2) + unpk 16(1,%r1),32(2,%r2) + unpk 16(1,%r0),32(2,%r2) + unpk 16(1,0),32(2,%r2) +# unpk 16(1,),32(2,%r2) # syntax error: explicitly omitted base + unpk 16(1),32(2,%r2) + unpk 16(1,%r1),32(2,%r0) + unpk 16(1,%r1),32(2,0) +# unpk 16(1,%r1),32(2,) # syntax error: explicitly omitted base + unpk 16(1,%r1),32(2) + unpk 16(1,%r0),32(2,%r0) + unpk 16(1,%r0),32(2,0) +# unpk 16(1,%r0),32(2,) # syntax error: explicitly omitted base + unpk 16(1,%r0),32(2) + unpk 16(1,0),32(2,%r0) + unpk 16(1,0),32(2,0) +# unpk 16(1,0),32(2,) # syntax error: explicitly omitted base + unpk 16(1,0),32(2) +# unpk 16(1,),32(2,%r0) # syntax error: explicitly omitted base +# unpk 16(1,),32(2,0) # syntax error: explicitly omitted base +# unpk 16(1,),32(2,) # syntax error: explicitly omitted base +# unpk 16(1,),32(2) # syntax error: explicitly omitted base + unpk 16(1),32(2,%r0) + unpk 16(1),32(2,0) +# unpk 16(1),32(2,) # syntax error: explicitly omitted base + unpk 16(1),32(2) + unpk 0(1),0(2) + +# V1,D2(VX2,B2),M3 + vgef %v1,16(%v2,%r3),0 + vgef %v1,16(%v0,%r3),0 + vgef %v1,16(0,%r3),0 + vgef %v1,16(,%r3),0 + vgef %v1,16(%r3),0 + vgef %v1,16(%v2,%r0),0 + vgef %v1,16(%v2,0),0 +# vgef %v1,16(%v2,),0 # syntax error: explicitly omitted base + vgef %v1,16(%v0,%r0),0 + vgef %v1,16(%v0,0),0 +# vgef %v1,16(%v0,),0 # syntax error: explicitly omitted base + vgef %v1,16(0,%r0),0 + vgef %v1,16(0,0),0 +# vgef %v1,16(0,),0 # syntax error: explicitly omitted base + vgef %v1,16(,%r0),0 + vgef %v1,16(,0),0 +# vgef %v1,16(,),0 # syntax error: explicitly omitted index & base +# vgef %v1,16(),0 # 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Thu, 15 Feb 2024 15:58:29 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:29 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 09/14] s390: Revise s390-specific assembler option descriptions Date: Thu, 15 Feb 2024 16:58:16 +0100 Message-Id: <20240215155821.4065623-10-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 2HQNScn21cmv8bL4PcpPAYrrspIeIkuD X-Proofpoint-GUID: 2HQNScn21cmv8bL4PcpPAYrrspIeIkuD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 mlxlogscore=908 bulkscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981638600800333 X-GMAIL-MSGID: 1790981638600800333 Reorder, reword, and complete the s390-specific option descriptions. Align the formatting of s390-specific assembler options to that of the general assembler options in "as --help". While at it change a warning message to use the term "z/Architecture" instead of the deprecated "esame" (ESA Modal Extensions or ESAME) one. gas/ * config/tc-s390.c: Revise s390-specific assembler option descriptions. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/config/tc-s390.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 9aebd8ca91e5..eef8428b40a6 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -475,15 +475,23 @@ void md_show_usage (FILE *stream) { fprintf (stream, _("\ - S390 options:\n\ - -mregnames Allow symbolic names for registers\n\ - -mwarn-areg-zero Warn about zero base/index registers\n\ - -mno-regnames Do not allow symbolic names for registers\n\ - -m31 Set file format to 31 bit format\n\ - -m64 Set file format to 64 bit format\n")); +S390 options:\n\ + -m31 generate 31-bit file format (31/32 bit word size)\n\ + -m64 generate 64-bit file format (64 bit word size)\n\ + -mesa assemble for Enterprise System Architecture/390\n\ + -mzarch assemble for z/Architecture\n\ + -march= assemble for processor \n\ + -mregnames allow symbolic names for registers\n\ + -mno-regnames do not allow symbolic names for registers\n\ + -mwarn-areg-zero warn about base/index register zero\n\ +")); fprintf (stream, _("\ - -V print assembler version number\n\ - -Qy, -Qn ignored\n")); + -V print assembler version number\n\ + -Qy, -Qn ignored\n")); + fprintf (stream, _("\ +Deprecated S390 options:\n\ + -Aesa assemble for processor IBM S/390 G5 (g5/arch3)\n\ + -Aesame assemble for processor IBM zSeries 900 (z900/arch5)\n")); } /* Generate the hash table mapping mnemonics to struct s390_opcode. @@ -557,9 +565,9 @@ md_begin (void) const struct s390_opcode *op; const struct s390_opcode *op_end; - /* Give a warning if the combination -m64-bit and -Aesa is used. */ + /* Give a warning if the combination -m64 and -Aesa is used. */ if (s390_arch_size == 64 && current_cpu < S390_OPCODE_Z900) - as_warn (_("The 64 bit file format is used without esame instructions.")); + as_warn (_("The 64-bit file format is used without z/Architecture instructions.")); s390_cie_data_alignment = -s390_arch_size / 8; From patchwork Thu Feb 15 15:58:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 201612 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp499156dyb; Thu, 15 Feb 2024 08:04:03 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUIODBtHBTlvHQkYp+OgoS9TzkhoBxiiyROTQ9XHP4nVIXhtUgRCOa1VE4gN+h6iTFUsIiTGUctmM79UZCjkJWhYs9u7A== X-Google-Smtp-Source: AGHT+IHg5nJKkiJbp8qmD+OwXOZ2+Yo8buQ6sA2+Z93jpw4/Z/GmofK9Fd/iFOlnScr3BHG5aUpU X-Received: by 2002:a05:620a:22d2:b0:785:bfc5:234a with SMTP id o18-20020a05620a22d200b00785bfc5234amr1818089qki.23.1708013043181; Thu, 15 Feb 2024 08:04:03 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708013043; cv=pass; d=google.com; s=arc-20160816; b=BQ+oivD/mwFz506U5gllZh7jC4laYG70J1JdPod1vnHCNiHXZ+T49/Pb1XA2qyD2AA 0D0X62n3X0Qs0XGlQpqxeNBB+xq1VhoycYV98n3iJgjv0weaBdrn8Osml7BkLI1xGfdR sIyrZyBO/yfc/uKWxmpojizyAfabXt74yX4nsY5wLkU1ekmo0y8rl4vDo8QnMyC0D1sL lpB8mQ+kkTyuvMkStuZN4vuecCo7axNNPf7zt8eSPPBWB8z7Une/jLQLVX9SCh7N1Wgx 8AogAhlfJZCwYHrdm+g950AZuuAwo9ILVZWvE2J+P5MwgriVUkAZLg+iervCJhZ+VbK3 vJjQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=dUtrh93pSU3wH6DFoe5IxCc9o9nHBf8X0qd7O0YRaLw=; fh=6sWHPsCQUoLz5ZcbqIohOjwdU7jjRT/citiAJwaEf0c=; b=eECZwPiBIJUuNYzsfJCsaiv3PAczglc0oUcrKDQ1nUOPmGboCZ1KfA9gv2DP7n5SsK NZb2KN5mn0PayMvYv1zyUW27nWe6mPBVOsfxScU50tcQROGt+Muo14/BNdG5jA7ZXkCL eaf4gH4Qm5A7ratOR00y7PrOmdxwNepwXZH51pHPQco9nJyfLwDyPiapE0ZnIoq9mExc LxdRdA0VTAgoCH9Bj8NoAD/lIoB4JgPCaoByN9qlrXKBqsFxE3om9SQhoddx7yFsf29P H2HhQcDc5Pe6VhX1nMMAg2MhG4OdU8T3I+3KNjyUJspttpXX7tzCGvDJeApeVCwQUGza Ta1g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=qeG7CCxi; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. 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Thu, 15 Feb 2024 15:58:29 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:29 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 10/14] s390: Warn when register name type does not match operand Date: Thu, 15 Feb 2024 16:58:17 +0100 Message-Id: <20240215155821.4065623-11-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 7N-d44Agx3ctHXTguKB-ZeiqQEjkcBTT X-Proofpoint-GUID: 7N-d44Agx3ctHXTguKB-ZeiqQEjkcBTT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_15,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 phishscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981484455648857 X-GMAIL-MSGID: 1790981484455648857 Print a warning message when the register type of a specified register name does not match with the operand's register type: operand {#}: expected {access|control|floating-point|general|vector} register name [as {base|index} register] Introduce a s390-specific assembler option "warn-regtype-mismatch" with the values "strict", "relaxed", and "no" as well as an option "no-warn-regtype-mismatch" which control whether the assembler performs register name type checks and generates above warning messages. warn-regtype-mismatch=strict: Perform strict register name type checks. warn-regtype-mismatch=relaxed: Perform relaxed register name type checks, which allow floating-point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating-point register (FPR) operands. This is acceptable as the FPRs are embedded into the lower halves of the VRs. Make "relaxed" the default, as GCC generates assembler code using FPR and VR interchangeably, which would cause assembler warnings to be generated with "strict". warn-regtype-mismatch=no: no-warn-regtype-mismatch: Disable any register name type checks. Tag .insn pseudo mnemonics as such, to skip register name type checks on those. They need to be skipped, as there do not exist .insn pseudo mnemonics for every possible operand register type combination. Keep track of the currently parsed operand number to provide it as reference in warning messages. To verify that the introduction of this change does not unnecessarily affect the compilation of existing code the GNU Binutils, GNU C Library, and Linux Kernel have been build with the new assembler, verifying that the assembler did not generate any of the new warning messages. gas/ * config/tc-s390.c: Handle new assembler options "[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate parsed register expressions with register type. Keep track of operand number being parsed. Print warning message in case of register type mismatch between instruction operand and parsed register expression. * doc/as.texi: Document new s390-specific assembler options "[no-]warn-regtype-mismatch[=strict|relaxed|no]". * NEWS: Mention new s390-specific register name type checks and related assembler option "warn-regtype-mismatch=strict| relaxed|no". * testsuite/gas/s390/s390.exp: Add test cases for new assembler option "warn-regtype-mismatch={strict|relaxed}". * testsuite/gas/s390/esa-g5.s: Fix register types in tests for didbr, diebr, tbdr, and tbedr. * testsuite/gas/s390/zarch-z13.s: Fix register types in tests for vgef, vgeg, vscef, and vsceg. * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s: Tests for assembler option "warn-regtype-mismatch=strict". * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l: Likewise. * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s: Tests for assembler option "warn-regtype-mismatch=relaxed". * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update test cases for assembler option "warn-regtype-mismatch" defaulting to "relaxed". * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. include/ * opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add instruction flag to tag .insn pseudo-mnemonics. opcodes/ * s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as such. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/NEWS | 6 + gas/config/tc-s390.c | 108 ++++++++++++++++++ gas/doc/as.texi | 20 ++++ gas/testsuite/gas/s390/esa-g5.s | 8 +- gas/testsuite/gas/s390/s390.exp | 2 + .../gas/s390/zarch-omitted-base-index-err.l | 29 ++--- .../gas/s390/zarch-omitted-base-index-err.s | 1 + .../zarch-warn-regtype-mismatch-relaxed.l | 15 +++ .../zarch-warn-regtype-mismatch-relaxed.s | 7 ++ .../s390/zarch-warn-regtype-mismatch-strict.l | 15 +++ .../s390/zarch-warn-regtype-mismatch-strict.s | 7 ++ gas/testsuite/gas/s390/zarch-z13.s | 8 +- include/opcode/s390.h | 3 + opcodes/s390-opc.c | 62 +++++----- 14 files changed, 238 insertions(+), 53 deletions(-) create mode 100644 gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l create mode 100644 gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s create mode 100644 gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l create mode 100644 gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s diff --git a/gas/NEWS b/gas/NEWS index 6494acfa3ea4..e5572da5f7b8 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,11 @@ -*- text -*- +* Warn when a register name type does not match the operand type on s390. + Add support for s390-specific option "warn-regtype-mismatch=[strict|relaxed| + no]" to override the register name type check behavior. The default + is "relaxed", which allows floating-point and vector register names to be + used interchangeably. + Changes in 2.42: * Add support for AMD znver5 processor. diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index eef8428b40a6..daa44bb3f816 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -60,6 +60,20 @@ static bool reg_names_p = TARGET_REG_NAMES_P; /* Set to TRUE if we want to warn about zero base/index registers. */ static bool warn_areg_zero = false; +/* Whether to warn about register name type check mismatches. */ +#ifndef S390_REGTYPE_CHECK +#define S390_REGTYPE_CHECK S390_REGTYPE_CHECK_RELAXED +#endif + +enum s390_regtype_check { + S390_REGTYPE_CHECK_NONE = 0, /* No register name type checks. */ + S390_REGTYPE_CHECK_RELAXED, /* Relaxed register name type checks. */ + S390_REGTYPE_CHECK_STRICT /* Strict register name type checks. */ +}; + +/* Whether to warn about register name type check mismatches. */ +static enum s390_regtype_check warn_regtype_mismatch = S390_REGTYPE_CHECK; + /* Generic assembler global variables which must be defined by all targets. */ @@ -110,6 +124,16 @@ const pseudo_typeS md_pseudo_table[] = { NULL, NULL, 0 } }; +/* Register types. */ +enum s390_register_type + { + S390_REGTYPE_AR, /* Access register. */ + S390_REGTYPE_CR, /* Control register. */ + S390_REGTYPE_FPR, /* Floating-point register. */ + S390_REGTYPE_GR, /* General register. */ + S390_REGTYPE_VR, /* Vector register. */ + }; + /* Given NAME, find the register number associated with that name, return the integer value associated with the given name or -1 on failure. */ @@ -180,6 +204,26 @@ register_name (expressionS *expressionP) { expressionP->X_op = O_register; expressionP->X_add_number = reg_number; + switch (name[0]) + { + case 'a': + expressionP->X_md = S390_REGTYPE_AR; + break; + case 'c': + expressionP->X_md = S390_REGTYPE_CR; + break; + case 'f': + expressionP->X_md = S390_REGTYPE_FPR; + break; + case 'r': + expressionP->X_md = S390_REGTYPE_GR; + break; + case 'v': + expressionP->X_md = S390_REGTYPE_VR; + break; + default: + expressionP->X_md = 0; + } /* Make the rest nice. */ expressionP->X_add_symbol = NULL; @@ -415,6 +459,18 @@ md_parse_option (int c, const char *arg) else if (arg != NULL && strcmp (arg, "warn-areg-zero") == 0) warn_areg_zero = true; + else if (arg != NULL && strcmp (arg, "warn-regtype-mismatch=strict") == 0) + warn_regtype_mismatch = S390_REGTYPE_CHECK_STRICT; + + else if (arg != NULL && strcmp (arg, "warn-regtype-mismatch=relaxed") == 0) + warn_regtype_mismatch = S390_REGTYPE_CHECK_RELAXED; + + else if (arg != NULL && strcmp (arg, "warn-regtype-mismatch=no") == 0) + warn_regtype_mismatch = S390_REGTYPE_CHECK_NONE; + + else if (arg != NULL && strcmp (arg, "no-warn-regtype-mismatch") == 0) + warn_regtype_mismatch = S390_REGTYPE_CHECK_NONE; + else if (arg != NULL && strcmp (arg, "31") == 0) s390_arch_size = 32; @@ -484,6 +540,13 @@ S390 options:\n\ -mregnames allow symbolic names for registers\n\ -mno-regnames do not allow symbolic names for registers\n\ -mwarn-areg-zero warn about base/index register zero\n\ + -mwarn-regtype-mismatch=strict\n\ + warn about register name type mismatches\n\ + -mwarn-regtype-mismatch=relaxed\n\ + warn about register name type mismatches,\n\ + but allow FPR and VR to be used interchangeably\n\ + -mno-warn-regtype-mismatch\n\ + do not warn about register name type mismatches\n\ ")); fprintf (stream, _("\ -V print assembler version number\n\ @@ -1279,6 +1342,7 @@ md_gather_operands (char *str, elf_suffix_type suffix; bfd_reloc_code_real_type reloc; int omitted_base_or_index; + int operand_number; char *f; int fc, i; @@ -1287,6 +1351,7 @@ md_gather_operands (char *str, /* Gather the operands. */ omitted_base_or_index = 0; /* Whether B in D(L,B) or X in D(X,B) were omitted. */ + operand_number = 1; /* Current operand number in e.g. R1,I2,M3,D4(B4). */ fc = 0; for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) { @@ -1378,6 +1443,44 @@ md_gather_operands (char *str, as_bad (_("invalid floating point register pair. Valid fp " "register pair operands are 0, 1, 4, 5, 8, 9, " "12 or 13.")); + if (warn_regtype_mismatch && ex.X_op == O_register + && !(opcode->flags & S390_INSTR_FLAG_PSEUDO_MNEMONIC)) + { + const char *expected_regtype = NULL; + + if ((operand->flags & S390_OPERAND_AR) + && ex.X_md != S390_REGTYPE_AR) + expected_regtype = _("access register"); + else if ((operand->flags & S390_OPERAND_CR) + && ex.X_md != S390_REGTYPE_CR) + expected_regtype = _("control register"); + else if ((operand->flags & S390_OPERAND_FPR) + && ex.X_md != S390_REGTYPE_FPR + && (warn_regtype_mismatch == S390_REGTYPE_CHECK_STRICT + || (ex.X_md != S390_REGTYPE_VR))) + expected_regtype = _("floating-point register"); + else if ((operand->flags & S390_OPERAND_GPR) + && ex.X_md != S390_REGTYPE_GR) + expected_regtype = _("general register"); + else if ((operand->flags & S390_OPERAND_VR) + && ex.X_md != S390_REGTYPE_VR + && (warn_regtype_mismatch == S390_REGTYPE_CHECK_STRICT + || (ex.X_md != S390_REGTYPE_FPR))) + expected_regtype = _("vector register"); + + if (expected_regtype) + { + if (operand->flags & S390_OPERAND_BASE) + as_warn (_("operand %d: expected %s name as base register"), + operand_number, expected_regtype); + else if (operand->flags & S390_OPERAND_INDEX) + as_warn (_("operand %d: expected %s name as index register"), + operand_number, expected_regtype); + else + as_warn (_("operand %d: expected %s name"), + operand_number, expected_regtype); + } + } s390_insert_operand (insn, operand, ex.X_add_number, NULL, 0); } } @@ -1516,6 +1619,7 @@ md_gather_operands (char *str, { /* Comma. */ str++; + operand_number++; } } } @@ -1572,6 +1676,7 @@ md_gather_operands (char *str, { /* Comma. */ str++; + operand_number++; } } } @@ -1610,6 +1715,9 @@ md_gather_operands (char *str, { /* Comma. */ str++; + if (!(operand->flags & (S390_OPERAND_INDEX + | S390_OPERAND_LENGTH))) + operand_number++; } } } diff --git a/gas/doc/as.texi b/gas/doc/as.texi index 50c054361416..1e122ccbbde0 100644 --- a/gas/doc/as.texi +++ b/gas/doc/as.texi @@ -584,6 +584,10 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-m31}|@b{-m64}] [@b{-mesa}|@b{-mzarch}] [@b{-march}=@var{CPU}] [@b{-mregnames}|@b{-mno-regnames}] [@b{-mwarn-areg-zero}] + [@b{-mwarn-regtype-mismatch=strict} + @b{-mwarn-regtype-mismatch=relaxed} + @b{-mwarn-regtype-mismatch=no} + @b{-mno-warn-regtype-mismatch}] @end ifset @ifset SCORE @@ -1963,6 +1967,22 @@ Allow or disallow symbolic names for registers. @item -mwarn-areg-zero Warn whenever the operand for a base or index register has been specified but evaluates to zero. +@item -mwarn-regtype-mismatch=strict +@itemx -mwarn-regtype-mismatch=relaxed +@itemx -mwarn-regtype-mismatch=no +@itemx -mno-warn-regtype-mismatch +Controls whether the assembler performs register name type checks and generates +a warning message in case of a mismatch with the operand register type. +The default (which can be restored by using the @option{relaxed} argument) is +to perform relaxed register name type checks, which allow floating point +register (FPR) names %f0 to %f15 to be specified as argument to vector register +(VR) operands and vector register (VR) names %v0 to %v15 to be specified as +argument to floating point register (FPR) operands. This is acceptable as the +FPR are embedded into the lower half of the VR. +Using the @option{strict} argument strict register name type checks are +performed. +The @option{no} argument, which is equivalent to +@samp{-mno-warn-regtype-mismatch}, disables any register name type checks. @end table @end ifset @c man end diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s index 2901a866ec93..812d56e65dbf 100644 --- a/gas/testsuite/gas/s390/esa-g5.s +++ b/gas/testsuite/gas/s390/esa-g5.s @@ -146,8 +146,8 @@ foo: debr %f6,%f9 der %f6,%f9 diag %r6,%r9,4095(%r5) - didbr %f6,%r9,%r5,10 - diebr %f6,%r9,%r5,10 + didbr %f6,%f9,%f5,10 + diebr %f6,%f9,%f5,10 dp 4095(6,%r5),4095(9,%r10) dr %r6,%r9 dxbr %f5,%f8 @@ -465,8 +465,8 @@ foo: sxr %f5,%f8 tar %a6,%r9 tb %r6,%r9 - tbdr %r6,5,%r9 - tbedr %r6,5,%r9 + tbdr %f6,5,%f9 + tbedr %f6,5,%f9 tcdb %f6,4095(%r5,%r10) tceb %f6,4095(%r5,%r10) tcxb %f5,4095(%r5,%r10) diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp index 613487fc453c..a4e8dbc44a50 100644 --- a/gas/testsuite/gas/s390/s390.exp +++ b/gas/testsuite/gas/s390/s390.exp @@ -61,4 +61,6 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { run_dump_test "zarch-base-index-0" "{as -m64}" run_list_test "zarch-base-index-0-err" "" run_list_test "zarch-warn-areg-zero" "-m64 -mwarn-areg-zero" + run_list_test "zarch-warn-regtype-mismatch-strict" "-m64 -mwarn-regtype-mismatch=strict" + run_list_test "zarch-warn-regtype-mismatch-relaxed" "-m64 -mwarn-regtype-mismatch=relaxed" } diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l index fe13f95d3174..e4bd7a8c4171 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l @@ -7,18 +7,19 @@ .*:9: Error: syntax error; missing '\)' after base register .*:12: Error: bad expression .*:12: Error: syntax error; missing '\)' after base register -.*:13: Error: bad expression -.*:13: Error: syntax error; missing '\)' after base register -.*:16: Error: missing operand +.*:13: Warning: operand 2: expected general register name as base register +.*:14: Error: bad expression +.*:14: Error: syntax error; missing '\)' after base register .*:17: Error: missing operand -.*:18: Error: invalid length field specified -.*:19: Error: bad expression -.*:19: Error: operand out of range \(0 is not between 1 and 256\) -.*:19: Error: operand out of range \(32 is not between 0 and 15\) -.*:19: Error: syntax error; missing '\)' after base register -.*:19: Error: syntax error; expected ',' -.*:19: Error: bad expression -.*:19: Error: found 'r', expected: '\)' -.*:19: Error: syntax error; missing '\)' after base register -.*:19: Error: junk at end of line: `r2\)' -.*:20: Error: syntax error; missing '\(' after displacement +.*:18: Error: missing operand +.*:19: Error: invalid length field specified +.*:20: Error: bad expression +.*:20: Error: operand out of range \(0 is not between 1 and 256\) +.*:20: Error: operand out of range \(32 is not between 0 and 15\) +.*:20: Error: syntax error; missing '\)' after base register +.*:20: Error: syntax error; expected ',' +.*:20: Error: bad expression +.*:20: Error: found 'r', expected: '\)' +.*:20: Error: syntax error; missing '\)' after base register +.*:20: Error: junk at end of line: `r2\)' +.*:21: Error: syntax error; missing '\(' after displacement diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s index 65ad739d02c6..dd0e9fe183f3 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s @@ -10,6 +10,7 @@ foo: # V1,D2(VX2,B2),M3 vgef %v1,16(%v2,),0 + vgef %v1,16(%v2),0 vgef %v1,16(),0 # D1(L1,B1),D2(B2) diff --git a/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l new file mode 100644 index 000000000000..e91f0206934f --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l @@ -0,0 +1,15 @@ +.*: Assembler messages: +.*:3: Warning: operand 1: expected general register name +.*:3: Warning: operand 2: expected general register name as index register +.*:3: Warning: operand 2: expected general register name as base register +.*:4: Warning: operand 1: expected floating-point register name +.*:4: Warning: operand 2: expected general register name as index register +.*:4: Warning: operand 2: expected general register name as base register +.*:5: Warning: operand 1: expected vector register name +.*:5: Warning: operand 2: expected general register name as index register +.*:5: Warning: operand 2: expected general register name as base register +.*:6: Warning: operand 1: expected vector register name +.*:6: Warning: operand 2: expected vector register name as index register +.*:6: Warning: operand 2: expected general register name as base register +.*:7: Warning: operand 1: expected access register name +.*:7: Warning: operand 2: expected general register name diff --git a/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s new file mode 100644 index 000000000000..ed6688db7027 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s @@ -0,0 +1,7 @@ +.text +foo: + la %f1,16(%f2,%f3) # la %r1,16(%r2,%r3) + ld %r1,16(%f2,%f3) # ld %f1,16(%r2,%r3) + vl %r1,16(%f2,%f3),0 # vl %v1,16(%r2,%r3),0 + vgef %r1,16(%r1,%f3),0 # vgef %v1,16(%v2,%r3),0 + sar %r1,%a2 # sar %a1,%r2 diff --git a/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l new file mode 100644 index 000000000000..e91f0206934f --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l @@ -0,0 +1,15 @@ +.*: Assembler messages: +.*:3: Warning: operand 1: expected general register name +.*:3: Warning: operand 2: expected general register name as index register +.*:3: Warning: operand 2: expected general register name as base register +.*:4: Warning: operand 1: expected floating-point register name +.*:4: Warning: operand 2: expected general register name as index register +.*:4: Warning: operand 2: expected general register name as base register +.*:5: Warning: operand 1: expected vector register name +.*:5: Warning: operand 2: expected general register name as index register +.*:5: Warning: operand 2: expected general register name as base register +.*:6: Warning: operand 1: expected vector register name +.*:6: Warning: operand 2: expected vector register name as index register +.*:6: Warning: operand 2: expected general register name as base register +.*:7: Warning: operand 1: expected access register name +.*:7: Warning: operand 2: expected general register name diff --git a/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s new file mode 100644 index 000000000000..ed6688db7027 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s @@ -0,0 +1,7 @@ +.text +foo: + la %f1,16(%f2,%f3) # la %r1,16(%r2,%r3) + ld %r1,16(%f2,%f3) # ld %f1,16(%r2,%r3) + vl %r1,16(%f2,%f3),0 # vl %v1,16(%r2,%r3),0 + vgef %r1,16(%r1,%f3),0 # vgef %v1,16(%v2,%r3),0 + sar %r1,%a2 # sar %a1,%r2 diff --git a/gas/testsuite/gas/s390/zarch-z13.s b/gas/testsuite/gas/s390/zarch-z13.s index 646dd3097fb3..8c2fb706e0c0 100644 --- a/gas/testsuite/gas/s390/zarch-z13.s +++ b/gas/testsuite/gas/s390/zarch-z13.s @@ -1,8 +1,8 @@ .text foo: lcbb %r6,4000(%r9,%r11),13 - vgef %v15,4000(%r6,%r9),13 - vgeg %v15,4000(%r6,%r9),13 + vgef %v15,4000(%v6,%r9),13 + vgeg %v15,4000(%v6,%r9),13 vgbm %v15,65533 vzero %v15 vone %v15 @@ -83,8 +83,8 @@ foo: vrepih %v15,-32765 vrepif %v15,-32765 vrepig %v15,-32765 - vscef %v15,4000(%r6,%r9),13 - vsceg %v15,4000(%r6,%r9),13 + vscef %v15,4000(%v6,%r9),13 + vsceg %v15,4000(%v6,%r9),13 vsel %v15,%v17,%v20,%v24 vseg %v15,%v17,13 vsegb %v15,%v17 diff --git a/include/opcode/s390.h b/include/opcode/s390.h index 5656368726a4..e5dfcb275707 100644 --- a/include/opcode/s390.h +++ b/include/opcode/s390.h @@ -77,6 +77,9 @@ enum s390_opcode_cpu_val (S390_INSTR_FLAG_CLASS_BRANCH | S390_INSTR_FLAG_CLASS_RELATIVE \ | S390_INSTR_FLAG_CLASS_SUBROUTINE) +/* Instruction is an .insn pseudo-mnemonic. */ +#define S390_INSTR_FLAG_PSEUDO_MNEMONIC 0x100 + /* The opcode table is an array of struct s390_opcode. */ struct s390_opcode diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 377a4a915893..10482fbc1e01 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -774,37 +774,37 @@ unused_s390_operands_static_asserts (void) const struct s390_opcode s390_opformats[] = { - { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0, 0, NULL }, - { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0, NULL }, - { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0, 0, NULL }, - { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0, 0, NULL }, - { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0, 0, NULL }, - { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6, 0, NULL }, - { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, NULL }, - { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, NULL }, - { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0, 0, NULL }, - { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6, 0, NULL }, - { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, NULL }, - { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0, 0, NULL }, - { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 0, NULL }, - { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 0, NULL }, - { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, NULL }, - { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0, 0, NULL }, - { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0, 0, NULL }, - { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0, NULL }, - { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, NULL }, - { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, NULL }, - { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3, 0, NULL }, - { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6, 0, NULL }, - { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 0, NULL }, - { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0, NULL }, - { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0, 0, NULL }, - { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9, 0, NULL }, - { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9, 0, NULL }, - { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9, 0, NULL }, - { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9, 0, NULL }, - { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9, 0, NULL }, - { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10, 0, NULL }, + { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0, 256, NULL }, + { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 256, NULL }, + { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0, 256, NULL }, + { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0, 256, NULL }, + { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0, 256, NULL }, + { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6, 256, NULL }, + { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 256, NULL }, + { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 256, NULL }, + { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0, 256, NULL }, + { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6, 256, NULL }, + { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 256, NULL }, + { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0, 256, NULL }, + { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 256, NULL }, + { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 256, NULL }, + { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 256, NULL }, + { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0, 256, NULL }, + { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0, 256, NULL }, + { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 256, NULL }, + { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0, 256, NULL }, + { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 256, NULL }, + { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3, 256, NULL }, + { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6, 256, NULL }, + { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 256, NULL }, + { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 256, NULL }, + { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0, 256, NULL }, + { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9, 256, NULL }, + { "vri", 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Thu, 15 Feb 2024 15:58:29 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:29 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 11/14] s390: Print base register 0 as "0" in disassembly Date: Thu, 15 Feb 2024 16:58:18 +0100 Message-Id: <20240215155821.4065623-12-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: W2lfle_rqOog2CiYvk9NleFbCog4l0Vv X-Proofpoint-ORIG-GUID: W2lfle_rqOog2CiYvk9NleFbCog4l0Vv X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 impostorscore=0 mlxscore=0 adultscore=0 priorityscore=1501 mlxlogscore=697 malwarescore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150128 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981271626869010 X-GMAIL-MSGID: 1790981271626869010 Base and index register 0 have no effect in address computation: "A value of zero in the B [base] or X [index] field specifies that no base or index is to be applied, and, thus, general register 0 cannot be designated as containing a base address or index." IBM z/Architecture Principles of Operation [1], chapter "Organization", section "General Registers". Index register 0 is omitted in the s390 disassembly. Base register 0 is omitted in D(B), D(L,B) and D(X,B) - the latter only if the index register is zero. To make it more apparent print base register 0 as "0" instead of "%r0", whenever it would still be printed in the disassembly. [1]: IBM z/Architecture Principles of Operation, SA22-7832-13, https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf opcodes/ * s390-dis.c: Print base register 0 as "0" in disassembly. binutils/ * NEWS: Mention base register 0 now being printed as "0" in s390 disassembly. gas/ * testsuite/gas/s390/zarch-base-index-0.d: Update test case output verification patterns to accept "0" as base base register due to disassembler output format change. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- binutils/NEWS | 2 + gas/testsuite/gas/s390/zarch-base-index-0.d | 66 +++++++++---------- .../gas/s390/zarch-omitted-base-index.d | 4 +- opcodes/s390-dis.c | 17 +++-- 4 files changed, 50 insertions(+), 39 deletions(-) diff --git a/binutils/NEWS b/binutils/NEWS index 7b7ac1cbba11..9c7c8f1f6033 100644 --- a/binutils/NEWS +++ b/binutils/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Base register 0 is now printed as "0" instead of "%r0" in s390 disassembly. + * When objdump or readelf are used to display the contents of a .eh_frame section they will now also display the contents of the .eh_frame_hdr section, if present. diff --git a/gas/testsuite/gas/s390/zarch-base-index-0.d b/gas/testsuite/gas/s390/zarch-base-index-0.d index e6266040c8e7..4dd913bff920 100644 --- a/gas/testsuite/gas/s390/zarch-base-index-0.d +++ b/gas/testsuite/gas/s390/zarch-base-index-0.d @@ -17,8 +17,8 @@ Disassembly of section .text: .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) -.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\) -.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) .*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 @@ -31,46 +31,46 @@ Disassembly of section .text: .*: 5a 00 00 00 [ ]*a %r0,0 .*: 5a 00 00 00 [ ]*a %r0,0 .*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,%r0\),0 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,0\),0 .*: f3 01 10 10 20 20 [ ]*unpk 16\(1,%r1\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,%r0\),0\(2,%r0\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,0\),0\(2,0\) .*: e7 12 30 10 00 13 [ ]*vgef %v1,16\(%v2,%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 -.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0 -.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index.d b/gas/testsuite/gas/s390/zarch-omitted-base-index.d index b2ff292628b1..cb168a2fe187 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index.d +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index.d @@ -18,5 +18,5 @@ Disassembly of section .text: .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\) .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c index a4cba77c6aeb..ee2f2cb62ed2 100644 --- a/opcodes/s390-dis.c +++ b/opcodes/s390-dis.c @@ -234,8 +234,13 @@ s390_print_insn_with_opcode (bfd_vma memaddr, { info->fprintf_styled_func (info->stream, dis_style_text, "%c", separator); - info->fprintf_styled_func (info->stream, dis_style_register, - "%%r%u", val.u); + if ((flags & (S390_OPERAND_BASE | S390_OPERAND_INDEX)) + && val.u == 0) + info->fprintf_styled_func (info->stream, dis_style_register, + "%u", val.u); + else + info->fprintf_styled_func (info->stream, dis_style_register, + "%%r%u", val.u); } else if (flags & S390_OPERAND_FPR) { @@ -248,8 +253,12 @@ s390_print_insn_with_opcode (bfd_vma memaddr, { info->fprintf_styled_func (info->stream, dis_style_text, "%c", separator); - info->fprintf_styled_func (info->stream, dis_style_register, - "%%v%i", val.u); + if ((flags & S390_OPERAND_INDEX) && val.u == 0) + info->fprintf_styled_func (info->stream, dis_style_register, + "%u", val.u); + else + info->fprintf_styled_func (info->stream, dis_style_register, + "%%v%i", val.u); } else if (flags & S390_OPERAND_AR) { From patchwork Thu Feb 15 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Thu, 15 Feb 2024 15:58:30 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:30 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 12/14] s390: Allow to explicitly omit base register operand in assembly Date: Thu, 15 Feb 2024 16:58:19 +0100 Message-Id: <20240215155821.4065623-13-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: clEKOX5Rd8pihqdkThPIGi7IjMMPSKHr X-Proofpoint-GUID: clEKOX5Rd8pihqdkThPIGi7IjMMPSKHr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 mlxlogscore=851 bulkscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981498355011132 X-GMAIL-MSGID: 1790981498355011132 The base register operand B may be omitted in D(B) by coding D and in D(L,B) by coding D(L). The index register operand X may be omitted in D(X,B) by coding D(B) or explicitly omitted by coding D(,B). In both cases the omitted base register operand value defaults to zero. Allow to explicitly omit the base register operand B in D(X,B) and D(L,B) by coding D(X,) and D(L,). Default the omitted base register operand value to zero. gas/ * config/tc-s390.c: Allow to explicitly omit the base register operand in assembly. * NEWS: Mention that the base register now may be omitted on s390. * gas/testsuite/gas/s390/zarch-base-index-0.s: Update test cases for change to allow to explicitly omit the base register operand in assembly. * gas/testsuite/gas/s390/zarch-base-index-0.d: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.s: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/NEWS | 4 + gas/config/tc-s390.c | 10 +- .../gas/s390/zarch-base-index-0-err.l | 156 ++++++------------ .../gas/s390/zarch-base-index-0-err.s | 19 --- gas/testsuite/gas/s390/zarch-base-index-0.d | 19 +++ gas/testsuite/gas/s390/zarch-base-index-0.s | 38 ++--- .../gas/s390/zarch-omitted-base-index-err.l | 32 ++-- .../gas/s390/zarch-omitted-base-index-err.s | 2 - .../gas/s390/zarch-omitted-base-index.d | 3 + .../gas/s390/zarch-omitted-base-index.s | 2 + 10 files changed, 120 insertions(+), 165 deletions(-) diff --git a/gas/NEWS b/gas/NEWS index e5572da5f7b8..f862547ac748 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,9 @@ -*- text -*- +* The base register operand in D(X,B) and D(L,B) may be explicitly omitted + in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0) + D(X,%r0), D(L,0), and D(L,%r0). + * Warn when a register name type does not match the operand type on s390. Add support for s390-specific option "warn-regtype-mismatch=[strict|relaxed| no]" to override the register name type check behavior. The default diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index daa44bb3f816..85a86d590ad1 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -1683,13 +1683,17 @@ md_gather_operands (char *str, else { /* We can find an 'early' closing parentheses in e.g. D(L) instead - of D(L,B). In this case the base register has to be skipped. */ - if (*str == ')') + of D(L,B). In this case the base register has to be skipped. + Same if the base register has been explicilty omitted in e.g. + D(X,) or D(L,). */ + if (*str == ')' || (str[0] == ',' && str[1] == ')')) { operand = s390_operands + *(++opindex_ptr); if (!(operand->flags & S390_OPERAND_BASE)) - as_bad (_("syntax error; ')' not allowed here")); + as_bad (_("syntax error; '%c' not allowed here"), *str); + if (*str == ',') + str++; str++; } diff --git a/gas/testsuite/gas/s390/zarch-base-index-0-err.l b/gas/testsuite/gas/s390/zarch-base-index-0-err.l index 1762b6ec0813..e7d03ecdfe11 100644 --- a/gas/testsuite/gas/s390/zarch-base-index-0-err.l +++ b/gas/testsuite/gas/s390/zarch-base-index-0-err.l @@ -5,122 +5,70 @@ .*:8: Error: syntax error; missing '\)' after base register .*:9: Error: bad expression .*:9: Error: syntax error; missing '\)' after base register -.*:10: Error: bad expression -.*:10: Error: syntax error; missing '\)' after base register -.*:11: Error: bad expression -.*:11: Error: syntax error; missing '\)' after base register .*:12: Error: bad expression .*:12: Error: syntax error; missing '\)' after base register +.*:13: Error: bad expression +.*:13: Error: syntax error; missing '\)' after base register +.*:14: Error: bad expression +.*:14: Error: syntax error; missing '\)' after base register .*:15: Error: bad expression .*:15: Error: syntax error; missing '\)' after base register .*:16: Error: bad expression .*:16: Error: syntax error; missing '\)' after base register -.*:17: Error: bad expression -.*:17: Error: syntax error; missing '\)' after base register -.*:18: Error: bad expression -.*:18: Error: syntax error; missing '\)' after base register -.*:19: Error: bad expression -.*:19: Error: syntax error; missing '\)' after base register -.*:20: Error: bad expression -.*:20: Error: syntax error; missing '\)' after base register +.*:17: Error: operand out of range \(0 is not between 1 and 256\) +.*:18: Error: missing operand +.*:19: Error: missing operand +.*:20: Error: missing operand .*:21: Error: bad expression +.*:21: Error: operand out of range \(0 is not between 1 and 256\) +.*:21: Error: operand out of range \(32 is not between 0 and 15\) .*:21: Error: syntax error; missing '\)' after base register +.*:21: Error: syntax error; expected ',' .*:21: Error: bad expression +.*:21: Error: found 'r', expected: '\)' .*:21: Error: syntax error; missing '\)' after base register -.*:22: Error: bad expression -.*:22: Error: syntax error; missing '\)' after base register -.*:23: Error: bad expression -.*:23: Error: syntax error; missing '\)' after base register -.*:24: Error: operand out of range \(0 is not between 1 and 256\) -.*:25: Error: missing operand -.*:26: Error: missing operand +.*:21: Error: junk at end of line: `r2\)' +.*:22: Error: syntax error; missing '\(' after displacement +.*:23: Error: invalid length field specified +.*:26: Error: operand out of range \(0 is not between 1 and 16\) .*:27: Error: missing operand -.*:27: Error: bad expression -.*:27: Error: syntax error; missing '\)' after base register -.*:28: Error: bad expression -.*:28: Error: operand out of range \(0 is not between 1 and 256\) -.*:28: Error: operand out of range \(32 is not between 0 and 15\) -.*:28: Error: syntax error; missing '\)' after base register -.*:28: Error: syntax error; expected ',' -.*:28: Error: bad expression -.*:28: Error: found 'r', expected: '\)' -.*:28: Error: syntax error; missing '\)' after base register -.*:28: Error: junk at end of line: `r2\)' -.*:29: Error: syntax error; missing '\(' after displacement -.*:30: Error: invalid length field specified -.*:33: Error: bad expression -.*:33: Error: syntax error; missing '\)' after base register -.*:34: Error: bad expression -.*:34: Error: syntax error; missing '\)' after base register -.*:35: Error: bad expression -.*:35: Error: syntax error; missing '\)' after base register +.*:28: Error: missing operand +.*:29: Error: missing operand +.*:30: Error: bad expression +.*:30: Error: operand out of range \(0 is not between 1 and 16\) +.*:30: Error: operand out of range \(32 is not between 0 and 15\) +.*:30: Error: syntax error; missing '\)' after base register +.*:30: Error: syntax error; expected ',' +.*:30: Error: found ',', expected: '\)' +.*:31: Error: syntax error; missing '\(' after displacement +.*:32: Error: operand out of range \(0 is not between 1 and 16\) +.*:33: Error: missing operand +.*:34: Error: missing operand +.*:35: Error: missing operand .*:36: Error: bad expression -.*:36: Error: syntax error; missing '\)' after base register -.*:37: Error: bad expression -.*:37: Error: syntax error; missing '\)' after base register -.*:38: Error: bad expression -.*:38: Error: syntax error; missing '\)' after base register -.*:39: Error: bad expression -.*:39: Error: syntax error; missing '\)' after base register -.*:39: Error: bad expression -.*:39: Error: syntax error; missing '\)' after base register -.*:40: Error: bad expression -.*:40: Error: syntax error; missing '\)' after base register -.*:41: Error: bad expression -.*:41: Error: syntax error; missing '\)' after base register +.*:36: Error: operand out of range \(0 is not between 1 and 16\) +.*:36: Error: syntax error; expected ',' +.*:37: Error: syntax error; missing '\(' after displacement +.*:38: Error: operand out of range \(0 is not between 1 and 16\) +.*:38: Error: operand out of range \(0 is not between 1 and 16\) +.*:39: Error: missing operand +.*:39: Error: missing operand +.*:40: Error: missing operand +.*:40: Error: missing operand +.*:41: Error: missing operand +.*:41: Error: missing operand +.*:42: Error: bad expression .*:42: Error: operand out of range \(0 is not between 1 and 16\) -.*:43: Error: missing operand -.*:44: Error: missing operand -.*:45: Error: missing operand -.*:45: Error: bad expression -.*:45: Error: syntax error; missing '\)' after base register +.*:42: Error: operand out of range \(32 is not between 0 and 15\) +.*:42: Error: syntax error; missing '\)' after base register +.*:42: Error: syntax error; expected ',' +.*:42: Error: bad expression +.*:42: Error: missing '\)' +.*:42: Error: operand out of range \(0 is not between 1 and 16\) +.*:42: Error: syntax error; expected ',' +.*:43: Error: syntax error; missing '\(' after displacement +.*:43: Error: syntax error; missing '\(' after displacement .*:46: Error: bad expression -.*:46: Error: operand out of range \(0 is not between 1 and 16\) -.*:46: Error: operand out of range \(32 is not between 0 and 15\) .*:46: Error: syntax error; missing '\)' after base register -.*:46: Error: syntax error; expected ',' -.*:46: Error: found ',', expected: '\)' -.*:47: Error: syntax error; missing '\(' after displacement -.*:48: Error: operand out of range \(0 is not between 1 and 16\) -.*:49: Error: missing operand -.*:50: Error: missing operand -.*:51: Error: missing operand -.*:51: Error: bad expression -.*:51: Error: syntax error; missing '\)' after base register -.*:52: Error: bad expression -.*:52: Error: operand out of range \(0 is not between 1 and 16\) -.*:52: Error: syntax error; expected ',' -.*:53: Error: syntax error; missing '\(' after displacement -.*:54: Error: operand out of range \(0 is not between 1 and 16\) -.*:54: Error: operand out of range \(0 is not between 1 and 16\) -.*:55: Error: missing operand -.*:55: Error: missing operand -.*:56: Error: missing operand -.*:56: Error: missing operand -.*:57: Error: missing operand -.*:57: Error: bad expression -.*:57: Error: syntax error; missing '\)' after base register -.*:57: Error: missing operand -.*:57: Error: bad expression -.*:57: Error: syntax error; missing '\)' after base register -.*:58: Error: bad expression -.*:58: Error: operand out of range \(0 is not between 1 and 16\) -.*:58: Error: operand out of range \(32 is not between 0 and 15\) -.*:58: Error: syntax error; missing '\)' after base register -.*:58: Error: syntax error; expected ',' -.*:58: Error: bad expression -.*:58: Error: missing '\)' -.*:58: Error: operand out of range \(0 is not between 1 and 16\) -.*:58: Error: syntax error; expected ',' -.*:59: Error: syntax error; missing '\(' after displacement -.*:59: Error: syntax error; missing '\(' after displacement -.*:62: Error: bad expression -.*:62: Error: syntax error; missing '\)' after base register -.*:63: Error: bad expression -.*:63: Error: syntax error; missing '\)' after base register -.*:64: Error: bad expression -.*:64: Error: syntax error; missing '\)' after base register -.*:65: Error: bad expression -.*:65: Error: syntax error; missing '\)' after base register -.*:66: Error: bad expression -.*:66: Error: syntax error; missing '\)' after base register +.*:47: Error: bad expression +.*:47: Error: syntax error; missing '\)' after base register diff --git a/gas/testsuite/gas/s390/zarch-base-index-0-err.s b/gas/testsuite/gas/s390/zarch-base-index-0-err.s index 175cc90b2699..472d24ef6273 100644 --- a/gas/testsuite/gas/s390/zarch-base-index-0-err.s +++ b/gas/testsuite/gas/s390/zarch-base-index-0-err.s @@ -5,21 +5,14 @@ foo: mvi 16(),32 # syntax error: empty parentheses # R1,D2(X2,B2) - a %r1,16(%r2,) # syntax error: explicitly omitted base - a %r1,16(%r0,) # syntax error: explicitly omitted base - a %r1,16(0,) # syntax error: explicitly omitted base a %r1,16(,) # syntax error: explicitly omitted index & base a %r1,16() # syntax error: empty parentheses # D1(L1,B1),D2(B2) - mvc 16(1,),32(%r2) # syntax error: explicitly omitted base mvc 16(1,%r1),32() # syntax error: empty parentheses mvc 16(1,%r0),32() # syntax error: empty parentheses mvc 16(1,0),32() # syntax error: empty parentheses - mvc 16(1,),32(%r0) # syntax error: explicitly omitted base - mvc 16(1,),32(0) # syntax error: explicitly omitted base mvc 16(1,),32() # syntax error: explicitly omitted base & empty parentheses - mvc 16(1,),32 # syntax error: explicitly omitted base mvc 16(1),32() # syntax error: empty parentheses mvc 16(0,%r1),32(%r2) # syntax error: length 0 mvc 16(,%r1),32(%r2) # syntax error: explicitly omitted length @@ -30,15 +23,6 @@ foo: mvc 16(%r1),32(%r2) # syntax error: omitted length # D1(L1,B1),D2(L2,B2) - unpk 16(1,),32(2,%r2) # syntax error: explicitly omitted base - unpk 16(1,%r1),32(2,) # syntax error: explicitly omitted base - unpk 16(1,%r0),32(2,) # syntax error: explicitly omitted base - unpk 16(1,0),32(2,) # syntax error: explicitly omitted base - unpk 16(1,),32(2,%r0) # syntax error: explicitly omitted base - unpk 16(1,),32(2,0) # syntax error: explicitly omitted base - unpk 16(1,),32(2,) # syntax error: explicitly omitted base - unpk 16(1,),32(2) # syntax error: explicitly omitted base - unpk 16(1),32(2,) # syntax error: explicitly omitted base unpk 16(0,%r1),32(2,%r2) # syntax error: length 0 unpk 16(,%r1),32(2,%r2) # syntax error: explicitly omitted length unpk 16(,1),32(2,%r2) # syntax error: explicitly omitted length @@ -59,8 +43,5 @@ foo: unpk 16,32 # syntax error: missing lengths # V1,D2(VX2,B2),M3 - vgef %v1,16(%v2,),0 # syntax error: explicitly omitted base - vgef %v1,16(%v0,),0 # syntax error: explicitly omitted base - vgef %v1,16(0,),0 # syntax error: explicitly omitted base vgef %v1,16(,),0 # syntax error: explicitly omitted index & base vgef %v1,16(),0 # syntax error: empty parentheses diff --git a/gas/testsuite/gas/s390/zarch-base-index-0.d b/gas/testsuite/gas/s390/zarch-base-index-0.d index 4dd913bff920..717eaac2423b 100644 --- a/gas/testsuite/gas/s390/zarch-base-index-0.d +++ b/gas/testsuite/gas/s390/zarch-base-index-0.d @@ -19,6 +19,9 @@ Disassembly of section .text: .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) .*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) +.*: 5a 10 00 10 [ ]*a %r1,16 +.*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 @@ -34,6 +37,7 @@ Disassembly of section .text: .*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) .*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) .*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 @@ -46,14 +50,26 @@ Disassembly of section .text: .*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 .*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 .*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 .*: d2 00 00 00 00 00 [ ]*mvc 0\(1,0\),0 .*: f3 01 10 10 20 20 [ ]*unpk 16\(1,%r1\),32\(2,%r2\) .*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) .*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) .*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) .*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) .*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) .*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) .*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) .*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) .*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) @@ -71,6 +87,9 @@ Disassembly of section .text: .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 .*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 +.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 +.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 diff --git a/gas/testsuite/gas/s390/zarch-base-index-0.s b/gas/testsuite/gas/s390/zarch-base-index-0.s index 15c792d776fa..e34c626707e2 100644 --- a/gas/testsuite/gas/s390/zarch-base-index-0.s +++ b/gas/testsuite/gas/s390/zarch-base-index-0.s @@ -18,13 +18,13 @@ foo: a %r1,16(%r3) a %r1,16(%r2,%r0) a %r1,16(%r2,0) -# a %r1,16(%r2,) # syntax error: explicitly omitted base + a %r1,16(%r2,) # syntax error: explicitly omitted base a %r1,16(%r0,%r0) a %r1,16(%r0,0) -# a %r1,16(%r0,) # syntax error: explicitly omitted base + a %r1,16(%r0,) # syntax error: explicitly omitted base a %r1,16(0,%r0) a %r1,16(0,0) -# a %r1,16(0,) # syntax error: explicitly omitted base + a %r1,16(0,) # syntax error: explicitly omitted base a %r1,16(0,%r0) a %r1,16(,%r0) a %r1,16(,0) @@ -39,7 +39,7 @@ foo: mvc 16(1,%r1),32(%r2) mvc 16(1,%r0),32(%r2) mvc 16(1,0),32(%r2) -# mvc 16(1,),32(%r2) # syntax error: explicitly omitted base + mvc 16(1,),32(%r2) mvc 16(1),32(%r2) mvc 16(1,%r1),32(%r0) mvc 16(1,%r1),32(0) @@ -53,10 +53,10 @@ foo: mvc 16(1,0),32(0) # mvc 16(1,0),32() # syntax error: empty parentheses mvc 16(1,0),32 -# mvc 16(1,),32(%r0) # syntax error: explicitly omitted base -# mvc 16(1,),32(0) # syntax error: explicitly omitted base + mvc 16(1,),32(%r0) + mvc 16(1,),32(0) # mvc 16(1,),32() # syntax error: explicitly omitted base & empty parentheses -# mvc 16(1,),32 # syntax error: explicitly omitted base + mvc 16(1,),32 mvc 16(1),32(%r0) mvc 16(1),32(0) # mvc 16(1),32() # syntax error: empty parentheses @@ -67,27 +67,27 @@ foo: unpk 16(1,%r1),32(2,%r2) unpk 16(1,%r0),32(2,%r2) unpk 16(1,0),32(2,%r2) -# unpk 16(1,),32(2,%r2) # syntax error: explicitly omitted base + unpk 16(1,),32(2,%r2) unpk 16(1),32(2,%r2) unpk 16(1,%r1),32(2,%r0) unpk 16(1,%r1),32(2,0) -# unpk 16(1,%r1),32(2,) # syntax error: explicitly omitted base + unpk 16(1,%r1),32(2,) unpk 16(1,%r1),32(2) unpk 16(1,%r0),32(2,%r0) unpk 16(1,%r0),32(2,0) -# unpk 16(1,%r0),32(2,) # syntax error: explicitly omitted base + unpk 16(1,%r0),32(2,) unpk 16(1,%r0),32(2) unpk 16(1,0),32(2,%r0) unpk 16(1,0),32(2,0) -# unpk 16(1,0),32(2,) # syntax error: explicitly omitted base + unpk 16(1,0),32(2,) unpk 16(1,0),32(2) -# unpk 16(1,),32(2,%r0) # syntax error: explicitly omitted base -# unpk 16(1,),32(2,0) # syntax error: explicitly omitted base -# unpk 16(1,),32(2,) # syntax error: explicitly omitted base -# unpk 16(1,),32(2) # syntax error: explicitly omitted base + unpk 16(1,),32(2,%r0) + unpk 16(1,),32(2,0) + unpk 16(1,),32(2,) + unpk 16(1,),32(2) unpk 16(1),32(2,%r0) unpk 16(1),32(2,0) -# unpk 16(1),32(2,) # syntax error: explicitly omitted base + unpk 16(1),32(2,) unpk 16(1),32(2) unpk 0(1),0(2) @@ -99,13 +99,13 @@ foo: vgef %v1,16(%r3),0 vgef %v1,16(%v2,%r0),0 vgef %v1,16(%v2,0),0 -# vgef %v1,16(%v2,),0 # syntax error: explicitly omitted base + vgef %v1,16(%v2,),0 vgef %v1,16(%v0,%r0),0 vgef %v1,16(%v0,0),0 -# vgef %v1,16(%v0,),0 # syntax error: explicitly omitted base + vgef %v1,16(%v0,),0 vgef %v1,16(0,%r0),0 vgef %v1,16(0,0),0 -# vgef %v1,16(0,),0 # syntax error: explicitly omitted base + vgef %v1,16(0,),0 vgef %v1,16(,%r0),0 vgef %v1,16(,0),0 # vgef %v1,16(,),0 # syntax error: explicitly omitted index & base diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l index e4bd7a8c4171..f222fe00093e 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l @@ -3,23 +3,19 @@ .*:5: Error: syntax error; missing '\)' after base register .*:8: Error: bad expression .*:8: Error: syntax error; missing '\)' after base register -.*:9: Error: bad expression -.*:9: Error: syntax error; missing '\)' after base register +.*:11: Warning: operand 2: expected general register name as base register .*:12: Error: bad expression .*:12: Error: syntax error; missing '\)' after base register -.*:13: Warning: operand 2: expected general register name as base register -.*:14: Error: bad expression -.*:14: Error: syntax error; missing '\)' after base register -.*:17: Error: missing operand -.*:18: Error: missing operand -.*:19: Error: invalid length field specified -.*:20: Error: bad expression -.*:20: Error: operand out of range \(0 is not between 1 and 256\) -.*:20: Error: operand out of range \(32 is not between 0 and 15\) -.*:20: Error: syntax error; missing '\)' after base register -.*:20: Error: syntax error; expected ',' -.*:20: Error: bad expression -.*:20: Error: found 'r', expected: '\)' -.*:20: Error: syntax error; missing '\)' after base register -.*:20: Error: junk at end of line: `r2\)' -.*:21: Error: syntax error; missing '\(' after displacement +.*:15: Error: missing operand +.*:16: Error: missing operand +.*:17: Error: invalid length field specified +.*:18: Error: bad expression +.*:18: Error: operand out of range \(0 is not between 1 and 256\) +.*:18: Error: operand out of range \(32 is not between 0 and 15\) +.*:18: Error: syntax error; missing '\)' after base register +.*:18: Error: syntax error; expected ',' +.*:18: Error: bad expression +.*:18: Error: found 'r', expected: '\)' +.*:18: Error: syntax error; missing '\)' after base register +.*:18: Error: junk at end of line: `r2\)' +.*:19: Error: syntax error; missing '\(' after displacement diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s index dd0e9fe183f3..0114c6403756 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s @@ -5,11 +5,9 @@ foo: clm %r1,0b1000,16() # R1,D2(X2,B2) - a %r1,16(%r2,) a %r1,16() # V1,D2(VX2,B2),M3 - vgef %v1,16(%v2,),0 vgef %v1,16(%v2),0 vgef %v1,16(),0 diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index.d b/gas/testsuite/gas/s390/zarch-omitted-base-index.d index cb168a2fe187..2795a9d095cb 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index.d +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index.d @@ -9,10 +9,12 @@ Disassembly of section .text: .*: bd 18 20 10 [ ]*clm %r1,8,16\(%r2\) .*: bd 18 00 10 [ ]*clm %r1,8,16 .*: 5a 12 30 10 [ ]*a %r1,16\(%r2,%r3\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 10 00 10 [ ]*a %r1,16 .*: e7 12 30 10 00 13 [ ]*vgef %v1,16\(%v2,%r3\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 @@ -20,3 +22,4 @@ Disassembly of section .text: .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) .*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: 07 07 [ ]*nopr %r7 diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index.s b/gas/testsuite/gas/s390/zarch-omitted-base-index.s index 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Thu, 15 Feb 2024 15:58:30 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:30 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 13/14] s390: Provide operand number in assembler warning and error messages Date: Thu, 15 Feb 2024 16:58:20 +0100 Message-Id: <20240215155821.4065623-14-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: K25K22EZpiihZDWjzhHlD0jiPc1SlZJD X-Proofpoint-ORIG-GUID: K25K22EZpiihZDWjzhHlD0jiPc1SlZJD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=976 impostorscore=0 adultscore=0 spamscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 malwarescore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981420329081893 X-GMAIL-MSGID: 1790981420329081893 Prepend the operand number "operand %d:" to the s390-specific assembler operand parsing warning and error messages. While at it reword the custom operand out of range error message text to be closer to the one used by as_bad_value_out_of_range(). Additionally reword the invalid FPR pair warning message to make it nicer. gas/ * config/tc-s390.c: Print operand number in error messages. * testsuite/gas/s390/zarch-base-index-0-err.l: Update test case verification patterns to accept syntax error messages now containing the operand number. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. * testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise. * testsuite/gas/s390/zarch-z9-109-err.l: Likewise. * testsuite/gas/s390/zarch-z900-err.l: Likewise. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/config/tc-s390.c | 107 ++++++++++----- .../gas/s390/zarch-base-index-0-err.l | 106 +++++++-------- .../gas/s390/zarch-omitted-base-index-err.l | 24 ++-- gas/testsuite/gas/s390/zarch-warn-areg-zero.l | 128 +++++++++--------- gas/testsuite/gas/s390/zarch-z9-109-err.l | 2 +- gas/testsuite/gas/s390/zarch-z900-err.l | 4 +- 6 files changed, 206 insertions(+), 165 deletions(-) diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 85a86d590ad1..786c372a9c1a 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -663,6 +663,41 @@ s390_md_finish (void) bfd_set_arch_mach (stdoutput, bfd_arch_s390, bfd_mach_s390_31); } +static void +s390_bad_operand_out_of_range (int operand_number, + offsetT value, + offsetT min, + offsetT max, + const char *file, + unsigned line) +{ + const char * err; + + if (operand_number > 0) + { + /* xgettext:c-format. */ + err =_("operand %d: operand out of range (%" PRId64 + " is not between %" PRId64 " and %" PRId64 ")"); + if (file) + as_bad_where (file, line, err, operand_number, + (int64_t) value, (int64_t) min, (int64_t) max); + else + as_bad (err, operand_number, + (int64_t) value, (int64_t) min, (int64_t) max); + } + else + { + /* xgettext:c-format. */ + err = _("operand out of range (%" PRId64 + " is not between %" PRId64 " and %" PRId64 ")"); + if (file) + as_bad_where (file, line, err, + (int64_t) value, (int64_t) min, (int64_t) max); + else + as_bad (err, (int64_t) value, (int64_t) min, (int64_t) max); + } +} + /* Insert an operand value into an instruction. */ static void @@ -670,7 +705,8 @@ s390_insert_operand (unsigned char *insn, const struct s390_operand *operand, offsetT val, const char *file, - unsigned int line) + unsigned int line, + int operand_number) { addressT uval; int offset; @@ -687,21 +723,16 @@ s390_insert_operand (unsigned char *insn, /* Check for underflow / overflow. */ if (val < min || val > max) { - const char *err = - _("operand out of range (%" PRId64 " not between %" PRId64 - " and %" PRId64 ")"); - if (operand->flags & S390_OPERAND_PCREL) { val = (offsetT) ((addressT) val << 1); min = (offsetT) ((addressT) min << 1); max = (offsetT) ((addressT) max << 1); } - if (file == (char *) NULL) - as_bad (err, (int64_t) val, (int64_t) min, (int64_t) max); - else - as_bad_where (file, line, - err, (int64_t) val, (int64_t) min, (int64_t) max); + + s390_bad_operand_out_of_range (operand_number, val, min, max, + file, line); + return; } /* val is ok, now restrict it to operand->bits bits. */ @@ -736,7 +767,8 @@ s390_insert_operand (unsigned char *insn, max++; } - as_bad_value_out_of_range (_("operand"), uval, (offsetT) min, (offsetT) max, file, line); + s390_bad_operand_out_of_range (operand_number, val, min, max, + file, line); return; } @@ -1364,7 +1396,7 @@ md_gather_operands (char *str, { /* Optional parameters might need to be ORed with a value so calling s390_insert_operand is needed. */ - s390_insert_operand (insn, operand, 0, NULL, 0); + s390_insert_operand (insn, operand, 0, NULL, 0, operand_number); break; } @@ -1394,12 +1426,12 @@ md_gather_operands (char *str, /* Write the operand to the insn. */ if (ex.X_op == O_illegal) - as_bad (_("illegal operand")); + as_bad (_("operand %d: illegal operand"), operand_number); else if (ex.X_op == O_absent) { if (opindex_ptr[0] == '\0') break; - as_bad (_("missing operand")); + as_bad (_("operand %d: missing operand"), operand_number); } else if (ex.X_op == O_register || ex.X_op == O_constant) { @@ -1410,7 +1442,7 @@ md_gather_operands (char *str, /* We need to generate a fixup for the expression returned by s390_lit_suffix. */ if (fc >= MAX_INSN_FIXUPS) - as_fatal (_("too many fixups")); + as_fatal (_("operand %d: too many fixups"), operand_number); fixups[fc].exp = ex; fixups[fc].opindex = *opindex_ptr; fixups[fc].reloc = BFD_RELOC_UNUSED; @@ -1420,29 +1452,32 @@ md_gather_operands (char *str, { if ((operand->flags & S390_OPERAND_LENGTH) && ex.X_op != O_constant) - as_bad (_("invalid length field specified")); + as_bad (_("operand %d: invalid length field specified"), + operand_number); if ((operand->flags & S390_OPERAND_INDEX) && ex.X_add_number == 0 && warn_areg_zero) - as_warn (_("index register specified but zero")); + as_warn (_("operand %d: index register specified but zero"), + operand_number); if ((operand->flags & S390_OPERAND_BASE) && ex.X_add_number == 0 && warn_areg_zero) - as_warn (_("base register specified but zero")); + as_warn (_("operand %d: base register specified but zero"), + operand_number); if ((operand->flags & S390_OPERAND_GPR) && (operand->flags & S390_OPERAND_REG_PAIR) && (ex.X_add_number & 1)) - as_bad (_("odd numbered general purpose register specified as " - "register pair")); + as_bad (_("operand %d: odd numbered general purpose register " + "specified as register pair"), operand_number); if ((operand->flags & S390_OPERAND_FPR) && (operand->flags & S390_OPERAND_REG_PAIR) && ex.X_add_number != 0 && ex.X_add_number != 1 && ex.X_add_number != 4 && ex.X_add_number != 5 && ex.X_add_number != 8 && ex.X_add_number != 9 && ex.X_add_number != 12 && ex.X_add_number != 13) - as_bad (_("invalid floating point register pair. Valid fp " - "register pair operands are 0, 1, 4, 5, 8, 9, " - "12 or 13.")); + as_bad (_("operand %d: invalid floating-point register (FPR) " + "pair (valid FPR pair operands are 0, 1, 4, 5, 8, 9, " + "12 or 13)"), operand_number); if (warn_regtype_mismatch && ex.X_op == O_register && !(opcode->flags & S390_INSTR_FLAG_PSEUDO_MNEMONIC)) { @@ -1481,7 +1516,7 @@ md_gather_operands (char *str, operand_number, expected_regtype); } } - s390_insert_operand (insn, operand, ex.X_add_number, NULL, 0); + s390_insert_operand (insn, operand, ex.X_add_number, NULL, 0, operand_number); } } else @@ -1567,11 +1602,11 @@ md_gather_operands (char *str, } if (suffix != ELF_SUFFIX_NONE && reloc == BFD_RELOC_UNUSED) - as_bad (_("invalid operand suffix")); + as_bad (_("operand %d: invalid operand suffix"), operand_number); /* We need to generate a fixup of type 'reloc' for this expression. */ if (fc >= MAX_INSN_FIXUPS) - as_fatal (_("too many fixups")); + as_fatal (_("operand %d: too many fixups"), operand_number); fixups[fc].exp = ex; fixups[fc].opindex = *opindex_ptr; fixups[fc].reloc = reloc; @@ -1591,7 +1626,8 @@ md_gather_operands (char *str, skipped. A length operand may not be skipped. */ operand = s390_operands + *(++opindex_ptr); if (!(operand->flags & (S390_OPERAND_INDEX|S390_OPERAND_BASE))) - as_bad (_("syntax error; missing '(' after displacement")); + as_bad (_("operand %d: syntax error; missing '(' after displacement"), + operand_number); /* Ok, skip all operands until S390_OPERAND_BASE. */ while (!(operand->flags & S390_OPERAND_BASE)) @@ -1611,7 +1647,8 @@ md_gather_operands (char *str, while (opindex_ptr[1] != '\0') { operand = s390_operands + *(++opindex_ptr); - as_bad (_("syntax error; expected ','")); + as_bad (_("operand %d: syntax error; expected ','"), + operand_number); break; } } @@ -1649,7 +1686,8 @@ md_gather_operands (char *str, { /* After the base register the parenthesised block ends. */ if (*str != ')') - as_bad (_("syntax error; missing ')' after base register")); + as_bad (_("operand %d: syntax error; missing ')' after base register"), + operand_number); else str++; omitted_base_or_index = 0; @@ -1668,7 +1706,8 @@ md_gather_operands (char *str, while (opindex_ptr[1] != '\0') { operand = s390_operands + *(++opindex_ptr); - as_bad (_("syntax error; expected ','")); + as_bad (_("operand %d: syntax error; expected ','"), + operand_number); break; } } @@ -1691,7 +1730,8 @@ md_gather_operands (char *str, operand = s390_operands + *(++opindex_ptr); if (!(operand->flags & S390_OPERAND_BASE)) - as_bad (_("syntax error; '%c' not allowed here"), *str); + as_bad (_("operand %d: syntax error; '%c' not allowed here"), + operand_number, *str); if (*str == ',') str++; str++; @@ -1711,7 +1751,8 @@ md_gather_operands (char *str, while (opindex_ptr[1] != '\0') { operand = s390_operands + *(++opindex_ptr); - as_bad (_("syntax error; expected ','")); + as_bad (_("operand %d: syntax error; expected ','"), + operand_number); break; } } @@ -2419,7 +2460,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) { /* Insert the fully resolved operand value. */ s390_insert_operand ((unsigned char *) where, operand, - (offsetT) value, fixP->fx_file, fixP->fx_line); + (offsetT) value, fixP->fx_file, fixP->fx_line, 0); return; } diff --git a/gas/testsuite/gas/s390/zarch-base-index-0-err.l b/gas/testsuite/gas/s390/zarch-base-index-0-err.l index e7d03ecdfe11..6332d9943496 100644 --- a/gas/testsuite/gas/s390/zarch-base-index-0-err.l +++ b/gas/testsuite/gas/s390/zarch-base-index-0-err.l @@ -1,74 +1,74 @@ .*: Assembler messages: .*:5: Error: bad expression -.*:5: Error: syntax error; missing '\)' after base register +.*:5: Error: operand 1: syntax error; missing '\)' after base register .*:8: Error: bad expression -.*:8: Error: syntax error; missing '\)' after base register +.*:8: Error: operand 2: syntax error; missing '\)' after base register .*:9: Error: bad expression -.*:9: Error: syntax error; missing '\)' after base register +.*:9: Error: operand 2: syntax error; missing '\)' after base register .*:12: Error: bad expression -.*:12: Error: syntax error; missing '\)' after base register +.*:12: Error: operand 2: syntax error; missing '\)' after base register .*:13: Error: bad expression -.*:13: Error: syntax error; missing '\)' after base register +.*:13: Error: operand 2: syntax error; missing '\)' after base register .*:14: Error: bad expression -.*:14: Error: syntax error; missing '\)' after base register +.*:14: Error: operand 2: syntax error; missing '\)' after base register .*:15: Error: bad expression -.*:15: Error: syntax error; missing '\)' after base register +.*:15: Error: operand 2: syntax error; missing '\)' after base register .*:16: Error: bad expression -.*:16: Error: syntax error; missing '\)' after base register -.*:17: Error: operand out of range \(0 is not between 1 and 256\) -.*:18: Error: missing operand -.*:19: Error: missing operand -.*:20: Error: missing operand +.*:16: Error: operand 2: syntax error; missing '\)' after base register +.*:17: Error: operand 1: operand out of range \(0 is not between 1 and 256\) +.*:18: Error: operand 1: missing operand +.*:19: Error: operand 1: missing operand +.*:20: Error: operand 1: missing operand .*:21: Error: bad expression -.*:21: Error: operand out of range \(0 is not between 1 and 256\) -.*:21: Error: operand out of range \(32 is not between 0 and 15\) -.*:21: Error: syntax error; missing '\)' after base register -.*:21: Error: syntax error; expected ',' +.*:21: Error: operand 1: operand out of range \(0 is not between 1 and 256\) +.*:21: Error: operand 1: operand out of range \(32 is not between 0 and 15\) +.*:21: Error: operand 1: syntax error; missing '\)' after base register +.*:21: Error: operand 1: syntax error; expected ',' .*:21: Error: bad expression .*:21: Error: found 'r', expected: '\)' -.*:21: Error: syntax error; missing '\)' after base register +.*:21: Error: operand 1: syntax error; missing '\)' after base register .*:21: Error: junk at end of line: `r2\)' -.*:22: Error: syntax error; missing '\(' after displacement -.*:23: Error: invalid length field specified -.*:26: Error: operand out of range \(0 is not between 1 and 16\) -.*:27: Error: missing operand -.*:28: Error: missing operand -.*:29: Error: missing operand +.*:22: Error: operand 1: syntax error; missing '\(' after displacement +.*:23: Error: operand 1: invalid length field specified +.*:26: Error: operand 1: operand out of range \(0 is not between 1 and 16\) +.*:27: Error: operand 1: missing operand +.*:28: Error: operand 1: missing operand +.*:29: Error: operand 1: missing operand .*:30: Error: bad expression -.*:30: Error: operand out of range \(0 is not between 1 and 16\) -.*:30: Error: operand out of range \(32 is not between 0 and 15\) -.*:30: Error: syntax error; missing '\)' after base register -.*:30: Error: syntax error; expected ',' +.*:30: Error: operand 1: operand out of range \(0 is not between 1 and 16\) +.*:30: Error: operand 1: operand out of range \(32 is not between 0 and 15\) +.*:30: Error: operand 1: syntax error; missing '\)' after base register +.*:30: Error: operand 1: syntax error; expected ',' .*:30: Error: found ',', expected: '\)' -.*:31: Error: syntax error; missing '\(' after displacement -.*:32: Error: operand out of range \(0 is not between 1 and 16\) -.*:33: Error: missing operand -.*:34: Error: missing operand -.*:35: Error: missing operand +.*:31: Error: operand 1: syntax error; missing '\(' after displacement +.*:32: Error: operand 2: operand out of range \(0 is not between 1 and 16\) +.*:33: Error: operand 2: missing operand +.*:34: Error: operand 2: missing operand +.*:35: Error: operand 2: missing operand .*:36: Error: bad expression -.*:36: Error: operand out of range \(0 is not between 1 and 16\) -.*:36: Error: syntax error; expected ',' -.*:37: Error: syntax error; missing '\(' after displacement -.*:38: Error: operand out of range \(0 is not between 1 and 16\) -.*:38: Error: operand out of range \(0 is not between 1 and 16\) -.*:39: Error: missing operand -.*:39: Error: missing operand -.*:40: Error: missing operand -.*:40: Error: missing operand -.*:41: Error: missing operand -.*:41: Error: missing operand +.*:36: Error: operand 2: operand out of range \(0 is not between 1 and 16\) +.*:36: Error: operand 2: syntax error; expected ',' +.*:37: Error: operand 2: syntax error; missing '\(' after displacement +.*:38: Error: operand 1: operand out of range \(0 is not between 1 and 16\) +.*:38: Error: operand 2: operand out of range \(0 is not between 1 and 16\) +.*:39: Error: operand 1: missing operand +.*:39: Error: operand 2: missing operand +.*:40: Error: operand 1: missing operand +.*:40: Error: operand 2: missing operand +.*:41: Error: operand 1: missing operand +.*:41: Error: operand 2: missing operand .*:42: Error: bad expression -.*:42: Error: operand out of range \(0 is not between 1 and 16\) -.*:42: Error: operand out of range \(32 is not between 0 and 15\) -.*:42: Error: syntax error; missing '\)' after base register -.*:42: Error: syntax error; expected ',' +.*:42: Error: operand 1: operand out of range \(0 is not between 1 and 16\) +.*:42: Error: operand 1: operand out of range \(32 is not between 0 and 15\) +.*:42: Error: operand 1: syntax error; missing '\)' after base register +.*:42: Error: operand 1: syntax error; expected ',' .*:42: Error: bad expression .*:42: Error: missing '\)' -.*:42: Error: operand out of range \(0 is not between 1 and 16\) -.*:42: Error: syntax error; expected ',' -.*:43: Error: syntax error; missing '\(' after displacement -.*:43: Error: syntax error; missing '\(' after displacement +.*:42: Error: operand 1: operand out of range \(0 is not between 1 and 16\) +.*:42: Error: operand 1: syntax error; expected ',' +.*:43: Error: operand 1: syntax error; missing '\(' after displacement +.*:43: Error: operand 2: syntax error; missing '\(' after displacement .*:46: Error: bad expression -.*:46: Error: syntax error; missing '\)' after base register +.*:46: Error: operand 2: syntax error; missing '\)' after base register .*:47: Error: bad expression -.*:47: Error: syntax error; missing '\)' after base register +.*:47: Error: operand 2: syntax error; missing '\)' after base register diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l index f222fe00093e..b2ee382b0f9d 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l @@ -1,21 +1,21 @@ .*: Assembler messages: .*:5: Error: bad expression -.*:5: Error: syntax error; missing '\)' after base register +.*:5: Error: operand 3: syntax error; missing '\)' after base register .*:8: Error: bad expression -.*:8: Error: syntax error; missing '\)' after base register +.*:8: Error: operand 2: syntax error; missing '\)' after base register .*:11: Warning: operand 2: expected general register name as base register .*:12: Error: bad expression -.*:12: Error: syntax error; missing '\)' after base register -.*:15: Error: missing operand -.*:16: Error: missing operand -.*:17: Error: invalid length field specified +.*:12: Error: operand 2: syntax error; missing '\)' after base register +.*:15: Error: operand 1: missing operand +.*:16: Error: operand 1: missing operand +.*:17: Error: operand 1: invalid length field specified .*:18: Error: bad expression -.*:18: Error: operand out of range \(0 is not between 1 and 256\) -.*:18: Error: operand out of range \(32 is not between 0 and 15\) -.*:18: Error: syntax error; missing '\)' after base register -.*:18: Error: syntax error; expected ',' +.*:18: Error: operand 1: operand out of range \(0 is not between 1 and 256\) +.*:18: Error: operand 1: operand out of range \(32 is not between 0 and 15\) +.*:18: Error: operand 1: syntax error; missing '\)' after base register +.*:18: Error: operand 1: syntax error; expected ',' .*:18: Error: bad expression .*:18: Error: found 'r', expected: '\)' -.*:18: Error: syntax error; missing '\)' after base register +.*:18: Error: operand 1: syntax error; missing '\)' after base register .*:18: Error: junk at end of line: `r2\)' -.*:19: Error: syntax error; missing '\(' after displacement +.*:19: Error: operand 1: syntax error; missing '\(' after displacement diff --git a/gas/testsuite/gas/s390/zarch-warn-areg-zero.l b/gas/testsuite/gas/s390/zarch-warn-areg-zero.l index decf896aecc7..b820e4c77a13 100644 --- a/gas/testsuite/gas/s390/zarch-warn-areg-zero.l +++ b/gas/testsuite/gas/s390/zarch-warn-areg-zero.l @@ -1,65 +1,65 @@ .*: Assembler messages: -.*:6: Warning: base register specified but zero -.*:7: Warning: base register specified but zero -.*:15: Warning: index register specified but zero -.*:16: Warning: index register specified but zero -.*:19: Warning: base register specified but zero -.*:20: Warning: base register specified but zero -.*:22: Warning: index register specified but zero -.*:22: Warning: base register specified but zero -.*:23: Warning: index register specified but zero -.*:23: Warning: base register specified but zero -.*:25: Warning: index register specified but zero -.*:25: Warning: base register specified but zero -.*:26: Warning: index register specified but zero -.*:26: Warning: base register specified but zero -.*:28: Warning: index register specified but zero -.*:28: Warning: base register specified but zero -.*:29: Warning: base register specified but zero -.*:30: Warning: base register specified but zero -.*:40: Warning: base register specified but zero -.*:41: Warning: base register specified but zero -.*:44: Warning: base register specified but zero -.*:45: Warning: base register specified but zero -.*:48: Warning: base register specified but zero -.*:48: Warning: base register specified but zero -.*:49: Warning: base register specified but zero -.*:49: Warning: base register specified but zero -.*:51: Warning: base register specified but zero -.*:52: Warning: base register specified but zero -.*:52: Warning: base register specified but zero -.*:53: Warning: base register specified but zero -.*:53: Warning: base register specified but zero -.*:55: Warning: base register specified but zero -.*:60: Warning: base register specified but zero -.*:61: Warning: base register specified but zero -.*:68: Warning: base register specified but zero -.*:69: Warning: base register specified but zero -.*:72: Warning: base register specified but zero -.*:73: Warning: base register specified but zero -.*:76: Warning: base register specified but zero -.*:76: Warning: base register specified but zero -.*:77: Warning: base register specified but zero -.*:77: Warning: base register specified but zero -.*:79: Warning: base register specified but zero -.*:80: Warning: base register specified but zero -.*:80: Warning: base register specified but zero -.*:81: Warning: base register specified but zero -.*:81: Warning: base register specified but zero -.*:83: Warning: base register specified but zero -.*:88: Warning: base register specified but zero -.*:89: Warning: base register specified but zero -.*:96: Warning: index register specified but zero -.*:97: Warning: index register specified but zero -.*:100: Warning: base register specified but zero -.*:101: Warning: base register specified but zero -.*:103: Warning: index register specified but zero -.*:103: Warning: base register specified but zero -.*:104: Warning: index register specified but zero -.*:104: Warning: base register specified but zero -.*:106: Warning: index register specified but zero -.*:106: Warning: base register specified but zero -.*:107: Warning: index register specified but zero -.*:107: Warning: base register specified but zero -.*:109: Warning: base register specified but zero -.*:110: Warning: base register specified but zero +.*:6: Warning: operand 1: base register specified but zero +.*:7: Warning: operand 1: base register specified but zero +.*:15: Warning: operand 2: index register specified but zero +.*:16: Warning: operand 2: index register specified but zero +.*:19: Warning: operand 2: base register specified but zero +.*:20: Warning: operand 2: base register specified but zero +.*:22: Warning: operand 2: index register specified but zero +.*:22: Warning: operand 2: base register specified but zero +.*:23: Warning: operand 2: index register specified but zero +.*:23: Warning: operand 2: base register specified but zero +.*:25: Warning: operand 2: index register specified but zero +.*:25: Warning: operand 2: base register specified but zero +.*:26: Warning: operand 2: index register specified but zero +.*:26: Warning: operand 2: base register specified but zero +.*:28: Warning: operand 2: index register specified but zero +.*:28: Warning: operand 2: base register specified but zero +.*:29: Warning: operand 2: base register specified but zero +.*:30: Warning: operand 2: base register specified but zero +.*:40: Warning: operand 1: base register specified but zero +.*:41: Warning: operand 1: base register specified but zero +.*:44: Warning: operand 2: base register specified but zero +.*:45: Warning: operand 2: base register specified but zero +.*:48: Warning: operand 1: base register specified but zero +.*:48: Warning: operand 2: base register specified but zero +.*:49: Warning: operand 1: base register specified but zero +.*:49: Warning: operand 2: base register specified but zero +.*:51: Warning: operand 1: base register specified but zero +.*:52: Warning: operand 1: base register specified but zero +.*:52: Warning: operand 2: base register specified but zero +.*:53: Warning: operand 1: base register specified but zero +.*:53: Warning: operand 2: base register specified but zero +.*:55: Warning: operand 1: base register specified but zero +.*:60: Warning: operand 2: base register specified but zero +.*:61: Warning: operand 2: base register specified but zero +.*:68: Warning: operand 1: base register specified but zero +.*:69: Warning: operand 1: base register specified but zero +.*:72: Warning: operand 2: base register specified but zero +.*:73: Warning: operand 2: base register specified but zero +.*:76: Warning: operand 1: base register specified but zero +.*:76: Warning: operand 2: base register specified but zero +.*:77: Warning: operand 1: base register specified but zero +.*:77: Warning: operand 2: base register specified but zero +.*:79: Warning: operand 1: base register specified but zero +.*:80: Warning: operand 1: base register specified but zero +.*:80: Warning: operand 2: base register specified but zero +.*:81: Warning: operand 1: base register specified but zero +.*:81: Warning: operand 2: base register specified but zero +.*:83: Warning: operand 1: base register specified but zero +.*:88: Warning: operand 2: base register specified but zero +.*:89: Warning: operand 2: base register specified but zero +.*:96: Warning: operand 2: index register specified but zero +.*:97: Warning: operand 2: index register specified but zero +.*:100: Warning: operand 2: base register specified but zero +.*:101: Warning: operand 2: base register specified but zero +.*:103: Warning: operand 2: index register specified but zero +.*:103: Warning: operand 2: base register specified but zero +.*:104: Warning: operand 2: index register specified but zero +.*:104: Warning: operand 2: base register specified but zero +.*:106: Warning: operand 2: index register specified but zero +.*:106: Warning: operand 2: base register specified but zero +.*:107: Warning: operand 2: index register specified but zero +.*:107: Warning: operand 2: base register specified but zero +.*:109: Warning: operand 2: base register specified but zero +.*:110: Warning: operand 2: base register specified but zero diff --git a/gas/testsuite/gas/s390/zarch-z9-109-err.l b/gas/testsuite/gas/s390/zarch-z9-109-err.l index 84d294de960a..b5460b65046d 100644 --- a/gas/testsuite/gas/s390/zarch-z9-109-err.l +++ b/gas/testsuite/gas/s390/zarch-z9-109-err.l @@ -1,2 +1,2 @@ .*: Assembler messages: -.*:3: Error: odd numbered general purpose register specified as register pair +.*:3: Error: operand 1: odd numbered general purpose register specified as register pair diff --git a/gas/testsuite/gas/s390/zarch-z900-err.l b/gas/testsuite/gas/s390/zarch-z900-err.l index cf8e9c2cefcc..2886802963ef 100644 --- a/gas/testsuite/gas/s390/zarch-z900-err.l +++ b/gas/testsuite/gas/s390/zarch-z900-err.l @@ -1,3 +1,3 @@ .*: Assembler messages: -.*:3: Error: operand out of range \(-4294967298 not between -4294967296 and 4294967294\) -.*:4: Error: operand out of range \(4294967296 not between -4294967296 and 4294967294\) +.*:3: Error: operand out of range \(-4294967298 is not between -4294967296 and 4294967294\) +.*:4: Error: operand out of range \(4294967296 is not between -4294967296 and 4294967294\) From patchwork Thu Feb 15 15:58:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 201605 Return-Path: Delivered-To: ouuuleilei@gmail.com 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Thu, 15 Feb 2024 15:58:30 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:30 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 14/14] s390: Be more verbose about missing operand type Date: Thu, 15 Feb 2024 16:58:21 +0100 Message-Id: <20240215155821.4065623-15-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: uk3W59yFvBD_BjTzJP4Ipk1j3sSACSlx X-Proofpoint-GUID: uk3W59yFvBD_BjTzJP4Ipk1j3sSACSlx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_15,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 phishscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150129 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981337904176024 X-GMAIL-MSGID: 1790981337904176024 Provide expected operand type in s390-specific assembler operand parsing error message: "error: operand : missing operand" With being one of: - base register - displacement - [vector] index register - length - access register - control register - floating-point register - general-purpose register - vector register - [un]signed number gas/ * config/tc-s390.c: Provide missing operand type in error message. * testsuite/gas/s390/zarch-base-index-0-err.l: Update test case result validation patterns to operand number in operand syntax error messages. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- gas/config/tc-s390.c | 38 ++++++++++++++++++- .../gas/s390/zarch-base-index-0-err.l | 30 +++++++-------- .../gas/s390/zarch-omitted-base-index-err.l | 4 +- 3 files changed, 54 insertions(+), 18 deletions(-) diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 786c372a9c1a..f43314666e1f 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -1329,6 +1329,41 @@ s390_elf_cons (int nbytes /* 1=.byte, 2=.word, 4=.long */) demand_empty_rest_of_line (); } +static const char * +operand_type_str(const struct s390_operand * operand) +{ + if (operand->flags & S390_OPERAND_BASE) + return _("base register"); + else if (operand->flags & S390_OPERAND_DISP) + return _("displacement"); + else if (operand->flags & S390_OPERAND_INDEX) + { + if (operand->flags & S390_OPERAND_VR) + return _("vector index register"); + else + return _("index register"); + } + else if (operand->flags & S390_OPERAND_LENGTH) + return _("length"); + else if (operand->flags & S390_OPERAND_AR) + return _("access register"); + else if (operand->flags & S390_OPERAND_CR) + return _("control register"); + else if (operand->flags & S390_OPERAND_FPR) + return _("floating-point register"); + else if (operand->flags & S390_OPERAND_GPR) + return _("general-purpose register"); + else if (operand->flags & S390_OPERAND_VR) + return _("vector register"); + else + { + if (operand->flags & S390_OPERAND_SIGNED) + return _("signed number"); + else + return _("unsigned number"); + } +} + /* Return true if all remaining operands in the opcode with OPCODE_FLAGS can be skipped. */ static bool @@ -1431,7 +1466,8 @@ md_gather_operands (char *str, { if (opindex_ptr[0] == '\0') break; - as_bad (_("operand %d: missing operand"), operand_number); + as_bad (_("operand %d: missing %s operand"), operand_number, + operand_type_str(operand)); } else if (ex.X_op == O_register || ex.X_op == O_constant) { diff --git a/gas/testsuite/gas/s390/zarch-base-index-0-err.l b/gas/testsuite/gas/s390/zarch-base-index-0-err.l index 6332d9943496..26187c93d4b3 100644 --- a/gas/testsuite/gas/s390/zarch-base-index-0-err.l +++ b/gas/testsuite/gas/s390/zarch-base-index-0-err.l @@ -16,9 +16,9 @@ .*:16: Error: bad expression .*:16: Error: operand 2: syntax error; missing '\)' after base register .*:17: Error: operand 1: operand out of range \(0 is not between 1 and 256\) -.*:18: Error: operand 1: missing operand -.*:19: Error: operand 1: missing operand -.*:20: Error: operand 1: missing operand +.*:18: Error: operand 1: missing length operand +.*:19: Error: operand 1: missing length operand +.*:20: Error: operand 1: missing length operand .*:21: Error: bad expression .*:21: Error: operand 1: operand out of range \(0 is not between 1 and 256\) .*:21: Error: operand 1: operand out of range \(32 is not between 0 and 15\) @@ -31,9 +31,9 @@ .*:22: Error: operand 1: syntax error; missing '\(' after displacement .*:23: Error: operand 1: invalid length field specified .*:26: Error: operand 1: operand out of range \(0 is not between 1 and 16\) -.*:27: Error: operand 1: missing operand -.*:28: Error: operand 1: missing operand -.*:29: Error: operand 1: missing operand +.*:27: Error: operand 1: missing length operand +.*:28: Error: operand 1: missing length operand +.*:29: Error: operand 1: missing length operand .*:30: Error: bad expression .*:30: Error: operand 1: operand out of range \(0 is not between 1 and 16\) .*:30: Error: operand 1: operand out of range \(32 is not between 0 and 15\) @@ -42,21 +42,21 @@ .*:30: Error: found ',', expected: '\)' .*:31: Error: operand 1: syntax error; missing '\(' after displacement .*:32: Error: operand 2: operand out of range \(0 is not between 1 and 16\) -.*:33: Error: operand 2: missing operand -.*:34: Error: operand 2: missing operand -.*:35: Error: operand 2: missing operand +.*:33: Error: operand 2: missing length operand +.*:34: Error: operand 2: missing length operand +.*:35: Error: operand 2: missing length operand .*:36: Error: bad expression .*:36: Error: operand 2: operand out of range \(0 is not between 1 and 16\) .*:36: Error: operand 2: syntax error; expected ',' .*:37: Error: operand 2: syntax error; missing '\(' after displacement .*:38: Error: operand 1: operand out of range \(0 is not between 1 and 16\) .*:38: Error: operand 2: operand out of range \(0 is not between 1 and 16\) -.*:39: Error: operand 1: missing operand -.*:39: Error: operand 2: missing operand -.*:40: Error: operand 1: missing operand -.*:40: Error: operand 2: missing operand -.*:41: Error: operand 1: missing operand -.*:41: Error: operand 2: missing operand +.*:39: Error: operand 1: missing length operand +.*:39: Error: operand 2: missing length operand +.*:40: Error: operand 1: missing length operand +.*:40: Error: operand 2: missing length operand +.*:41: Error: operand 1: missing length operand +.*:41: Error: operand 2: missing length operand .*:42: Error: bad expression .*:42: Error: operand 1: operand out of range \(0 is not between 1 and 16\) .*:42: Error: operand 1: operand out of range \(32 is not between 0 and 15\) diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l index b2ee382b0f9d..9ff6392915e7 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l @@ -6,8 +6,8 @@ .*:11: Warning: operand 2: expected general register name as base register .*:12: Error: bad expression .*:12: Error: operand 2: syntax error; missing '\)' after base register -.*:15: Error: operand 1: missing operand -.*:16: Error: operand 1: missing operand +.*:15: Error: operand 1: missing length operand +.*:16: Error: operand 1: missing length operand .*:17: Error: operand 1: invalid length field specified .*:18: Error: bad expression .*:18: Error: operand 1: operand out of range \(0 is not between 1 and 256\)