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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790956212336616966 X-GMAIL-MSGID: 1790956212336616966 Document the Adreno 750 GMU found on the SM8650 platform. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Acked-by: Conor Dooley --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 4e1c25b42908..b3837368a260 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -224,6 +224,7 @@ allOf: enum: - qcom,adreno-gmu-730.1 - qcom,adreno-gmu-740.1 + - qcom,adreno-gmu-750.1 then: properties: reg: From patchwork Thu Feb 15 09:20:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 201319 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp282634dyb; Thu, 15 Feb 2024 01:49:48 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVCmYjxTbSMQK53jJB7s1qyyilJEGAEPYRZPVuroCzE+LZlrJkECIavWw24IX3zxIwaGUb0r1zVl8ZMtmj+6eBeY9+Sjg== X-Google-Smtp-Source: AGHT+IGu+T0Nu1uN03Nk/wJ98s3RUS78KU+biu5L3AGuJBRVbrBH2U6LnXgkTBjLIbDyp68bo8z8 X-Received: by 2002:a05:6a00:148a:b0:6e0:ef8f:6bea with SMTP id v10-20020a056a00148a00b006e0ef8f6beamr1490246pfu.4.1707990587812; Thu, 15 Feb 2024 01:49:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707990587; cv=pass; d=google.com; s=arc-20160816; b=hXWpSoopztCoJ/pTx5IMsM5o114ycg3mRTOaUcjHnBwxOaD+p7gj5eKkIoj5UuHbIv bFfnX4cukXY547MXRfoF6T1LDIouAFqCsRyD/Mo82mjB9YlmwbDjn+rMIwuTBRBmdAcD ZFcU7oNvyV95ZdRVF66NSQjleaUj5W2U9/MeZOXH+NfbeFDTLzKP9FTxNVleQWr5w9ky 3R1rHJlY87k7/rLHyvYoUaxEsKxxCCm7ZGvw2/PPjuuY6RYcsk/K4Jknge/yEc9rSSqH /J+woEMw9fjgtL4tv5c7CXS71sSv5dSe+iLKmiZLQYWcS+XRfHUsF5Zl79oDkznvEmIQ Kvwg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=rJagULZ78/2FNiklIv2V0yaJYekfWzVBl7+5o+wg9ug=; fh=GU5Qjw8pI1KoNMvgxRzepv3NqA+sqXrJzXKuIR0wUnI=; b=wYoc3g+80ez3RpAd4CZBm9pX99QFV+oopOhxcbdD5Xbl312q1+ZX98WEpsKiWBGaAb Nl5mGFRkS+itJQG6A20XT617uRPlQfdPAZRH3w01IPL6jvhQPpkI60RMMjTOjastK1Ne y6hrDaXu/PZv16IGzXSy5urdthSuL3uFhMdict+7um39UnckW7GlFuODngJxikmMgIhf /85Pa4sDAyZk/W79Qw0p1LehSxK27qj43HsqDox6eiS5u5N/m9y/oRp+xuox+ttZTC4T +f04e3+W5GR/pIezJg7dpGCTOmuirNPp1PMFGfGW1MolBkOOraXbV5/hkXhq1RNgF5FK 3UHg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sZJBTARU; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-66514-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-66514-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790956516087777356 X-GMAIL-MSGID: 1790957938607736173 Document the GPU SMMU found on the SM8650 platform. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index a4042ae24770..3ad5c850f3bf 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -93,6 +93,7 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -508,7 +509,10 @@ allOf: - if: properties: compatible: - const: qcom,sm8550-smmu-500 + contains: + enum: + - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 then: properties: clock-names: @@ -544,7 +548,6 @@ allOf: - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 then: properties: From patchwork Thu Feb 15 09:20:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 201300 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp271262dyb; Thu, 15 Feb 2024 01:22:34 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWT60mNAuado8PFi/sS8KuQH+EXKO8VOE2cjlKC6msTJy2dDtQEmG6lYy9jUxUTFmSiycAGqATrNfZ/5yDm18pe/c51ew== X-Google-Smtp-Source: AGHT+IHU2W/9YufngBpIadKYDIv5BiFARkX5GA5Ry27utK3qkmCGR0h6VuAZoU+VX1w9l98vB6HW X-Received: by 2002:a0c:aa5d:0:b0:68f:1aa7:12bf with SMTP id e29-20020a0caa5d000000b0068f1aa712bfmr595554qvb.22.1707988954591; Thu, 15 Feb 2024 01:22:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707988954; cv=pass; d=google.com; s=arc-20160816; b=Gyk1Ozblagk4kBERa5cBRkWlEwHcHH0DA5lXXHxVUPn5/mGRyx38ohYndWWPamicHi pFp3bx2q2A9UcPrahfwVJXDNmNeio53IVUkOoB4SQvctMbz3U8pLyJa2t1hEeHvu4UDY HBwIyQ2tvDPFH2zFZsD/QLADtTAYPSBHdhYszlLAJyE1uln1OdWOX+MKOKcYs2rcexuM F0QFKp3C5QTR2p2mC1WDoNXpwOC6SFVTIxNM94aZ7R5n9k8Txp102RrlZzzaabB5DVuD MByx3sPEfONWTNyb/UdwsDQKjv0q0c7ZDio08noNVCycopE1shPvQNiNdYLtZPqMAamK 4RKQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=5ygFt5WEvBpqUpx/ZfEWpp/27W6mJ4fXmmus9YC0aao=; fh=8p6AVpgHJDU6IIA6jQHAR6nXTr0jRPDluJtTzxJtHVM=; b=YD+kW8RT/pXTzuy4yR6A3mOJzcIjoobs5IVfLVerW6FcFYJR0/AsRptJOPXgrag/Xn 5e/dIQ4y0QqCLNabuoW6tjj1rXL79Euweh2R4tkZZ6VsA4Csb9rs+DYzfFjcNIt1dLVE o6YqdjtJWQOJ2+qnEX+ujAG6KOMbnnHAALSMML2Mq/IxBJPe+RvQ++S/XxCzoyuGkz7q CHnGs1n8Kcp+bABuORlvssc81fEfce7DTSZVL8WOil2AUxy9eXHBOFJZ4rmb6xpPO8BL e5oNtvvG1wSMuD3cvy2lhkEpcms4ZhVzXlntbRiWcf7p61JiLYiZHYX8GnSM8EhMee7L FCWg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uT5LL9Zd; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-66515-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-66515-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790956226054972337 X-GMAIL-MSGID: 1790956226054972337 Sync missing regs for A750 clock gating control related registers from Mesa a6xx.xml.h generated file. Those registers were added in the !27576 merge request [1]. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27576 Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 863b5e3b0e67..58877464692a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1725,6 +1725,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 +#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad + #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 @@ -1939,12 +1941,19 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d +#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e + +#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f + #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122 +#define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001 + #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff From patchwork Thu Feb 15 09:20:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 201316 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp280472dyb; Thu, 15 Feb 2024 01:44:08 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXYOCCn2v/42hsO1TAP56sU4UFN1M2VOfTKag1YI2j52IEnzl15QVPOei5j3r+GqW/kExNFsegBefIlirIOu6yrWHaq8A== X-Google-Smtp-Source: AGHT+IEIydbagZX5VtNmX2S9EINcAEYdP42+qXKph9KQ1Erbu3GJuvc8drCk14lXiwmnDFbU9Otp X-Received: by 2002:a05:6808:640b:b0:3c0:4638:3d5e with SMTP id fg11-20020a056808640b00b003c046383d5emr1730364oib.4.1707990248555; Thu, 15 Feb 2024 01:44:08 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707990248; cv=pass; d=google.com; s=arc-20160816; b=Ej3FEb3wF8BVZ0kOWCXDMhlXPjStfonnPnJHclSJOAE4g6clkCFfJHY6r0f19RiPob 1I6/ws3BzJZTgIOh04OfhcRKVHJfi2eaks/bLFeeRFRkHpQxyI42WiDYHvbMTWljaXyf rmsCfimBEY8Hd1YcIgznYTucP2HDtn7luOqgGlCdqHueI3nT1QD6IPyZpCUI0wEv5Z6X dbnzlX3d0VFmEyzAMQYSlvrK81JjPJHRBTf/9u+JfLg/7mwQD66gCJKuOA/TUDuehr5v 1g8+wa2FMsUOsNbFoZwTQQBVxLzbHvYdCKhpMRg0bnWI08QzuPuIcUF9txN7VqFxdd6J pCUA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=Wz/R+OttvCXysokn6zYBH1UjPAsuemNSOQvMKQiaZxo=; fh=0nnbPQiNtnebE/OPCtdvMsj4ur0PjkL1wMR4BjJGyko=; b=lpYgtQnYAyoUykJNVpslmZ7s7fKNDtiDGRneYsMRjZ4RgQhqOA6uO0h+FGwDVQMadM 49muzmDwWhbJKe9glI9Vpp1tlQEOi/j+iQQA0iM9/o0PoXJbeVv7v1Cz2IDVy50B2QKH 0f71MsZEKIYG5tp3iIvCezSFzRhJf0q6Ar7jxrBguQju+zue3LD2Jc8yQuKftbbgz/fx IExwb6mkyORFv4NlLt8ymBq3UEcsSubbf/PV1Akj45CvIg4oPDhzKKxi/bTFutqeCBvu T8Eqeo29jG5mLYkJbvcQ/Lr/8l4wJTkYi18uOnw6mnhpq5fxZ2OswhhWxcSqmpOumvLA cCyg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WSq2SiQQ; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-66516-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-66516-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790957582992939977 X-GMAIL-MSGID: 1790957582992939977 Add support for the A750 GPU found on the SM8650 platform Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++++++-- 4 files changed, 49 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 8c4900444b2c..325881d8ff08 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -842,6 +842,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) */ if (adreno_is_a740(adreno_gpu)) chipid_min = 2; + else if (adreno_is_a750(adreno_gpu)) + chipid_min = 9; else return -EINVAL; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c9c55e2ea584..475b601a48ee 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -961,7 +961,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) unsigned int i; u32 val, clock_cntl_on, cgc_mode; - if (!adreno_gpu->info->hwcg) + if (!(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu))) return; if (adreno_is_a630(adreno_gpu)) @@ -982,6 +982,25 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) state ? 0x5555 : 0); } + if (!adreno_gpu->info->hwcg) { + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); + gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); + + if (state) { + gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); + + if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, + val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { + dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); + return; + } + + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); + } + + return; + } + val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); /* Don't re-program the registers if they are already correct */ @@ -1239,7 +1258,9 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) count = ARRAY_SIZE(a660_protect); count_max = 48; BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); - } else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) { + } else if (adreno_is_a730(adreno_gpu) || + adreno_is_a740(adreno_gpu) || + adreno_is_a750(adreno_gpu)) { regs = a730_protect; count = ARRAY_SIZE(a730_protect); count_max = 48; @@ -2880,7 +2901,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || - config->info->family == ADRENO_7XX_GEN2; + config->info->family == ADRENO_7XX_GEN2 || + config->info->family == ADRENO_7XX_GEN3; a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2ce7d7b1690d..e2582c91d7e7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -522,6 +522,20 @@ static const struct adreno_info gpulist[] = { .zapfw = "a740_zap.mdt", .hwcg = a740_hwcg, .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ + .family = ADRENO_7XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "gen70900_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70900.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "gen70900_zap.mbn", + .address_space_size = SZ_16G, }, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index bc14df96feb0..9e9415df2cea 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -48,6 +48,7 @@ enum adreno_family { ADRENO_6XX_GEN4, /* a660 family */ ADRENO_7XX_GEN1, /* a730 family */ ADRENO_7XX_GEN2, /* a740 family */ + ADRENO_7XX_GEN3, /* a750 family */ }; #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) @@ -423,12 +424,17 @@ static inline int adreno_is_a740(struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x43050a01; } -/* Placeholder to make future diffs smaller */ +static inline int adreno_is_a750(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x43051401; +} + static inline int adreno_is_a740_family(struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return gpu->info->family == ADRENO_7XX_GEN2; + return gpu->info->family == ADRENO_7XX_GEN2 || + gpu->info->family == ADRENO_7XX_GEN3; } static inline int adreno_is_a7xx(struct adreno_gpu *gpu) From patchwork Thu Feb 15 09:20:27 2024 Content-Type: text/plain; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790957862365780384 X-GMAIL-MSGID: 1790957862365780384 Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++++++++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 62e6ae93a9a8..27dcef27b6ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2589,6 +2589,128 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43051401", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-629000000 { + opp-hz = /bits/ 64 <629000000>; + opp-level = ; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = ; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-level = ; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + }; + + opp-231000000 { + opp-hz = /bits/ 64 <231000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = ; + }; + + opp-260000000 { + opp-hz = /bits/ 64 <260000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8650-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -2602,6 +2724,50 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; From patchwork Thu Feb 15 09:20:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 201303 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp271988dyb; Thu, 15 Feb 2024 01:24:20 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXqCBarx/BN39tWWuBNCn7TtI66OSx3wQp7Z4RPvYGtbuvFwi9oONu0TK4oX8NolwcnBVaW8l2+gI2/73eT2Y8htFMwCQ== X-Google-Smtp-Source: AGHT+IE6CAg4OCLmFSZEMdPBiC16+/y716y0Grwaiucdkba69DEg/Yt+J+QtCGPLqNp+J+vM9I3i X-Received: by 2002:a17:907:11c7:b0:a3c:ffbb:b47c with SMTP id va7-20020a17090711c700b00a3cffbbb47cmr774016ejb.72.1707989060128; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790956337080652030 X-GMAIL-MSGID: 1790956337080652030 Add path of the GPU firmware for the SM8650-QRD board Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b07cac2e5bc8..dc91f0bf4b8c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -766,6 +766,14 @@ &ipa { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21";