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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7k008333; Thu, 15 Feb 2024 02:55:24 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 1/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable camera peripherals Date: Thu, 15 Feb 2024 14:25:10 +0530 Message-ID: <20240215085518.552692-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790954668010168482 X-GMAIL-MSGID: 1790954668010168482 CSI cameras are controlled using I2C. On J721S2 Common Processor Board, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. Common Processor Board schematics: https://www.ti.com/lit/zip/sprr411 J721S2 SoM schematics: https://www.ti.com/lit/zip/sprr439 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. .../dts/ti/k3-j721s2-common-proc-board.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 361365bb5523..5631735c9b7a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,13 @@ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -356,6 +363,24 @@ exp2: gpio@22 { }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { /* eMMC */ status = "okay"; From patchwork Thu Feb 15 08:55:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 201271 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp259355dyb; Thu, 15 Feb 2024 00:56:58 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUWaG/v4W8Rm7yRKFAFYyGeQgL0Ugu6QGLXTXKz4uxRHLxK+6oX15vCk5HYGS+vhuOX268g81SV6KUf32gv0G0xDpIb+g== X-Google-Smtp-Source: AGHT+IHw7SCXNI0dzDxFXe8RTkS5FIm0QqnGv3rHnYRYhxAz6p5tqpkrUPc79iVqFD/8ZsrFLPp5 X-Received: by 2002:a05:6214:4107:b0:68c:7c27:fc83 with SMTP id kc7-20020a056214410700b0068c7c27fc83mr1201648qvb.18.1707987418546; Thu, 15 Feb 2024 00:56:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707987418; cv=pass; d=google.com; s=arc-20160816; b=c4uOGCeXpJiU/pV1tgX4YB484V1CH3+oGD6g1tKjx76p/kGHVdDnHOXTZm0Gf8RLjc ymeQt17zn1J0LwlsNZq7vR0NI/b/w617dFx6apnGGirzwfrNQH5w8VyjrtOD28oe5IWG 7RUVUZ6Aa+OHHlzlVT/xYOHX6zG5N51MNhsCLQGOZbnpQ82NoULBUWPNi/MKdKZo5Fmw FudBuM5Box3/EWobGAiE1ormbNZBCf5CUgbymQECv6XXHMmSNHrSdGTRrEBebhKJ/SKC vcI1yzqE51B3eRkDjL4fZ62AsVZK69FRIbdk9rlEkK3c/8M71o0ZqU4I/WzYtMC3o7Ts HcyQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=x/k1nR+0Oofrre15QvBy2e7fuQCsoXlHJGCKKMdrXLU=; fh=Q0qfAugDSiRH+GkuTIKfokhNWAVNOIduw9aJ54bFjbE=; b=M4eUtIg+Mra8za/YGlXELYGPEqEguD75Nyg7O18wb3b6s5LDFKmaE/YF63usIDGnJz HaQtWOI1dBew7H1SxoN4PA8GRXeCDSbAOVLPrKdvITy29vdqWq+YKKPOZBKUkwBm3vQq UeSZ9a6bxAuZnZERHCCq9JvYHtOjh/X365aS3v2MYRl36VRneFhefA9IjFj/7OwvyWiv BZ4DAFBl9SkrTwMOIJzX/n5VcjtyNCgxzX1fjs9bw/6eHtpRoAb5YsYk5opYqhI94lEY UhsFH1hcUZMWOLnJpaubUjthZR3nEtbUFlYfwmB+NUOSlNUyDdiSMmaSKXhpSU+Dv+Sn cGEQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gFYYWw2k; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-66457-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-66457-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7l008333; Thu, 15 Feb 2024 02:55:28 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 2/9] arm64: dts: ti: k3-j784s4-evm: Enable camera peripherals Date: Thu, 15 Feb 2024 14:25:11 +0530 Message-ID: <20240215085518.552692-3-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790954615373539606 X-GMAIL-MSGID: 1790954615373539606 CSI cameras are controlled using I2C. On J784S4 EVM, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. J784S4 EVM schematics: https://www.ti.com/lit/zip/sprr458 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 57e7cb8ea2b8..bb2558b68381 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -297,6 +297,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -761,6 +768,24 @@ exp2: gpio@22 { }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ From patchwork Thu Feb 15 08:55:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 201274 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp259726dyb; Thu, 15 Feb 2024 00:58:00 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWStk3hy1fJteiJ46ZrAeLdBPRBb8spycD3A0aA0U/jmGLVLPLNCBTspsinOvL8YkK+YwkrBH1pI/SaVkLPieizOXMsrQ== X-Google-Smtp-Source: AGHT+IGJZhdsg+3eh8uaTSvif8U0C63Upt1x8FvyyMXa7oJ/mUDdE3iAms543nfMJwoyrhwKPcT5 X-Received: by 2002:a05:6512:124c:b0:511:85ae:8985 with SMTP id fb12-20020a056512124c00b0051185ae8985mr1044719lfb.53.1707987480264; Thu, 15 Feb 2024 00:58:00 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707987480; cv=pass; d=google.com; s=arc-20160816; b=bZu5kzupZ0pPIoYDhmVj6MYWPnL7FyRLsKoNXRT9YWrGs8Huz3Hqft8ndGm1xfvGUa uQqKH3uUIRdqL8NDsP7aPdeTlJu19osv0QbIvvhBKWz3xbyxK4U2kNYAvHMJGCcgzwN5 fnpKMlkLJwGsJA0u5duk0iuJ7Xi525qnIFdkUY90p+/nLNrBVxWx2Lcm4gof3EFjVJBU ewrZrDof6K5h9FBm4LxAiaR2hlbraQyoN5y7KKJgbQHGubOTrGaKwsMumXJd6oY/RXFD kEBlzfd72ATm+PyxDvfS817r+mkkUWcZWl8krJ1/TZMqFH3JkS0XRw8kN/8azLBn1b/I re/w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=qA03AiPQ76ODZlkdfgCJ4bbvmcQFxo0DGUcdzk429lc=; fh=Q0qfAugDSiRH+GkuTIKfokhNWAVNOIduw9aJ54bFjbE=; b=QaXrqBRQU1BRexPNUvaBLfxMolXdxpGZoECd8olaP/dkb5vlHXvEwW16MqeSt+c2E0 Bjgv6WpR4BfD1toSItVceJYaLciRq2bVB6viCBdVE3JkK1IrfC0MNFzduL4GJRBCALlT 09hmfHDC5m/DnXMGPiCqPFqpuW7rwlEG5tIxqLZSOdIyn3AExNvnadEs4emZ/X6en3Xy Lpk+VICSFQ9k3bpitxFKCec+45xDqDQRT5Pl0+26bLdFIUzpguaPHbM4oojXWwwUa++I 8gnyJe/NgyOoBkDIkydLIyImJELxKpPFUkPcbAXpeYnTMLLORzrkP7MaTI5L6wPEzYPr iWQg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=e+Hsyz3z; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-66460-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-66460-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7m008333; Thu, 15 Feb 2024 02:55:32 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 3/9] arm64: dts: ti: k3-am68-sk-base-board: Enable camera peripherals Date: Thu, 15 Feb 2024 14:25:12 +0530 Message-ID: <20240215085518.552692-4-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790954680161733238 X-GMAIL-MSGID: 1790954680161733238 CSI cameras are controlled using I2C. On AM68 Starter Kit, this is routed to I2C-1, so enable the instance and the TCA9543 I2C switch on the bus. AM68 SK schematics: https://www.ti.com/lit/zip/sprr463 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. .../boot/dts/ti/k3-am68-sk-base-board.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index f48155dd16a3..d743f023cdd9 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -169,6 +169,13 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp3 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; }; &main_pmx0 { @@ -186,6 +193,13 @@ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -431,6 +445,42 @@ exp1: gpio@21 { }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + status = "okay"; + + exp3: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", + "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_i2c4 { status = "okay"; pinctrl-names = "default"; From patchwork Thu Feb 15 08:55:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 201280 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp260141dyb; Thu, 15 Feb 2024 00:59:09 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVCpaiDPZfETyO5/tf4kcs/A6BEqzCJj4wdDQFivD45I0VuDVXmfOhyDOM6MRfKBUAeXE9WS9acZp8Y8MEx04XZmcJhzw== X-Google-Smtp-Source: AGHT+IEcoquXrDbmuSRMrmYpKkupap4CYdx8k6oE/AAro32cUpUK0gsWBaJve2LL0jxzplVdiV/l X-Received: by 2002:a17:903:58d:b0:1d9:4282:4be8 with SMTP id jv13-20020a170903058d00b001d942824be8mr971524plb.25.1707987549659; Thu, 15 Feb 2024 00:59:09 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707987549; cv=pass; d=google.com; s=arc-20160816; b=GsbMya22Zy7uHoZs2Ep3MRCJEh9n2DpXjVyBHx+Js10WhJsTABwW31ws7hSResQspC DSwvtlzTvLXNEbBOXVgWj0JToLvj9XmGedEQ0ChxlvhUBTVZfByHJdcqDDriv2vKJZB+ vQDwu7c8o7zShOVtuXCECnCR6FD3LwAm+V3awSOl4sMUbtZjHMhbMegJjJw1JXk4miYw qBrb73tpLtXycDFOkq+8uug+ktBULCm3GjIGHtCxR2Roq1sb6qNcplHHY/oYZPfRmFIL Mj3DbmvnFT7G6s0kwZJwtb3G5uTAetPBP2SWujNCuvsw8oGXU96+bZCvzRc1pjPs2h6I Cw6g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=5f06S+zYcwCeq2tvXJVvkkRoi5yjPpWJZR1EyBYAnic=; fh=Q0qfAugDSiRH+GkuTIKfokhNWAVNOIduw9aJ54bFjbE=; b=bZy592Ch6qCkhymyci8HSKrdJfHhG4aqDlcfYSvW+AJs1vF7JR7VIVcjffHXkaKD2c 0gCvlwZXloP5PUiGG1KOAFS+jb0WsJlHW3gOctPBO26p7hP5MmgYKQ/PLhupFAAozqXT 5788bUss7Ob4kmX4+CzlN1lH8RoIfciXNGESOlWpuaICFBagy1ozjpSUEmXW+i/w2vcc 6hCyQSVnjP3xkFjgCJrYEjzqA3l1jkZjUgcoEchrU/Un8cU/Q30QmcL9nrVfmMpyvw9p vPHi6oZP/7weU84e6NcLq5lJH+oyAPt+54DTsn+UilMI3KRKky7rCcWq+NGSXbgMxvZq oVAw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="Ar/c+M6e"; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-66459-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-66459-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7n008333; Thu, 15 Feb 2024 02:55:36 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 4/9] arm64: dts: ti: k3-am69-sk: Enable camera peripherals Date: Thu, 15 Feb 2024 14:25:13 +0530 Message-ID: <20240215085518.552692-5-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790954752404931707 X-GMAIL-MSGID: 1790954752404931707 CSI cameras are controlled using I2C. On AM69 Starter Kit, this is routed to I2C-1, so enable the instance, TCA9543 I2C switch and the TCA6408 GPIO expander on the bus. AM69 SK has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. AM69 SK schematics: https://www.ti.com/lit/zip/sprr466 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-am69-sk.dts | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 5f0a43a69333..46cf90bb3eb8 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -322,6 +322,14 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; + }; &main_pmx0 { @@ -341,6 +349,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -775,6 +790,42 @@ exp1: gpio@21 { }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", + "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ From patchwork Thu Feb 15 08:55:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 201275 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp259773dyb; Thu, 15 Feb 2024 00:58:08 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXXFOVrUna973qtZHOB6L4ZEZMuwl3gDO3TNMttcOXA8ShyWBBeQ4jvFijf0WMZatTg72Q72p1m3hB9yPit02TpryKDXQ== X-Google-Smtp-Source: AGHT+IGAJjH599YMhQ+5iMPa/5rFXU7luy3Wv15QUCO6Y0ktsG+A19PuTotVUJlFa5YNJtaGnz0p X-Received: by 2002:a05:6402:38c:b0:561:f4bc:606 with SMTP id o12-20020a056402038c00b00561f4bc0606mr981113edv.0.1707987487977; Thu, 15 Feb 2024 00:58:07 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707987487; cv=pass; d=google.com; s=arc-20160816; b=eLTE6kUIfgAY7gD2b9kIEtMIgAu+5vtLE/5vinBzWhHB+WccI8uUpPVQp1EeRSOuq1 uJApk84Oob9wKrUIGKXV2cRuJNPOzfflQF8m6jDdXDvGt/PbLj87TjY34YR8GMBa4XRh uEf8F0uD5d98/qDaVgEAZYx5u2gI0eNj3itzIHQ+PNCVrNWcSWXnDht8CD3XIgjhPREb wVX+AOPfdJSenzwoY+pE2q4k0ScL3cC7zyh0xLwmlkO3Hc46boDuz/M5mhFKRgFZEdVo +rfZ25RKP2MTff+UcfRgDKEPuJ5SHb/JtmSi6RhbrpyWi2zRnN6VZgcm8kgfSfV4WWxM NSlA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=WftwmOV6VJghVZe5M9HH30MtAUbPXmvOMWm7w3lYE+c=; fh=Q0qfAugDSiRH+GkuTIKfokhNWAVNOIduw9aJ54bFjbE=; b=bF/GzviPv+QOeKX8g8cVs8ZBR9wDiZgitoLddeeo6TavfuFdhDh+qR4EpvSbqhLnNL h6Fxdw/KGeMi2ACGjpie6bugANYZp527S7MB1+Lshtk8YJsOnYAEWbGfdFEZ6w6wTLzJ EO5FrpMXowglsJtbTbbnPi7DplIpUt3pDti2iMZLXYO5zaLuywdIi3QRyrHXcLIFGq1h n9eSLHeT2ra91c7tS06U8pr+Dk1M70mRj2lk8HOuOx1XYMq9KlFH395WMBN4mVt/wzD0 cBeUocCjt6MT67uPHiUXwZsDdcwg6HHUTDTTfSi8zv9NAVnEf2YbfzQf4wimcPzz9uxu 01dA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=df8q64KX; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-66461-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-66461-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7o008333; Thu, 15 Feb 2024 02:55:40 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 5/9] arm64: dts: ti: k3-j721e-sk: Model CSI2RX connector mux Date: Thu, 15 Feb 2024 14:25:14 +0530 Message-ID: <20240215085518.552692-6-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790954688228745784 X-GMAIL-MSGID: 1790954688228745784 J721E SK has the CSI2RX routed to a MIPI CSI connector and to 15-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. Also provide labels to the I2C mux bus instances so that a generic overlay can be used across multiple platforms. J721E SK schematics: https://www.ti.com/lit/zip/sprr438 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 6950b1ff124f..5dbc85bc5038 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -286,6 +286,15 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_csi_mux_sel_pins_default>; + }; }; &main_pmx0 { @@ -352,6 +361,12 @@ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; }; + main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ + >; + }; + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ @@ -858,14 +873,14 @@ i2c-mux@70 { reg = <0x70>; /* CSI0 I2C */ - i2c@0 { + cam0_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; /* CSI1 I2C */ - i2c@1 { + cam1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; From patchwork Thu Feb 15 08:55:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 201281 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp260301dyb; Thu, 15 Feb 2024 00:59:34 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCX1P6OXg/rj8nkzXWaralQK0tGO+a1QgMTp5CF9BFr5x3buMIjeL8iKpdeh/imNv8Jf2odvLhOdFJjo5l5Wb1JEzNtcaA== X-Google-Smtp-Source: AGHT+IGwIhISONLxev8Kb1P1WjCRWT9f71FfNGmdKLByo+cGbZ3NrvPSUdnsvAzuoJSfg7GE+4uk X-Received: by 2002:a05:6a21:2d8a:b0:1a0:6888:2c23 with SMTP id ty10-20020a056a212d8a00b001a068882c23mr1660457pzb.12.1707987574246; Thu, 15 Feb 2024 00:59:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707987574; cv=pass; d=google.com; s=arc-20160816; b=dr9/gmFx89hfjgteylWF0UosQwyuSV9B67V+HM+jD5j3Fzkc0mTYrLb6wZRUjhPHGi QQYReKbU2vxpkB5fiJT5LA/xvLS2qWrL9h5HefvAhTm+W1YHaN2XogbYPUmGPa7pCdx6 x6OPniCZr591bpSoyTNLNYeuE1VRYZussnNARyZG4wCQNQLpfbmM/HG31LaBVBp5BBSI GTkmYPtY56+LIUJvYk0C0X3KqtVP6iK4FGGwr8H38iRyajoCo+60HLkZG6/7Qdi+BDBJ m0Ke7WottKqg3rA3A6KB9ZTEEV8rOw7VYg0/zAWp52Mawrnu7Q4y2JG+Ta3aSmu/SbaU 0CoQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=hle8B4wOVmCnu+NYK66b75xWUwcEbuBSDmVLCNAJScI=; fh=Q0qfAugDSiRH+GkuTIKfokhNWAVNOIduw9aJ54bFjbE=; b=vUWrfhCUAqWZ+3CFk8l9NaBi0WrSxDWNqyaQxztx9h7W53uz85rsqwJRJZcVwrVlj+ /Yw2r6j1ArPV2jCf+fjWKHZ2M9l3Z6mg0YplljN01mMDqSf2Roi01RaGDLtSIlnHmVVs OV1IngAGVlncoNhKOUlMo0oYWaXcpkx/yquP7l+hLF6RASr2f3sLGcgranDPlqAcg06U e50YOlcCf2IHgG12U9GNQyT5KiNvqidBtPKPEGMynJ2WNEXANgFroDSPFN/avzacwN/3 nZOqYkPVjnYraf/0iTyn+hJDj8w5kV8hBM22l1HOA6ubcOOdImmaXZjmOibjFpqRoE9t f+4w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rlxAKeC8; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-66462-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-66462-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7p008333; Thu, 15 Feb 2024 02:55:44 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 6/9] arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes Date: Thu, 15 Feb 2024 14:25:15 +0530 Message-ID: <20240215085518.552692-7-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790954778169429054 X-GMAIL-MSGID: 1790954778169429054 J721E has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721E TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruil1 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V2->V3: Fix order of properties as per dts coding style. V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 122 ++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 062a6fca5a31..841752d20de1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -572,6 +572,128 @@ main_timerio_output: pinctrl@104280 { pinctrl-single,function-mask = <0x0000001f>; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x0 0x4500000 0x0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4504000 0x0 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x0 0x4510000 0x0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_udmap 0x4960>; + dma-names = "rx0"; + power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4514000 0x0 0x1000>; + clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, + <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4580000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4590000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7q008333; Thu, 15 Feb 2024 02:55:48 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 7/9] arm64: dts: ti: k3-j721s2-main: Add CSI2RX capture nodes Date: Thu, 15 Feb 2024 14:25:16 +0530 Message-ID: <20240215085518.552692-8-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790954719940903458 X-GMAIL-MSGID: 1790954719940903458 J721S2 has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721S2 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J721S2 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj28 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V2->V3: Fix order of properties as per dts coding style. V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 123 ++++++++++++++++++++- 1 file changed, 122 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index dcaa4da0d678..9063aa609993 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1122,7 +1122,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id = <225>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { @@ -1233,6 +1232,128 @@ usb0: usb@6000000 { }; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04500000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x1000>; + clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x1000>; + clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + serdes_wiz0: wiz@5060000 { compatible = "ti,j721s2-wiz-10g"; #address-cells = <1>; From patchwork Thu Feb 15 08:55:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 201279 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp260005dyb; Thu, 15 Feb 2024 00:58:46 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXooMo5VFP7UERP/FLJMBp9NVFbMUQU3D6mlOlUJebguYS6+t2DDhCHpEe9Mpuskww4yYs9CGUkLaXqh4UkWrkfN19NRg== X-Google-Smtp-Source: AGHT+IHDvOeC6v0jJvEArjs5MUNKw+JLT0aHhZ6lwlGqMwqfNJAprlgXQvm3rL4uDpZ+z5KMIOkl X-Received: by 2002:a17:906:1cc2:b0:a3d:534f:98bf with SMTP id i2-20020a1709061cc200b00a3d534f98bfmr855071ejh.75.1707987526392; Thu, 15 Feb 2024 00:58:46 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7r008333; Thu, 15 Feb 2024 02:55:53 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 8/9] arm64: dts: ti: k3-j784s4-main: Add CSI2RX capture nodes Date: Thu, 15 Feb 2024 14:25:17 +0530 Message-ID: <20240215085518.552692-9-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790954728541524500 X-GMAIL-MSGID: 1790954728541524500 J784S4 has three CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J784S4 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J784S4 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj52 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V2->V3: Fix order of properties as per dts coding style. V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 183 ++++++++++++++++++++- 1 file changed, 182 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 3cb964982792..42e4ca1d0b65 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -662,6 +662,188 @@ main_i2c6: i2c@2060000 { status = "disabled"; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04500000 0x00 0x00001000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x00001000>; + clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, + <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x00001000>; + clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, + <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@4520000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04520000 0x00 0x00001000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4980 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@4524000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04524000 0x00 0x00001000>; + clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, + <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@45a0000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x045a0000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x1000>, @@ -1224,7 +1406,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id = <281>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { From patchwork Thu Feb 15 08:55:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 201282 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:b825:b0:106:860b:bbdd with SMTP id da37csp260500dyb; Thu, 15 Feb 2024 01:00:04 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCV13vifFluf+OjXY+aTGrY7vwJtbZhnK3Q+n9WCzihnjYLOxjDkrE31MCeNKzMtcrieEy4HsRSUPMAyZmk9+7nJ2NkHAA== X-Google-Smtp-Source: AGHT+IFtNqLUjv9XFJNUjUhSHKRndHa75l94rPXL0HIo9Jn/sCkq+qVhHYDK4vHjOOmJOUOndzhi X-Received: by 2002:a17:902:e545:b0:1d9:8bb4:3fdf with SMTP id n5-20020a170902e54500b001d98bb43fdfmr1156158plf.10.1707987604633; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41F8tJ7s008333; Thu, 15 Feb 2024 02:55:57 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 9/9] arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219 Date: Thu, 15 Feb 2024 14:25:18 +0530 Message-ID: <20240215085518.552692-10-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215085518.552692-1-vaishnav.a@ti.com> References: <20240215085518.552692-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790954810418754082 X-GMAIL-MSGID: 1790954810418754082 RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM69, J721E SK, and AM68 SK through the 22-pin CSI-RX connector. Add a reference overlay for dual IMX219 RPI camera v2 modules which can be used across AM68 SK, AM69 SK, TDA4VM SK boards that have a 15/22-pin FFC connector. Also enable build testing and symbols for all the three platforms. Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V3->V4: * Add additional port information in overlays to fix DTC warning: Warning (graph_child_address): graph node has single child node, #address-cells/#size-cells are not necessary V1->V2: * Rename overlays to indicate first platform (j721e-sk) supported and dual camera. * Add missed build test, fix missing newline. arch/arm64/boot/dts/ti/Makefile | 13 ++ .../dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso | 165 ++++++++++++++++++ 2 files changed, 178 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 4a570dffb638..e019efd3ce94 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -69,6 +69,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb @@ -106,8 +107,14 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo +k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ @@ -122,7 +129,10 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62a7-sk-hdmi-audio.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ + k3-am68-sk-base-board-csi2-dual-imx219-dtbs \ + k3-am69-sk-csi2-dual-imx219-dtbs \ k3-j721e-evm-pcie0-ep.dtb \ + k3-j721e-sk-csi2-dual-imx219-dtbs \ k3-j721s2-evm-pcie1-ep.dtb # Enable support for device-tree overlays @@ -132,5 +142,8 @@ DTC_FLAGS_k3-am62-lp-sk += -@ DTC_FLAGS_k3-am62a7-sk += -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ +DTC_FLAGS_k3-am68-sk-base-board += -@ +DTC_FLAGS_k3-am69-sk += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ +DTC_FLAGS_k3-j721e-sk += -@ DTC_FLAGS_k3-j721s2-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso new file mode 100644 index 000000000000..47bb5480b5b0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 + * on J721E SK, AM68 SK or AM69-SK board. + * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&csi_mux { + idle-state = <1>; +}; + +/* CAM0 I2C */ +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_0: imx219-0@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +/* CAM1 I2C */ +&cam1_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_1: imx219-1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; +}; + +&dphy1 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +};