From patchwork Wed Feb 14 17:55:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Easwar Hariharan X-Patchwork-Id: 201084 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp1391537dyb; Wed, 14 Feb 2024 09:57:33 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUtvAml7mIvzjh2TqYNB4jMD3SQ9i+iYiO48mb41of9GrpLKWu5mLwl9Js9sCjRMpJkXpruiN9xvT+dzXtd1W8BVQiqPw== X-Google-Smtp-Source: AGHT+IFoVY0JAdmYj7azcVol8o+bLh0EvSlXuu8AyPV9sT4LEGc7qLdjnRooToHW7QAoXAnAHgSR X-Received: by 2002:a17:906:840c:b0:a3c:be90:a5fb with SMTP id n12-20020a170906840c00b00a3cbe90a5fbmr1861672ejx.31.1707933452852; Wed, 14 Feb 2024 09:57:32 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707933452; cv=pass; d=google.com; s=arc-20160816; b=dV2wdLIfDvTtR4zPDa72N0WDEPkXp0bVgrZx4/8WEhA47rthQcyRJtJy/aebCw3hoU UfEBIrrNWLV0jWtxKC7lmUZC0ffflj+mlRD63H70g6Gt1VhGYhz7wHRdQFDWIyAKb6XK dOeMp+9Qsb6cZutj2Pi+0G0PFRUP0Vkzk32J0HNBq08j1Ug+N3W8UEhVN9Vsp+2tie3J 66tDDKF3PC/bfFYcgRVW/p5WSMCnJDfDBEUiLelMQ780aTK24IPjINb0mGexu8hY5+5C XixOdw20WaOkxfteg4RYpyfAw/O46PM3ed1qXF9ScLXX74gGgOsfKbOgQIYfU3pEJJ/k l12w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:date:subject:cc:to :from:dkim-signature:dkim-filter; bh=r+rU2WMM4VJfoXEWQNhgxysCmsxnkWOjgrrXu2wK71A=; fh=18hfe/EWECPXLcx0wOYMA+4FscDVSZoSkLmqsi9fe/g=; b=z04nwbk6w22q7zCTV5+INFqr0J3dQZztWIeeDkeXzkybzkNp/04/bEyqWUN9bTkck/ P387k1276T7sk0lNYAmGLBCvWNWYYaSLAZXYQ6QUQ6frKOnYgjLsdjzHN5v/jJGpD4lS 794NkwgWEG10vPpktpFHLZNqy1pzNRuaIRkaDSOVzDdKJQONAW6TzYxrzKIrsBKwlIWE tzmtYiLnHamO340XxRiL3bS4wDeoRhQBxz67w/SO7ZSwpPnZiJOHzdhG9HbqFE8EB20i 0F7f2z6urnJJBGsUkQJuuqAYZmTOU3WBXgzvXJg451kPUTN7t17vHaJh32ZCjjLIsncX AZkw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linux.microsoft.com header.s=default header.b=CANiH6Gk; arc=pass (i=1 spf=pass spfdomain=linux.microsoft.com dkim=pass dkdomain=linux.microsoft.com dmarc=pass fromdomain=linux.microsoft.com); spf=pass (google.com: domain of linux-kernel+bounces-65732-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-65732-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.microsoft.com X-Forwarded-Encrypted: i=2; AJvYcCX1SuEnrjvtt55As3lPo6wSWuEAQqlfHGkwKmZv4BwILPDCl2rE3NFpZj/+5Uu+7M/yXVnSAxk3n2+v5/vwKifqKpj8Fg== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id le16-20020a170907171000b00a3d1d27cd7fsi1321291ejc.340.2024.02.14.09.57.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Feb 2024 09:57:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-65732-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@linux.microsoft.com header.s=default header.b=CANiH6Gk; arc=pass (i=1 spf=pass spfdomain=linux.microsoft.com dkim=pass dkdomain=linux.microsoft.com dmarc=pass fromdomain=linux.microsoft.com); spf=pass (google.com: domain of linux-kernel+bounces-65732-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-65732-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.microsoft.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 074D21F293AA for ; Wed, 14 Feb 2024 17:56:53 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C4C8D129A6D; Wed, 14 Feb 2024 17:55:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="CANiH6Gk" Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7EBEC128384; Wed, 14 Feb 2024 17:55:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707933357; cv=none; b=qfzVuwm8aSe7RKJn+2G9MkdQwH1ub+IqHIit+gXlPdVFdLXESZYfMq7moV7z9XnOaEdAMqBgN43hv+LFV2/7IgFKSBMj+RN7VQAOjbPlCt4lwTXzLz+dbmArHzsmqyRFOycC5QUjdpP8m4MuBA5qiDxefdLtC+QKoW1XQbWI1j0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707933357; c=relaxed/simple; bh=3qB79HFhmwRQp/g0OaJbQumLxLHsG6yTbWfyt0udki8=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=ewMIs5AR9QzqW06O+iFVYoWyRx6B0pKNY4Ljas2cjwEk7DSdQTNvKxm9lPfz9eTPuTYpy5laC2H4ESKmR5OkAvvmFX6zgULSm7tVS8vrzJbGRSLwVbNR4eatZfVOIkhl5fVxhZS6t/Cf22kd80yVGTQ3sXxiUVM1VrEpI1NT/kY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=CANiH6Gk; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Received: from rrs24-12-35.corp.microsoft.com (unknown [131.107.160.19]) by linux.microsoft.com (Postfix) with ESMTPSA id 03A7920B2000; Wed, 14 Feb 2024 09:55:55 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 03A7920B2000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1707933355; bh=r+rU2WMM4VJfoXEWQNhgxysCmsxnkWOjgrrXu2wK71A=; h=From:To:Cc:Subject:Date:From; b=CANiH6GkGIzkHCJvTmaYYdBbsgL+mrRs2lfI6hhhbU35UwoGFie29kiAWK/wPd8kn NBeGr6rQ2UuRKn2CUsYs5mwOCE1Uf5nw/ckCX9rBz7wW5i8GmnCuw16FHmrsmb9VNa 8rWPxip0zOgOfI9hR2Ss9o5Ib4rVfg3MiqYSS/es= From: Easwar Hariharan To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Rob Herring , Andre Przywara , Easwar Hariharan , Mark Rutland , Oliver Upton , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-kernel@vger.kernel.org (open list) Cc: stable@vger.kernel.org Subject: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Date: Wed, 14 Feb 2024 17:55:18 +0000 Message-Id: <20240214175522.2457857-1-eahariha@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790898028691860079 X-GMAIL-MSGID: 1790898028691860079 Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore suffers from all the same errata. CC: stable@vger.kernel.org # 5.15+ Signed-off-by: Easwar Hariharan Acked-by: Marc Zyngier --- changelog: v1->v2: * v1: https://lore.kernel.org/linux-arm-kernel/20240212232909.2276378-1-eahariha@linux.microsoft.com/T/#u * Consistently use MICROSOFT throughout --- Documentation/arch/arm64/silicon-errata.rst | 7 +++++++ arch/arm64/include/asm/cputype.h | 4 ++++ arch/arm64/kernel/cpu_errata.c | 3 +++ 3 files changed, 14 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index e8c2ce1f9df6..45a7f4932fe0 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -243,3 +243,10 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ASR | ASR8601 | #8601001 | N/A | +----------------+-----------------+-----------------+-----------------------------+ ++----------------+-----------------+-----------------+-----------------------------+ +| Microsoft | Azure Cobalt 100| #2139208 | ARM64_ERRATUM_2139208 | ++----------------+-----------------+-----------------+-----------------------------+ +| Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 | ++----------------+-----------------+-----------------+-----------------------------+ +| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 | ++----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 7c7493cb571f..52f076afeb96 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -61,6 +61,7 @@ #define ARM_CPU_IMP_HISI 0x48 #define ARM_CPU_IMP_APPLE 0x61 #define ARM_CPU_IMP_AMPERE 0xC0 +#define ARM_CPU_IMP_MICROSOFT 0x6D #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 @@ -135,6 +136,8 @@ #define AMPERE_CPU_PART_AMPERE1 0xAC3 +#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */ + #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) @@ -193,6 +196,7 @@ #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX) #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100) /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 967c7c7a4e7d..76b8dd37092a 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = { static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { #ifdef CONFIG_ARM64_ERRATUM_2139208 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), #endif #ifdef CONFIG_ARM64_ERRATUM_2119858 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), @@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { static const struct midr_range tsb_flush_fail_cpus[] = { #ifdef CONFIG_ARM64_ERRATUM_2067961 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), #endif #ifdef CONFIG_ARM64_ERRATUM_2054223 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), @@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = { static struct midr_range trbe_write_out_of_range_cpus[] = { #ifdef CONFIG_ARM64_ERRATUM_2253138 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), #endif #ifdef CONFIG_ARM64_ERRATUM_2224489 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),