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Wed, 14 Feb 2024 06:51:54 -0600 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41ECprfd056051; Wed, 14 Feb 2024 06:51:53 -0600 From: Devarsh Thakkar To: , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH v2 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region Date: Wed, 14 Feb 2024 18:21:50 +0530 Message-ID: <20240214125151.1965137-2-devarsht@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240214125151.1965137-1-devarsht@ti.com> References: <20240214125151.1965137-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790878936361584395 X-GMAIL-MSGID: 1790878936361584395 TI keystone display subsystem present in AM65 and other SoCs such as AM62 support two separate register spaces namely "common" and "common1" which can be used by two separate hosts to program the display controller as described in respective Technical Reference Manuals [1]. The common1 register space has similar set of configuration registers as supported in common register space except the global configuration registers which are exclusive to common region. This adds binding for "common1" register region too as supported by the hardware. [1]: AM62x TRM: https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) AM65x TRM: https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) AM62A TRM: https://www.ti.com/lit/pdf/spruj16 (Section 14.9.9.1 DSS Registers) Signed-off-by: Devarsh Thakkar Acked-by: Conor Dooley --- V2: Add Acked-by tag --- .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index b6767ef0d24d..55e3e490d0e6 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -37,6 +37,7 @@ properties: - description: OVR2 overlay manager for vp2 - description: VP1 video port 1 - description: VP2 video port 2 + - description: common1 DSS register area reg-names: items: @@ -47,6 +48,7 @@ properties: - const: ovr2 - const: vp1 - const: vp2 + - const: common1 clocks: items: @@ -147,9 +149,10 @@ examples: <0x04a07000 0x1000>, /* ovr1 */ <0x04a08000 0x1000>, /* ovr2 */ <0x04a0a000 0x1000>, /* vp1 */ - <0x04a0b000 0x1000>; /* vp2 */ + <0x04a0b000 0x1000>, /* vp2 */ + <0x04a01000 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 67 1>, From patchwork Wed Feb 14 12:51:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devarsh Thakkar X-Patchwork-Id: 200949 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp1188645dyb; Wed, 14 Feb 2024 04:54:27 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWKBAs9tPFgnM2lAcsordCkUGLSb1+5XDJTEFy+2Xa0ddWSo02uYSz4PAEDuOHEttFLusF/UD4diUrY0ofWrF2zdF7Uig== X-Google-Smtp-Source: AGHT+IF7xUuQv2gZSDOStPikijS1SDH5SUdqnFUFoI7IL8cmkOhXWn4Q3dez35MQPPsnYqorvh8u X-Received: by 2002:a0c:f0cb:0:b0:68e:f8aa:ee93 with SMTP id d11-20020a0cf0cb000000b0068ef8aaee93mr2550754qvl.50.1707915267318; Wed, 14 Feb 2024 04:54:27 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707915266; cv=pass; d=google.com; s=arc-20160816; b=p09C1mB9NDhEKVpQobgM9qQ9OnNOVyOw4ac8UD7WmhFFlacYOfuftRbKSq0U13zPam rLEBHt+rXEQHhRaxTq1aMp7OxtLjYwIwnC2kpfmphdaUvBt2kBD/4fV/9e44HZ2AozEN VBjSWTmmrR+qu+25jPMIW5r3V5yo6y6oMseXfwyKc7U2Z+49tRZLJsdOlnNYBlqAxzTF 1ymAk9o5x4qaHvAu36XOgf6h9+dOdFPaxG/qZAXgex2iXvSv23H8gyrdgxOff4Hl+a5X 6PQIvhCCnrX/4LHQz5jDjD3EIvql0olQtgihPfJdXqyZrgUdcOYh4eTZI3Udfpxa+apQ /ayg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=kuoeBUR4o4+sd1G1Nxv5Un7Uktabr5/pM9BWB3fx2HY=; fh=ejwOjWQE/Ddi0eiqQIwGnEqM1baot6+b4895CxlEFMc=; b=NeovLJ1N8hcJinjXwP7fPejIc+4ApJgcdwLl/f5zsfLaKndUGtihWmpe2BTOp0bwn5 iXJHefQugCytBjD+aa1Xms3dyVedbWAh3DFwzSEPsXcPAbOpA/wWjjz1dtQRch/0WHrQ nHV9SL1yyKpO2U2QiITxj5htwRtcWUjughIMzX38CoYfO6pJME8F4TiHmouDsRJ3WSua aMjUZHGZc+Xg62Fz5ppw6xJfnxmH8MQeLpcHTD0Pv6l+bvbT+xZmOAS0Kc30jbkKKw7Q v3fyDmZtaVYqKqfThOpDpx5lTXuwwXATwnXfli9L0m8f42AzVF6AZblvHoBLGI2Qm4to Pilg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CwertjnW; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-65224-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-65224-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCXE/wSO6VcSw8tVguBmRrH8YWGMjFwfjodAml2eNuyHDdoK0sEkVSprb+MBqb5BVzgS2jY7VZzc4J0s6Ljq35Xceot+fQ== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Wed, 14 Feb 2024 06:51:55 -0600 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41ECpsTq092363; Wed, 14 Feb 2024 06:51:55 -0600 From: Devarsh Thakkar To: , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH v2 2/2] arm64: dts: ti: Add common1 register space for AM62x, AM62A & AM65x SoCs Date: Wed, 14 Feb 2024 18:21:51 +0530 Message-ID: <20240214125151.1965137-3-devarsht@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240214125151.1965137-1-devarsht@ti.com> References: <20240214125151.1965137-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790878958882630091 X-GMAIL-MSGID: 1790878958882630091 This adds common1 register space for AM62x, AM62A and AM65x SoC's which are using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml Signed-off-by: Devarsh Thakkar --- V2: Add common1 region for AM62A SoC too --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index fe0cc4a9a501..8cee4d94cdd3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -779,9 +779,10 @@ dss: dss@30200000 { <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&dss_vp1_clk>, diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 972971159a62..f475daea548e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -994,9 +994,10 @@ dss: dss@30200000 { <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&k3_clks 186 0>, diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 07010d31350e..ff857117d719 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -991,9 +991,10 @@ dss: dss@4a00000 { <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;