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Cc: Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Reviewed-by: Andrew Jones Signed-off-by: Samuel Holland --- (no changes since v1) arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..2468c55933cd 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -424,6 +424,7 @@ # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE # define CSR_TVEC CSR_MTVEC +# define CSR_ENVCFG CSR_MENVCFG # define CSR_SCRATCH CSR_MSCRATCH # define CSR_EPC CSR_MEPC # define CSR_CAUSE CSR_MCAUSE @@ -448,6 +449,7 @@ # define CSR_STATUS CSR_SSTATUS # define CSR_IE CSR_SIE # define CSR_TVEC CSR_STVEC +# define CSR_ENVCFG CSR_SENVCFG # define CSR_SCRATCH CSR_SSCRATCH # define CSR_EPC CSR_SEPC # define CSR_CAUSE CSR_SCAUSE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..c5b13f7dd482 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -950,7 +950,7 @@ arch_initcall(check_unaligned_access_all_cpus); void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) - csr_set(CSR_SENVCFG, ENVCFG_CBZE); + csr_set(CSR_ENVCFG, ENVCFG_CBZE); } #ifdef CONFIG_RISCV_ALTERNATIVE From patchwork Wed Feb 14 09:01:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 200867 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp1080692dyb; Wed, 14 Feb 2024 01:02:55 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVUtmrTYLGJOMsn4b55idyrNgIWSgjpJpEUncWqEwir2LfWk4HWa3mfB13VmJ7C9A0KWy6MDDKKu/wpz3kavHOkVH/Jwg== X-Google-Smtp-Source: AGHT+IFvT9rMJr+pWrjzPiCUOAzaHzEYabc8jMffm5lpodPduyDSSt1R7kmgucZ545yhHRFoYLlf X-Received: by 2002:a05:620a:458a:b0:785:cde8:fe0a with SMTP id bp10-20020a05620a458a00b00785cde8fe0amr2381797qkb.27.1707901375662; Wed, 14 Feb 2024 01:02:55 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707901375; cv=pass; d=google.com; s=arc-20160816; b=Ac26SWhywCsOwoCaejHezX1E70lsoW6vI28gd4putYbwpF83yzpdwbvvU9d8hC+KnH y01azJr7d5oPbLbDbAad4Xwqve3Q7X9CMI3mgrgweZhMDjXdcfbT1eg+EEBx1wPykbb/ lRf4xP9fD9R1usBbz5CgA5cFSWLxMRy4WxLReido7lTjrZeO/7HSDBVZ35HvSOCF/w0V SqgO6J3ibBZRbbURLRsyh0auL2UoVvBMlzENdH/N9/j0TfJns3QRnMhL182quq3KZr3P jkjEBYeVSKs4IPK/m6ETAw8TGr14k6471cP45706kKHnbuhaRcUNE28QBjuDglS7iG/P HcsQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=PPRsJ6g4sGjHYOROeqaGh/pr9ekDnpVi90clFxCUkAg=; fh=B9PI7nBLJ0Fo3sAb7asNP8dYthWr/mKzIxynVbF9o1o=; b=zpdqtXm9Ifl9c4iowsQnC/R9p4rE5etB+MQM1eFUArXXk3xGKYj+5FgGpnVm8i1RK/ q2HdL3KuePIsdLe53FsxA28Ctbz4VoZaTl1MlLk80Bd+Cm3LCf6nemW4tq7bnb/LKj75 WO01rW88meajk5bAFKiHajIyu7XfTVfmtj0s8QTAViksiFBD3339a+7pM3pJ7SZBLN1Y GoESjiyWBxG7hSE8XoTtq7PFlR3Rgq1G2Imp4ZKh/VAYkg5EOV/qiEkeBkA9HEMLqRHQ hJMIBCeNYKt7riLv41MGmjQ+wrXm0aIMcFjdLhvhmpFqoQTASekkdgI0csmWCESWjgV9 UGqw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=CISgWuk1; arc=pass (i=1 spf=pass spfdomain=sifive.com dkim=pass dkdomain=sifive.com dmarc=pass fromdomain=sifive.com); spf=pass (google.com: domain of linux-kernel+bounces-64906-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-64906-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=sifive.com X-Forwarded-Encrypted: i=2; AJvYcCX0lrMxIgZe8SK0USolcTY/joMAGtR/dnX865twaDRJOqDqHxNjsICDBly+vmvT3+KtpZq4GbWMYEEfGty86LHI5AJW/g== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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AJvYcCUTUMYj6Mbob234o6DVkvzgdfcee6xQnFWptSYffagJMi1onPluc5MIgjQ6BKEnHl1P1kMVcoth6n4tU1YljZiWRn7STpH6ZhSvKCx+ X-Gm-Message-State: AOJu0Ywk2leSXEYkwiQmcEt0ALc52iIdfCjrTWN5uCCVna7mn1kloqrB PrNXL53cJeVcbXErxpAMaggxi+MEwXyIZ87e1pZwyXn2DNioDnY7RObYIm7x72I= X-Received: by 2002:a05:6a20:d487:b0:19e:4c37:8737 with SMTP id im7-20020a056a20d48700b0019e4c378737mr2014592pzb.5.1707901330438; Wed, 14 Feb 2024 01:02:10 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCVBa/niUfhaptGFm9lpsC7zFdtIR2IEOBXSB0tdcyp6YZbUOgFtfbI/clENDxQCc8TCx8cnV0UJM0uPePynqx9jmQ7hY4b5ASPHIgiC4ZfxONgs2/Bri+S7wIUid9Bd0gcGYFrdshm5ssWW0rX7DOV8ZmKL6m+ulTzguKOnSdLt5I/uYehmsE75yEXVwh5SFONe5K6zDtg+cMtGVcnmC/zs52MkLQukmDPBDfZPnewiiQR2bVV8CVafM5Yknt5+zeqr1cvS7wKO Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id m25-20020a638c19000000b005d7994a08dcsm2476681pgd.36.2024.02.14.01.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Feb 2024 01:02:10 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt Cc: Andrew Jones , linux-kernel@vger.kernel.org, Conor Dooley , linux-riscv@lists.infradead.org, Stefan O'Rear , Samuel Holland , stable@vger.kernel.org Subject: [PATCH -fixes v3 2/2] riscv: Save/restore envcfg CSR during CPU suspend Date: Wed, 14 Feb 2024 01:01:57 -0800 Message-ID: <20240214090206.195754-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240214090206.195754-1-samuel.holland@sifive.com> References: <20240214090206.195754-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790864393075088608 X-GMAIL-MSGID: 1790864393075088608 The value of the [ms]envcfg CSR is lost when entering a nonretentive idle state, so the CSR must be rewritten when resuming the CPU. The [ms]envcfg CSR was added in version 1.12 of the privileged ISA, and is used by extensions other than Zicboz. However, the kernel currenly has no way to determine the privileged ISA version. Since Zicboz is the only in-kernel user of this CSR so far, use it as a proxy for determining if the CSR is implemented. Cc: # v6.7+ Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Signed-off-by: Samuel Holland Reviewed-by: Andrew Jones --- Changes in v3: - Check for Zicboz instead of the privileged ISA version Changes in v2: - Check for privileged ISA v1.12 instead of the specific CSR - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s arch/riscv/include/asm/suspend.h | 1 + arch/riscv/kernel/suspend.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h index 02f87867389a..491296a335d0 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -14,6 +14,7 @@ struct suspend_context { struct pt_regs regs; /* Saved and restored by high-level functions */ unsigned long scratch; + unsigned long envcfg; unsigned long tvec; unsigned long ie; #ifdef CONFIG_MMU diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 239509367e42..28166006688e 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -15,6 +15,8 @@ void suspend_save_csrs(struct suspend_context *context) { context->scratch = csr_read(CSR_SCRATCH); + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) + context->envcfg = csr_read(CSR_ENVCFG); context->tvec = csr_read(CSR_TVEC); context->ie = csr_read(CSR_IE); @@ -36,6 +38,8 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { csr_write(CSR_SCRATCH, context->scratch); + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) + csr_write(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); csr_write(CSR_IE, context->ie);