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AJvYcCWJB6s0uOWf/gL4yJ56gcBGsj937G41IEiLhVORwJ08yb2+9MSbW+R2yJ3Y0IBSTo4F7PbSyjxrafAEcRUQAK7Jn+lqXaYfaw+DW9ym X-Gm-Message-State: AOJu0Ywrtu06hc3SiTfjSGmGtJH3xxOisP1Sb0VqChUdlNs8AAbhqKgG WeErNsb5Yw1oBF+qtMDxekerIwi0zhBxJf01cC6tBBVLd4/IdG/3BLQT5yr1yBxsddq8YloJt9c 0ciyYuw4NoKvT/IPj4g== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a25:d842:0:b0:dc6:e8a7:fdba with SMTP id p63-20020a25d842000000b00dc6e8a7fdbamr161224ybg.4.1707863957363; Tue, 13 Feb 2024 14:39:17 -0800 (PST) Date: Tue, 13 Feb 2024 22:39:09 +0000 In-Reply-To: <20240213223810.2595804-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213223810.2595804-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213223909.2596587-1-ericchancf@google.com> Subject: [PATCH v5 1/4] riscv/barrier: Define __{mb,rmb,wmb} From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790825174944164852 X-GMAIL-MSGID: 1790825174944164852 Introduce __{mb,rmb,wmb}, and rely on the generic definitions for {mb,rmb,wmb}. Although KCSAN is not yet support, it can be made more consistent with generic instrumentation. Signed-off-by: Eric Chan --- arch/riscv/include/asm/barrier.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 110752594228..4c49a8ff2c68 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -20,9 +20,9 @@ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ -#define mb() RISCV_FENCE(iorw,iorw) -#define rmb() RISCV_FENCE(ir,ir) -#define wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw,iorw) +#define __rmb() RISCV_FENCE(ir,ir) +#define __wmb() RISCV_FENCE(ow,ow) /* These barriers do not need to enforce ordering on devices, just memory. */ #define __smp_mb() RISCV_FENCE(rw,rw) From patchwork Tue Feb 13 22:39:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 200719 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp851753dyb; Tue, 13 Feb 2024 14:51:01 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU4ZNPhrVM0VUlNj/7nxOfCUK+GkE9F375I7+y7gSJosvfWQZ8UPYK+JCOExPLr8OsBgKZN0LaQwVpesp8hJGMm5S421g== X-Google-Smtp-Source: AGHT+IG+sGk6Qfa0QrWvQadCDUo4/AjxqYTkQkVwIh//zc+5bENQs/jvb4WJABd0tlvIMOP8r8gN X-Received: by 2002:a05:6a00:2b58:b0:6e0:e235:e2c1 with SMTP id du24-20020a056a002b5800b006e0e235e2c1mr606856pfb.9.1707864661327; Tue, 13 Feb 2024 14:51:01 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707864661; cv=pass; d=google.com; s=arc-20160816; b=Pwy3GN+mQhEkQK9E/0se30ooKEVkHIpVPOfNtw1nnYVFlLJpWIsCbFnzmNy6Ogxh2f wLsAgweZ6XNmqEpYeijaYufR75t8XZNQ/ZywULLBCkgA8OGeOMEYuNF9udkHFtWZm3tY PIA/ZSjM0lQ6BTQFVpBkrgFnW97FybSI5ej9P24tAnkQLpmWc2s1lt/WFDR+DrFjCBI2 LyJH7k6U6FKsHiKqFUuJQhiJ5vxFa5Lmix1DT5z+RosoYk5hq6ho1lZYpts+oqaa0EZ4 SX+tn32FM/ZmIgX2FxmKAnVpN4SU6aoqabjeTzPn3wocl0afBZ5WD/bfDt+DqARopb/Y OBGg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:from:subject:message-id:references:mime-version :list-unsubscribe:list-subscribe:list-id:precedence:in-reply-to:date :dkim-signature; bh=2A5s0YU98xz4fK0cK8V3de3MUudesnEU1GM23Fa1guU=; fh=BR5mQJwMcPL+VmTv5SGkOCa1LJCKWr+EpqLUkSFpRDc=; b=fY5mpO8nEg31USmErYJrSAwhOAaCi9p3AxADq6Y9o2RHWrrMD+qoEWHEs4Zie1exXr hmVevOidl2pZSDH27CU52L7T8FUPY0CaLlpFLpFwwKTKcxy6Pp1K1vnEvbny0er1EvvK VZ9l9nKGbO+B7dnrjqej/kEVtfnAXCUwJn1+zlU1J2DxBou7f+nZj12iMJW0hobG60sw BvFAAk2TQ5XnTOTOmWC5MW+kfRPfFCZiNH19JRk4wCEMKabodxNIQlJWD4CeQ9/8vG+R gyPeOsG+cYpZqjVlSrzrxUoacBoMtazTkm1kkT8+3f8K6CSO6A1jp8fL5PR7mVaOgnE8 AQSQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=rUAdsbKX; arc=pass (i=1 spf=pass spfdomain=flex--ericchancf.bounces.google.com dkim=pass dkdomain=google.com dmarc=pass fromdomain=google.com); spf=pass (google.com: domain of linux-kernel+bounces-64471-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-64471-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com X-Forwarded-Encrypted: i=2; AJvYcCV54ox/V8xXNxvBGoycmLjznsG/hA71OSy8q4SsIZ23j2/EV8kbKPpwDAipmM+c49YYpvjr51T2JrND1p8CZpumJ25IKw== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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AJvYcCU3YBYH/Yk63hF5gSGD201vn/XiNCJijE1OCILxqFRzjVwmzG9+TKdZAeI8Qu/lE9T3rVXxISj/MKVC6UaAN9hQa83mLdsjhc5tAi05 X-Gm-Message-State: AOJu0Yz64WNy2DSF0WcxHV+HdOuVff6rCStynqrBoMMdcP9B0QBX09lz wk6VB4T/xvLL58jvONspHpvp6twlDiBN3B0GUkTywF/nxNFGPWGIn2POU0CRlTexE0XoM1iaMuX IdGLMJuV+GlE5WyjmuA== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:1027:b0:dc6:dd76:34cc with SMTP id x7-20020a056902102700b00dc6dd7634ccmr45468ybt.1.1707863969224; Tue, 13 Feb 2024 14:39:29 -0800 (PST) Date: Tue, 13 Feb 2024 22:39:23 +0000 In-Reply-To: <20240213223810.2595804-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213223810.2595804-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213223923.2597036-1-ericchancf@google.com> Subject: [PATCH v5 2/4] riscv/barrier: Define RISCV_FULL_BARRIER From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790825895216074110 X-GMAIL-MSGID: 1790825895216074110 Introduce RISCV_FULL_BARRIER and use in arch_atomic* function. like RISCV_ACQUIRE_BARRIER and RISCV_RELEASE_BARRIER, the fence instruction can be eliminated When SMP is not enabled. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 16 ++++++++-------- arch/riscv/include/asm/cmpxchg.h | 4 ++-- arch/riscv/include/asm/fence.h | 2 ++ 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index f5dfef6c2153..31e6e2e7cc18 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -207,7 +207,7 @@ static __always_inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int " add %[rc], %[p], %[a]\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -228,7 +228,7 @@ static __always_inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, " add %[rc], %[p], %[a]\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -248,7 +248,7 @@ static __always_inline bool arch_atomic_inc_unless_negative(atomic_t *v) " addi %[rc], %[p], 1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -268,7 +268,7 @@ static __always_inline bool arch_atomic_dec_unless_positive(atomic_t *v) " addi %[rc], %[p], -1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -288,7 +288,7 @@ static __always_inline int arch_atomic_dec_if_positive(atomic_t *v) " bltz %[rc], 1f\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -310,7 +310,7 @@ static __always_inline bool arch_atomic64_inc_unless_negative(atomic64_t *v) " addi %[rc], %[p], 1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -331,7 +331,7 @@ static __always_inline bool arch_atomic64_dec_unless_positive(atomic64_t *v) " addi %[rc], %[p], -1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -352,7 +352,7 @@ static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) " bltz %[rc], 1f\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 2f4726d3cfcc..a608e4d1a0a4 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -313,7 +313,7 @@ " bne %0, %z3, 1f\n" \ " sc.w.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" ((long)__old), "rJ" (__new) \ @@ -325,7 +325,7 @@ " bne %0, %z3, 1f\n" \ " sc.d.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" (__old), "rJ" (__new) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 2b443a3a487f..6c26c44dfcd6 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -4,9 +4,11 @@ #ifdef CONFIG_SMP #define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" #define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#define RISCV_FULL_BARRIER "\tfence rw, rw\n" #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER +#define RISCV_FULL_BARRIER #endif #endif /* _ASM_RISCV_FENCE_H */ From patchwork Tue Feb 13 22:39:41 2024 Content-Type: text/plain; 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AJvYcCWrPLtwdEHB7KJAwodCeUpbwlClGCMoTtwPF3RdnQRqzksrSQS2VUtbBmulCIYCTW/WBp6tq+13REfJkzMN2ZAQwXtYxywMsJNJC/I1 X-Gm-Message-State: AOJu0YwYjnZq91KZpkrlPxEl73MsCNNrCzNzL36mz/wr+NjQBxGfKPvK pCIHIN/eLilRDfYmcnOn/hp+i294cYZHMU1/gSi4fw66T8lAd8C6+vAwLQ5iLS7jnwBN2exvWNx /tMpUk8QLFQi8BQNlGA== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a0d:e884:0:b0:5ff:a885:65b with SMTP id r126-20020a0de884000000b005ffa885065bmr136409ywe.10.1707863992743; Tue, 13 Feb 2024 14:39:52 -0800 (PST) Date: Tue, 13 Feb 2024 22:39:41 +0000 In-Reply-To: <20240213223810.2595804-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213223810.2595804-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213223941.2597526-1-ericchancf@google.com> Subject: [PATCH v5 3/4] riscv/barrier: Consolidate fence definitions From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790825286174586721 X-GMAIL-MSGID: 1790825286174586721 Disparate fence implementations are consolidated into fence.h. Also introduce RISCV_FENCE_ASM to make fence macro more reusable. Signed-off-by: Eric Chan --- v4 -> v5: keep __atomic_acquire_fence and __atomic_release_fence omit-the-fence-on-uniprocessor optimization, and fix the typo of RISCV_RELEASE_BARRIER when spliting the patch in v3. arch/riscv/include/asm/atomic.h | 1 - arch/riscv/include/asm/barrier.h | 3 +-- arch/riscv/include/asm/cmpxchg.h | 1 - arch/riscv/include/asm/fence.h | 10 +++++++--- arch/riscv/include/asm/io.h | 8 ++++---- arch/riscv/include/asm/mmio.h | 5 +++-- arch/riscv/include/asm/mmiowb.h | 2 +- 7 files changed, 16 insertions(+), 14 deletions(-) -- 2.43.0.687.g38aa6559b0-goog diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 31e6e2e7cc18..0e0522e588ca 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -17,7 +17,6 @@ #endif #include -#include #define __atomic_acquire_fence() \ __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 4c49a8ff2c68..4f4743d7440d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -11,13 +11,12 @@ #define _ASM_RISCV_BARRIER_H #ifndef __ASSEMBLY__ +#include #define nop() __asm__ __volatile__ ("nop") #define __nops(n) ".rept " #n "\nnop\n.endr\n" #define nops(n) __asm__ __volatile__ (__nops(n)) -#define RISCV_FENCE(p, s) \ - __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ #define __mb() RISCV_FENCE(iorw,iorw) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index a608e4d1a0a4..2fee65cc8443 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -8,7 +8,6 @@ #include -#include #include #define __xchg_relaxed(ptr, new, size) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 6c26c44dfcd6..6bcd80325dfc 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -1,10 +1,14 @@ #ifndef _ASM_RISCV_FENCE_H #define _ASM_RISCV_FENCE_H +#define RISCV_FENCE_ASM(p, s) "\tfence " #p "," #s "\n" +#define RISCV_FENCE(p, s) \ + ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) + #ifdef CONFIG_SMP -#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" -#define RISCV_RELEASE_BARRIER "\tfence rw, w\n" -#define RISCV_FULL_BARRIER "\tfence rw, rw\n" +#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r, rw) +#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw, w) +#define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw, rw) #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 42497d487a17..1c5c641075d2 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -47,10 +47,10 @@ * sufficient to ensure this works sanely on controllers that support I/O * writes. */ -#define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory"); -#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory"); -#define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); -#define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); +#define __io_pbr() RISCV_FENCE(io, i) +#define __io_par(v) RISCV_FENCE(i, ior) +#define __io_pbw() RISCV_FENCE(iow, o) +#define __io_paw() RISCV_FENCE(o, io) /* * Accesses from a single hart to a single I/O address must be ordered. This diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index 4c58ee7f95ec..06cadfd7a237 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -12,6 +12,7 @@ #define _ASM_RISCV_MMIO_H #include +#include #include /* Generic IO read/write. These perform native-endian accesses. */ @@ -131,8 +132,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); }) -#define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) +#define __io_ar(v) RISCV_FENCE(i, ir) +#define __io_bw() RISCV_FENCE(w, o) #define __io_aw() mmiowb_set_pending() #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiowb.h index 0b2333e71fdc..52ce4a399d9b 100644 --- a/arch/riscv/include/asm/mmiowb.h +++ b/arch/riscv/include/asm/mmiowb.h @@ -7,7 +7,7 @@ * "o,w" is sufficient to ensure that all writes to the device have completed * before the write to the spinlock is allowed to commit. */ -#define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory"); +#define mmiowb() RISCV_FENCE(o, w) #include #include From patchwork Tue Feb 13 22:40:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 200724 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp859726dyb; Tue, 13 Feb 2024 15:08:07 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUk+xZ/Mr8HryYsGU2uFvGbmCH9rqVZUFuVfSJwXk/rxEyOPr9DfY9Y9QB9+nIvQmxe/mH+Q8CjOFeSNvneOH34gbnYMw== X-Google-Smtp-Source: AGHT+IFSdrqUGuP6VxazZZgZfFPd+XM5Ps9++N+eT0K4t4o/XLKwjkrgrpIYq42BeSqe/2DoUIl0 X-Received: by 2002:a17:902:f68d:b0:1da:1ea9:9a41 with SMTP id l13-20020a170902f68d00b001da1ea99a41mr417594plg.12.1707865687656; Tue, 13 Feb 2024 15:08:07 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707865687; cv=pass; d=google.com; s=arc-20160816; b=J9U3BhxNnBWoh/cbgH+O5KeYK7IODX1auWasMmwXyo38lhl65/bNHJfB3JrNfc/dtP pa0Nh5maLQsTRqFrlvF8DO7jZOG0GrIWKtsnkCrflDvGAfLKFYrdPlhmLCUaGgd4PgfX g1vTyKctlxEzUXUSP4xl25v/QxUu+fzEeYRUtQNPWNOSCE+8i4InZobwxOsYJ6qY9HDP Y2YBkOw+2ZB2lufwPLPouJUFm9iV1V2WWHOHzeKy/slqx66uZAeGgTyB6PFL4c30sv0U kZyYxgoMGU1oGi0aAplvJZvur/ySLpl8b1/2EjByt0X5pO0xjXCKQpjqYHH6Lwtqf/MH D7Rg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:from:subject:message-id:references:mime-version :list-unsubscribe:list-subscribe:list-id:precedence:in-reply-to:date :dkim-signature; bh=RC2T9SgmWwA0L5LQ8BYxxpjFIKV4b3AtrMRzB+GqR24=; fh=VO/gkBHTStF7ct9y06r0dVjj0WZIMJS2jTlJwpNx/mA=; b=QmVSMA+4Yv10RDfckJZhYC7ghxXtk2rSZHwYZD9leK+5vE+X3d2pCrw1pvn7HxKLi6 uhFm4jiEkFkHb9fg8+mjzxN9rGWReI7O+3MoiVNAMdIAKTEdaGMInok9sBvJ1eSTx3s8 HstcG2ilcD+EKBMmxJuqwPxHENqUrQJPrvczdFnxbsHLC+U3VbBDhQuqJ+UAkOXj2ENV DFKw5tElNpkH2//CNUcbGwobEWe2N3Y/dBB2CCkqDqOpbvcCndVQUnydArkFTImUYk+k JmxGx8qAq4yWpmTYApzXoLJTezsWPrvREKD51efloqP0SaGDQwdJmXqaK24xUWN0mdPh d0eQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=s3IJmPjw; arc=pass (i=1 spf=pass spfdomain=flex--ericchancf.bounces.google.com dkim=pass dkdomain=google.com dmarc=pass fromdomain=google.com); spf=pass (google.com: domain of linux-kernel+bounces-64474-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-64474-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com X-Forwarded-Encrypted: i=2; AJvYcCU2mEraZlVPj/UvfvGIz0r66H7SHebmipwoHeJ9ikXlVh9qCSZVm3vsgg1ygxVnDFcjCq/yjg9QXwilJ7yo20gz/fM3hw== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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AJvYcCUuElhavILzSBIF/vnFqXDyARcouCxYWfNmbHsvZgNWcxHmDIKOn+PQaZBMv+BcKx07Orsd0DDrWhBTge4/1xuEsF6qdmkybEfi+1ju X-Gm-Message-State: AOJu0YzFYx9XxgtfoJYb5RKfP7XkAucaTY5ORyTS7GAiZFgHWGHOxyDV LvC/8g7riTVeJvDrIRPkzEzKpKOBAGc0nU8TXJDeRfRI8H0Lu4dmY7tlXuit+OR1yYbHPlbAzu9 mRamWHX6uDXUXGu/7IA== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:114d:b0:dc6:d2c8:6e50 with SMTP id p13-20020a056902114d00b00dc6d2c86e50mr105619ybu.7.1707864006063; Tue, 13 Feb 2024 14:40:06 -0800 (PST) Date: Tue, 13 Feb 2024 22:40:00 +0000 In-Reply-To: <20240213223810.2595804-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213223810.2595804-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213224000.2597959-1-ericchancf@google.com> Subject: [PATCH v5 4/4] riscv/barrier: Resolve checkpatch.pl error From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790826971661536612 X-GMAIL-MSGID: 1790826971661536612 The past form of RISCV_FENCE would cause checkpatch.pl to issue error messages, the example is as follows: ERROR: space required after that ',' (ctx:VxV) +#define __atomic_acquire_fence() RISCV_FENCE(r,rw) ^ fix the remaining of RISCV_FENCE. Signed-off-by: Eric Chan --- arch/riscv/include/asm/barrier.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 4f4743d7440d..880b56d8480d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -19,19 +19,19 @@ /* These barriers need to enforce ordering on both devices or memory. */ -#define __mb() RISCV_FENCE(iorw,iorw) -#define __rmb() RISCV_FENCE(ir,ir) -#define __wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw, iorw) +#define __rmb() RISCV_FENCE(ir, ir) +#define __wmb() RISCV_FENCE(ow, ow) /* These barriers do not need to enforce ordering on devices, just memory. */ -#define __smp_mb() RISCV_FENCE(rw,rw) -#define __smp_rmb() RISCV_FENCE(r,r) -#define __smp_wmb() RISCV_FENCE(w,w) +#define __smp_mb() RISCV_FENCE(rw, rw) +#define __smp_rmb() RISCV_FENCE(r, r) +#define __smp_wmb() RISCV_FENCE(w, w) #define __smp_store_release(p, v) \ do { \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(rw,w); \ + RISCV_FENCE(rw, w); \ WRITE_ONCE(*p, v); \ } while (0) @@ -39,7 +39,7 @@ do { \ ({ \ typeof(*p) ___p1 = READ_ONCE(*p); \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(r,rw); \ + RISCV_FENCE(r, rw); \ ___p1; \ }) @@ -68,7 +68,7 @@ do { \ * instances the scheduler pairs this with an mb(), so nothing is necessary on * the new hart. */ -#define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw) +#define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw) #include