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AJvYcCV651hGpPeTVcv9W3WurymzRLY03ESpVNKhE5M4Wp0z/s3utp5agUIznykJxIjjnEv4Z18lLmA/W0RcR0TJpIlln40wxg0RUxeW4ka0 X-Gm-Message-State: AOJu0YwlFChgSOWzUSyGbPeUof8sy3Cdkht33Z4UQ8CSmHk6IjGEC/TA i+eTRAd8Wb6dW4k3okpHa2Y/ogdzWPNJfa69zZs8xbNv7rN1ZA+zt690/7Cjl+IGiJ8LkaaIaO2 SmY8vPbi2BeSuTBZySA== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a0d:d989:0:b0:607:8b76:4744 with SMTP id b131-20020a0dd989000000b006078b764744mr104441ywe.2.1707855107574; Tue, 13 Feb 2024 12:11:47 -0800 (PST) Date: Tue, 13 Feb 2024 20:11:41 +0000 In-Reply-To: <20240213200923.2547570-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213200923.2547570-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213201141.2548566-1-ericchancf@google.com> Subject: [PATCH v4 1/4] riscv/barrier: Define __{mb,rmb,wmb} From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790815892868686533 X-GMAIL-MSGID: 1790815892868686533 Introduce __{mb,rmb,wmb}, and rely on the generic definitions for {mb,rmb,wmb}. Although KCSAN is not yet support, it can be made more consistent with generic instrumentation. Signed-off-by: Eric Chan --- v3 -> v4: fix commit message weird line breaks arch/riscv/include/asm/barrier.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.43.0.687.g38aa6559b0-goog diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 110752594228..4c49a8ff2c68 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -20,9 +20,9 @@ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ -#define mb() RISCV_FENCE(iorw,iorw) -#define rmb() RISCV_FENCE(ir,ir) -#define wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw,iorw) +#define __rmb() RISCV_FENCE(ir,ir) +#define __wmb() RISCV_FENCE(ow,ow) /* These barriers do not need to enforce ordering on devices, just memory. */ #define __smp_mb() RISCV_FENCE(rw,rw) From patchwork Tue Feb 13 20:11:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 200590 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp783541dyb; Tue, 13 Feb 2024 12:12:19 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXYdfmDUFF0s4wzU2LpEUPQt8QSHdzdx17aZjcZddp9ObZ6NLx24boZUmLxmbxVzApxLQiBQJUdFOc9cK0wvvqlg7l/SQ== X-Google-Smtp-Source: AGHT+IFeYmxQzJa/teO/z8fSwW20ZWoBsouqURB+8Rdvq+fHAcorm16of3PR7lFu9wrnVokAadcD X-Received: by 2002:a05:6402:b36:b0:560:4f1c:99c0 with SMTP id bo22-20020a0564020b3600b005604f1c99c0mr479263edb.13.1707855138850; Tue, 13 Feb 2024 12:12:18 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707855138; cv=pass; d=google.com; s=arc-20160816; b=zNqq4bvydqtK5vrL12ZAaSywn5Pkms0ulgXhsw/w5skZLLswiO/Niv6kojhS1dGkJW xOX6jZuDwflgZztbHisHkwCCLtdO5azSg0/sB5qDC17Nz4Ba04jajhc/4mMVqVyfnrmy pffkB6cnniC0agGayTZFc2gJZL9lMg1IvEcjsxx6qnw1mWzywLSgcDGFzO7p7jhqUl4s wCLL4zLHepf35y0xp2OJG6YSORjM9JCTi8cen97uAzExRC6exMBKUiEv0PauyjWv5t+c 16PiiVpsb+VSTpwpp7SUMc84HsqjRJs28E1SwqYZyx5szfggEqUZP1OM89J0pUxQ3ujC tlYw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:from:subject:message-id:references:mime-version :list-unsubscribe:list-subscribe:list-id:precedence:in-reply-to:date :dkim-signature; bh=2A5s0YU98xz4fK0cK8V3de3MUudesnEU1GM23Fa1guU=; fh=8VulGKvSKCURlgblKLY2Ao+QiMrgesSz3W94IRVQjow=; b=jSPTELjLuuoFD2EDAvykw1BDec6CG4zpLOxlRL7hM9WxGq7eAb2mq7t7uVTGZobfVY B5kJcQ0NDUYH/18HAJT76e1pPF3wWH6aXMMVt+Y+VSYjFiQGcpebcMevUNrZzi0ksrmY D6Tm7w6PdM8QDvJmFmC9hEKTY+0iq9mPpn4+WbA8Dn89ftPE+7v2ckQBOCpgDmYqax/M YWhQ+80P7wpznm/p92RaE1Qbm9UU9iVE2JaQpXl8jsuGUwpIjKH1iIrNYfR16XSGoKuj asOUs+iHSaSbUDa0PietsWD4kVqyn9fHrMRvT3lgl3a2oHR4I3BUPKWnLDk+blvWHOeM 1wdg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=FcchW9NF; arc=pass (i=1 spf=pass spfdomain=flex--ericchancf.bounces.google.com dkim=pass dkdomain=google.com dmarc=pass fromdomain=google.com); spf=pass (google.com: domain of linux-kernel+bounces-64216-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-64216-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com X-Forwarded-Encrypted: i=2; AJvYcCXosI4O5g9rgIOY+yfisjuRvmvYE4gCsiCIlwnJfFk89zHz7YgVSZT+i1K1ZwTTn2onGuzFSJ3S1+r1f4EzeD9OzK0TyQ== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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AJvYcCW73N1TtPIFxJUkC65CBv1VxW6UCoG+7G7UWR7Irot8HQJ+MR2QlKep/fpnCMq9wUPXUjhzSoEtd59zngFLx+zLc/dd0TcYQAh5N063 X-Gm-Message-State: AOJu0YxJCVmwjpffWg7dyyd7OnD5IDmrHwNn4TKtogCvhQqAoJ8K/y/K rDPxh01VAzDLy5xgiiAVvhTVkBS6tvpcICc+V9Yy15C/cMe3BqVmimkbYpddVYwHsAPWYqQlUZp QXsCIAWTBwETzk20c0A== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6a00:c94:b0:6e0:59a6:fbab with SMTP id a20-20020a056a000c9400b006e059a6fbabmr103151pfv.1.1707855122648; Tue, 13 Feb 2024 12:12:02 -0800 (PST) Date: Tue, 13 Feb 2024 20:11:56 +0000 In-Reply-To: <20240213200923.2547570-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213200923.2547570-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213201156.2549021-1-ericchancf@google.com> Subject: [PATCH v4 2/4] riscv/barrier: Define RISCV_FULL_BARRIER From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790815910266232581 X-GMAIL-MSGID: 1790815910266232581 Introduce RISCV_FULL_BARRIER and use in arch_atomic* function. like RISCV_ACQUIRE_BARRIER and RISCV_RELEASE_BARRIER, the fence instruction can be eliminated When SMP is not enabled. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 16 ++++++++-------- arch/riscv/include/asm/cmpxchg.h | 4 ++-- arch/riscv/include/asm/fence.h | 2 ++ 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index f5dfef6c2153..31e6e2e7cc18 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -207,7 +207,7 @@ static __always_inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int " add %[rc], %[p], %[a]\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -228,7 +228,7 @@ static __always_inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, " add %[rc], %[p], %[a]\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -248,7 +248,7 @@ static __always_inline bool arch_atomic_inc_unless_negative(atomic_t *v) " addi %[rc], %[p], 1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -268,7 +268,7 @@ static __always_inline bool arch_atomic_dec_unless_positive(atomic_t *v) " addi %[rc], %[p], -1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -288,7 +288,7 @@ static __always_inline int arch_atomic_dec_if_positive(atomic_t *v) " bltz %[rc], 1f\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -310,7 +310,7 @@ static __always_inline bool arch_atomic64_inc_unless_negative(atomic64_t *v) " addi %[rc], %[p], 1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -331,7 +331,7 @@ static __always_inline bool arch_atomic64_dec_unless_positive(atomic64_t *v) " addi %[rc], %[p], -1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -352,7 +352,7 @@ static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) " bltz %[rc], 1f\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 2f4726d3cfcc..a608e4d1a0a4 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -313,7 +313,7 @@ " bne %0, %z3, 1f\n" \ " sc.w.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" ((long)__old), "rJ" (__new) \ @@ -325,7 +325,7 @@ " bne %0, %z3, 1f\n" \ " sc.d.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" (__old), "rJ" (__new) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 2b443a3a487f..6c26c44dfcd6 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -4,9 +4,11 @@ #ifdef CONFIG_SMP #define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" #define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#define RISCV_FULL_BARRIER "\tfence rw, rw\n" #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER +#define RISCV_FULL_BARRIER #endif #endif /* _ASM_RISCV_FENCE_H */ From patchwork Tue Feb 13 20:12:10 2024 Content-Type: text/plain; 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AJvYcCVN9OXK3Vsce7GA0EnOsG7UEBm0CdWSG4f5xby45SbqfwUgVKC2t5nsmyWcvkE4CRspk9vDq9BcwZb03GrwopSC6SOkD6UsnjNtoNOv X-Gm-Message-State: AOJu0YwTfR9iPFUA3bukeogAlKkpmqzooFlcpCZhf3aFlbWroZ94SOs9 v5ppLm1n2QYCWMhu0NtkUVqFdP7qEohVz1RVNzd2QrIYM8BWeSwaHYs5k3ugzUChCEiZ+zdwME7 lGetFFbNAsYEDOCTKjg== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a0d:eac3:0:b0:5ff:b07b:fb83 with SMTP id t186-20020a0deac3000000b005ffb07bfb83mr74538ywe.4.1707855135937; Tue, 13 Feb 2024 12:12:15 -0800 (PST) Date: Tue, 13 Feb 2024 20:12:10 +0000 In-Reply-To: <20240213200923.2547570-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213200923.2547570-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213201210.2549488-1-ericchancf@google.com> Subject: [PATCH v4 3/4] riscv/barrier: Consolidate fence definitions From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790815923266909497 X-GMAIL-MSGID: 1790815923266909497 Disparate fence implementations are consolidated into fence.h. Also introduce RISCV_FENCE_ASM to make fence macro more reusable. Signed-off-by: Eric Chan --- v3 -> v4: fix the form that can pass the checking of checkpatch.pl. arch/riscv/include/asm/atomic.h | 8 ++------ arch/riscv/include/asm/barrier.h | 3 +-- arch/riscv/include/asm/cmpxchg.h | 1 - arch/riscv/include/asm/fence.h | 10 +++++++--- arch/riscv/include/asm/io.h | 8 ++++---- arch/riscv/include/asm/mmio.h | 5 +++-- arch/riscv/include/asm/mmiowb.h | 2 +- 7 files changed, 18 insertions(+), 19 deletions(-) -- 2.43.0.687.g38aa6559b0-goog diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 31e6e2e7cc18..19050d13b6c1 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -17,13 +17,9 @@ #endif #include -#include -#define __atomic_acquire_fence() \ - __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") - -#define __atomic_release_fence() \ - __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory"); +#define __atomic_acquire_fence() RISCV_FENCE(r, rw) +#define __atomic_release_fence() RISCV_FENCE(rw, r) static __always_inline int arch_atomic_read(const atomic_t *v) { diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 4c49a8ff2c68..4f4743d7440d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -11,13 +11,12 @@ #define _ASM_RISCV_BARRIER_H #ifndef __ASSEMBLY__ +#include #define nop() __asm__ __volatile__ ("nop") #define __nops(n) ".rept " #n "\nnop\n.endr\n" #define nops(n) __asm__ __volatile__ (__nops(n)) -#define RISCV_FENCE(p, s) \ - __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ #define __mb() RISCV_FENCE(iorw,iorw) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index a608e4d1a0a4..2fee65cc8443 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -8,7 +8,6 @@ #include -#include #include #define __xchg_relaxed(ptr, new, size) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 6c26c44dfcd6..5b46f96a3ec8 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -1,10 +1,14 @@ #ifndef _ASM_RISCV_FENCE_H #define _ASM_RISCV_FENCE_H +#define RISCV_FENCE_ASM(p, s) "\tfence " #p "," #s "\n" +#define RISCV_FENCE(p, s) \ + ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) + #ifdef CONFIG_SMP -#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" -#define RISCV_RELEASE_BARRIER "\tfence rw, w\n" -#define RISCV_FULL_BARRIER "\tfence rw, rw\n" +#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r, rw) +#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw, r) +#define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw, rw) #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 42497d487a17..1c5c641075d2 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -47,10 +47,10 @@ * sufficient to ensure this works sanely on controllers that support I/O * writes. */ -#define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory"); -#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory"); -#define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); -#define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); +#define __io_pbr() RISCV_FENCE(io, i) +#define __io_par(v) RISCV_FENCE(i, ior) +#define __io_pbw() RISCV_FENCE(iow, o) +#define __io_paw() RISCV_FENCE(o, io) /* * Accesses from a single hart to a single I/O address must be ordered. This diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index 4c58ee7f95ec..06cadfd7a237 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -12,6 +12,7 @@ #define _ASM_RISCV_MMIO_H #include +#include #include /* Generic IO read/write. These perform native-endian accesses. */ @@ -131,8 +132,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); }) -#define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) +#define __io_ar(v) RISCV_FENCE(i, ir) +#define __io_bw() RISCV_FENCE(w, o) #define __io_aw() mmiowb_set_pending() #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiowb.h index 0b2333e71fdc..52ce4a399d9b 100644 --- a/arch/riscv/include/asm/mmiowb.h +++ b/arch/riscv/include/asm/mmiowb.h @@ -7,7 +7,7 @@ * "o,w" is sufficient to ensure that all writes to the device have completed * before the write to the spinlock is allowed to commit. */ -#define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory"); +#define mmiowb() RISCV_FENCE(o, w) #include #include From patchwork Tue Feb 13 20:12:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 200592 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp783933dyb; Tue, 13 Feb 2024 12:13:01 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU/oUgOro21mPWMInHPlu16CeXRUOnnBEgs2IS0f4g/YTYwmSDLt3+sX422X8CyugjrbAypQF1YU05c2wEMTU5nYrAXjA== X-Google-Smtp-Source: AGHT+IH447IGkHY9mMRV9yIKJi0O/7gn6CZnm8FJeTqHJdtsWpXtKMk0DXTc2EuGnB1Flx+859qR X-Received: by 2002:a17:902:db06:b0:1d9:ca7e:f0a8 with SMTP id m6-20020a170902db0600b001d9ca7ef0a8mr779015plx.1.1707855181530; Tue, 13 Feb 2024 12:13:01 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707855181; cv=pass; d=google.com; s=arc-20160816; b=BMftAPkJcZii0tmVwgKNenYYkGiRSJIC3ONL+ieaD9j8EaCc9LXILy0rYqLvw/rwEr fHhAKyQlQTsGn2yIgtdwtdTLWrkfVpy9MU0UC7DuLzL1rSYCO+JU5gbDVgrh456g0wyD roohOp+029nN5z3Qhl2/oie7foZmRAcC4T4B0zay+ndAYalLKEXWaKnr3ohpKrYIL32Q VmS9xW+n6c6u6avWj+foR0a9iv2ah+5zSuS0hccBHCNFcvL3hcsv7KyrHRXwbHC7ylzv 8awHd7EMFmER+P56j1XrNkfpzGE/rWc4XwzLzwxvxJYsCYItI3r7yd1lyHv+x+NUsAH7 ni5A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:from:subject:message-id:references:mime-version :list-unsubscribe:list-subscribe:list-id:precedence:in-reply-to:date :dkim-signature; bh=RC2T9SgmWwA0L5LQ8BYxxpjFIKV4b3AtrMRzB+GqR24=; fh=OzUm7TrYu8MyhUgouem3k5PvE+uKQ5l/wePHBmTREHo=; b=EZiQTQFzjmsOgOSWcDkWCZkHTNOAsOZTJZKTqr+FPZUsm3dPF3n9glhR55KVHtcvvI MDm2v8ucE9qC2ZskOo0LSMaSMxyAtjYADox4mcnYO08ITgMlG07cxsyqhrk4irGYp9le 3ZS6/ilONh5xrU/udVP4eHAQNxINiYri1DzBeD71K2BDEYtZutTElrznWPHQEFipDGj7 Ax1UjFJ7/U4h2JzIColwwvF5YpqUq6FzYnatpNMv5qjnP8zVXjfEvQaU6/aVSDPXxENd lRM5dqPf6y1aEeVjoVoqZUfCEZ3Dit/7t/1jVAa3HF2Eu/Ihh2JTmepR0ZlsXYPub21D b1ZQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=qXmhTkpz; arc=pass (i=1 spf=pass spfdomain=flex--ericchancf.bounces.google.com dkim=pass dkdomain=google.com dmarc=pass fromdomain=google.com); spf=pass (google.com: domain of linux-kernel+bounces-64219-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-64219-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com X-Forwarded-Encrypted: i=2; AJvYcCWlA1QsywuOwuvAJVcIDeSskc5Ds7wPxaiO+egoD5M5H1SGpd0HK7kf5fZszGaXH92SP1iPDHSMRrLHTpulXevxQujAUA== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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AJvYcCXaV1QvZ342QLq0JsNIR+EqciGHg66Ozs8+A/MrcG9b/PhTlpDPu3F6aanG0eY1S7QoEAWr02xa7hbHshoTGGOvoS74v5AnF626Hdmr X-Gm-Message-State: AOJu0Yz8/YOIkhZSxrvCggL2/BRf2faUuRNB031RFPQ3RdIizQcKADNI EEA+ymSPK91Syy76pOzV/9hO0B+2NQNVllHWo53Z3rVsQzaoMis8mC/dR90PWCp2dwpmvx2FbuV 5ORlq3fw2F/CFop03qA== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a0d:d752:0:b0:5ff:6623:be27 with SMTP id z79-20020a0dd752000000b005ff6623be27mr93462ywd.3.1707855147567; Tue, 13 Feb 2024 12:12:27 -0800 (PST) Date: Tue, 13 Feb 2024 20:12:21 +0000 In-Reply-To: <20240213200923.2547570-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213200923.2547570-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213201221.2549924-1-ericchancf@google.com> Subject: [PATCH v4 4/4] riscv/barrier: Resolve checkpatch.pl error From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790815954924315309 X-GMAIL-MSGID: 1790815954924315309 The past form of RISCV_FENCE would cause checkpatch.pl to issue error messages, the example is as follows: ERROR: space required after that ',' (ctx:VxV) +#define __atomic_acquire_fence() RISCV_FENCE(r,rw) ^ fix the remaining of RISCV_FENCE. Signed-off-by: Eric Chan --- arch/riscv/include/asm/barrier.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) -- 2.43.0.687.g38aa6559b0-goog diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 4f4743d7440d..880b56d8480d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -19,19 +19,19 @@ /* These barriers need to enforce ordering on both devices or memory. */ -#define __mb() RISCV_FENCE(iorw,iorw) -#define __rmb() RISCV_FENCE(ir,ir) -#define __wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw, iorw) +#define __rmb() RISCV_FENCE(ir, ir) +#define __wmb() RISCV_FENCE(ow, ow) /* These barriers do not need to enforce ordering on devices, just memory. */ -#define __smp_mb() RISCV_FENCE(rw,rw) -#define __smp_rmb() RISCV_FENCE(r,r) -#define __smp_wmb() RISCV_FENCE(w,w) +#define __smp_mb() RISCV_FENCE(rw, rw) +#define __smp_rmb() RISCV_FENCE(r, r) +#define __smp_wmb() RISCV_FENCE(w, w) #define __smp_store_release(p, v) \ do { \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(rw,w); \ + RISCV_FENCE(rw, w); \ WRITE_ONCE(*p, v); \ } while (0) @@ -39,7 +39,7 @@ do { \ ({ \ typeof(*p) ___p1 = READ_ONCE(*p); \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(r,rw); \ + RISCV_FENCE(r, rw); \ ___p1; \ }) @@ -68,7 +68,7 @@ do { \ * instances the scheduler pairs this with an mb(), so nothing is necessary on * the new hart. */ -#define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw) +#define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw) #include