From patchwork Tue Feb 13 18:03:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Parvathaneni X-Patchwork-Id: 200539 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp711179dyb; Tue, 13 Feb 2024 10:03:28 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXyva0H/+agYaCKxoBEIxdS7aC/ODJeC1nv7XGFQHY/2aji3qDSbNb4q2HeFQw7yG8f5810uCADZ5tQSn/Vr5JTMehrFg== X-Google-Smtp-Source: AGHT+IEEQzLz0AI1iD+xNkaZ6U4bt8CUc5FvXMinuMPqqUkGI4gfa6Qps1M7YCCwl89X9du06vL8 X-Received: by 2002:a05:6214:c2f:b0:68c:9698:5a3d with SMTP id a15-20020a0562140c2f00b0068c96985a3dmr211457qvd.37.1707847408102; Tue, 13 Feb 2024 10:03:28 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707847408; cv=pass; d=google.com; s=arc-20160816; b=InS79X/9axjMfQiPQNOSFRPSyRzlUSjrG1y3lTNOsziJ84dwsvqfJt3KOJbHwCcEZW zWhKCkqyAEwRkW3wIaCOauQzp9P9BZcF8uC+Z5zbR/n+FMm+j49Pq4Bgf2UFmTVv9U9p lniRQmXfy+8CY3cLjzcxG2M4UAwpDCPuRgS3gRAMOq9wpqawIMmyHu5aKsgTJaE1X0Re bzNPYjXFkwDIYKRlVBvSz8bxJYNAR3+5wIQz1cwn9aqOV9Ox26QJiIjx+I5XeCJvKEDd 7XEM7+pQ9JUdBoUnFagNGqt+IeIFIlb/53frD8ua1zSD3JEtrFvSxqtLUrudAkADPN20 6WKw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:arc-filter :dmarc-filter:delivered-to; bh=dwDnV+jLSbi3ielw81U6lLEcbMCZD2JOy81vL59zkvo=; fh=+wLiPdAJGMPoWKpqXHURAcW2AP6Ib3o6CQgEduRpl/8=; b=ebRTnf4lm/vxImDfxizaskxYLiBv7PFpFOlmxuKscv89lD5YGFqTrJON23370BQ084 Tkn90P5ZFN5qp1sHJIt6GWdt521p0JJk0E97jFOFF8Ix2bgqZ5ga6uX9fahxXeh5iPYD PX3D0qJYKK70qnBSk6zbUItv1DEYeAJZeBsW/0VYIjOcFu7BdJS8DfW2dp/m+Uh/gtAc l7aPUezTafuPcmLY94HZ6DpZuXncGKhZ/jkUvmLY4uFiN8ERzPqtRUcC+yTt28rh4l3K F7PjCzESCSRQRTBp6wzFb1F/5TqCkAA8EtI79VlxhLNaPUjRqjkRvAqPDmNzFahpzpmk d2Ow==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com X-Forwarded-Encrypted: i=2; AJvYcCUw37To9fGs10FakRYQRtpY8DGJeX8FlPn53DbMlybC+hGziuHcy1UFQgAnFyWk0jo+O3SWrYTu3W7fRHK0WsS7YgbfOg== Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id jp12-20020ad45f8c000000b00685c947ea1dsi3350743qvb.535.2024.02.13.10.03.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Feb 2024 10:03:28 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C9F743857C41 for ; Tue, 13 Feb 2024 18:03:27 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat-cam2.arm.com [217.140.106.50]) by sourceware.org (Postfix) with ESMTPS id 355213857C51 for ; Tue, 13 Feb 2024 18:03:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 355213857C51 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 355213857C51 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.106.50 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707847398; cv=none; b=Lc2o6rezlpiyOOKXxXnyZxA8Nz+hv1fqGZT5HhKmAb/GxigiQq/2nco42IibOpxQdSXBdOcjtxVhMkuTmLbSiMJf7urGCqYquhVHkmkunDkbAMTzN3GKu3+As4e+oRH/VSiOg5XK97u4e4NoAL9Nv9SFqiVZ/BsH9lfxIau4nwQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707847398; c=relaxed/simple; bh=+ghq3ehLFCiRKWT48HZfMMUI67Mxs3aYL6cNUb1xLpo=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=uqr9LCZwbxOMjwQXYWRZQclj6fH/FUr26dGC/GAx1mQ5LASeb01ci4VVTgF6fREiJ1OXBojFlnDClrW2Iah/QXS6kAs5CabmK2dsvBqfqW6ctN7x5rFCoQGKVDQAWA3N7z6asvukzRrGri+5/Yidz8NS9iTN020W9v7V9ZicjFQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from e120703.cambridge.arm.com (e120703.arm.com [10.2.81.20]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id 41DI3DwT018529; Tue, 13 Feb 2024 18:03:13 GMT From: srinath To: binutils@sourceware.org Cc: richard.earnshaw@arm.com, nickc@redhat.com, Srinath Parvathaneni Subject: [PATCH v1 1/1][Binutils] aarch64: Fix the 2nd operand in gcsstr and gcssttr instructions. Date: Tue, 13 Feb 2024 18:03:11 +0000 Message-Id: <20240213180311.2141095-1-srinath.parvathaneni@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-24.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KHOP_HELO_FCRDNS, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790807803548153103 X-GMAIL-MSGID: 1790807803548153103 Hi, The assembler wrongly expects plain register name instead of memory-form 2nd operand for gcsstr and gcssttr instructions. This patch fixes the issue. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Also ok to be backported to binutils-2.42 branch? Regards, Srinath. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31376 --- gas/testsuite/gas/aarch64/gcs-1-bad.l | 48 +++++++++++++-------------- gas/testsuite/gas/aarch64/gcs-1.d | 48 +++++++++++++-------------- gas/testsuite/gas/aarch64/gcs-1.s | 2 +- opcodes/aarch64-tbl.h | 4 +-- 4 files changed, 51 insertions(+), 51 deletions(-) diff --git a/gas/testsuite/gas/aarch64/gcs-1-bad.l b/gas/testsuite/gas/aarch64/gcs-1-bad.l index ca8d17ab8fc..4c69c6e1c57 100644 --- a/gas/testsuite/gas/aarch64/gcs-1-bad.l +++ b/gas/testsuite/gas/aarch64/gcs-1-bad.l @@ -19,27 +19,27 @@ [^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x15' [^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x30' [^ :]+:[0-9]+: Error: selected processor does not support `gcspopm xzr' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,x1' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,x16' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,sp' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,x1' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,x16' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,sp' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,x1' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,x16' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,sp' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,x1' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,x16' -[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,sp' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,x1' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,x16' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,sp' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,x1' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,x16' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,sp' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,x1' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,x16' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,sp' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,x1' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,x16' -[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,sp' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,\[x1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,\[x16\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,\[x1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,\[x16\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,\[x1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,\[x16\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,\[x1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,\[x16\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,\[x1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,\[x16\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,\[x1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,\[x16\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,\[x1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,\[x16\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,\[x1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,\[x16\]' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,\[sp\]' diff --git a/gas/testsuite/gas/aarch64/gcs-1.d b/gas/testsuite/gas/aarch64/gcs-1.d index 09fa418e5ea..ff059a36525 100644 --- a/gas/testsuite/gas/aarch64/gcs-1.d +++ b/gas/testsuite/gas/aarch64/gcs-1.d @@ -29,27 +29,27 @@ .*: d52b772f gcspopm x15 .*: d52b773e gcspopm x30 .*: d52b773f gcspopm -.*: d91f0c20 gcsstr x0, x1 -.*: d91f0e00 gcsstr x0, x16 -.*: d91f0fe0 gcsstr x0, sp -.*: d91f0c2f gcsstr x15, x1 -.*: d91f0e0f gcsstr x15, x16 -.*: d91f0fef gcsstr x15, sp -.*: d91f0c3e gcsstr x30, x1 -.*: d91f0e1e gcsstr x30, x16 -.*: d91f0ffe gcsstr x30, sp -.*: d91f0c3f gcsstr xzr, x1 -.*: d91f0e1f gcsstr xzr, x16 -.*: d91f0fff gcsstr xzr, sp -.*: d91f1c20 gcssttr x0, x1 -.*: d91f1e00 gcssttr x0, x16 -.*: d91f1fe0 gcssttr x0, sp -.*: d91f1c2f gcssttr x15, x1 -.*: d91f1e0f gcssttr x15, x16 -.*: d91f1fef gcssttr x15, sp -.*: d91f1c3e gcssttr x30, x1 -.*: d91f1e1e gcssttr x30, x16 -.*: d91f1ffe gcssttr x30, sp -.*: d91f1c3f gcssttr xzr, x1 -.*: d91f1e1f gcssttr xzr, x16 -.*: d91f1fff gcssttr xzr, sp +.*: d91f0c20 gcsstr x0, \[x1\] +.*: d91f0e00 gcsstr x0, \[x16\] +.*: d91f0fe0 gcsstr x0, \[sp\] +.*: d91f0c2f gcsstr x15, \[x1\] +.*: d91f0e0f gcsstr x15, \[x16\] +.*: d91f0fef gcsstr x15, \[sp\] +.*: d91f0c3e gcsstr x30, \[x1\] +.*: d91f0e1e gcsstr x30, \[x16\] +.*: d91f0ffe gcsstr x30, \[sp\] +.*: d91f0c3f gcsstr xzr, \[x1\] +.*: d91f0e1f gcsstr xzr, \[x16\] +.*: d91f0fff gcsstr xzr, \[sp\] +.*: d91f1c20 gcssttr x0, \[x1\] +.*: d91f1e00 gcssttr x0, \[x16\] +.*: d91f1fe0 gcssttr x0, \[sp\] +.*: d91f1c2f gcssttr x15, \[x1\] +.*: d91f1e0f gcssttr x15, \[x16\] +.*: d91f1fef gcssttr x15, \[sp\] +.*: d91f1c3e gcssttr x30, \[x1\] +.*: d91f1e1e gcssttr x30, \[x16\] +.*: d91f1ffe gcssttr x30, \[sp\] +.*: d91f1c3f gcssttr xzr, \[x1\] +.*: d91f1e1f gcssttr xzr, \[x16\] +.*: d91f1fff gcssttr xzr, \[sp\] diff --git a/gas/testsuite/gas/aarch64/gcs-1.s b/gas/testsuite/gas/aarch64/gcs-1.s index 35584a8810e..17734f9f979 100644 --- a/gas/testsuite/gas/aarch64/gcs-1.s +++ b/gas/testsuite/gas/aarch64/gcs-1.s @@ -14,7 +14,7 @@ .irp op gcsstr, gcssttr .irp reg1 x0, x15, x30, xzr .irp reg2 x1, x16, sp - \op \reg1, \reg2 + \op \reg1, [\reg2] .endr .endr .endr diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 9ea4de01c60..18ac80251e9 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4283,8 +4283,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = GCS_INSN ("gcsss2", 0xd52b7760, 0xffffffe0, OP1 (Rt), QL_I1X, 0), GCS_INSN ("gcspopm", 0xd52b773f, 0xffffffff, OP0 (), {}, 0), GCS_INSN ("gcspopm", 0xd52b7720, 0xffffffe0, OP1 (Rt), QL_I1X, 0), - GCS_INSN ("gcsstr", 0xd91f0c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0), - GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0), + GCS_INSN ("gcsstr", 0xd91f0c00, 0xfffffc00, OP2 (Rt, ADDR_SIMPLE), QL_DST_X, 0), + GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, ADDR_SIMPLE), QL_DST_X, 0), CORE_INSN ("gcsb", 0xd503227f, 0xffffffff, ic_system, 0, OP1 (BARRIER_GCSB), {}, F_ALIAS), CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)), D128_INSN ("sysp", 0xd5480000, 0xfff80000, OP6 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt, PAIRREG_OR_XZR), QL_SYSP, F_HAS_ALIAS | F_OPD_NARROW | F_OPD4_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)),