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AJvYcCV/ROWtHSVL4gthMIudCU9Sfqu99ATwDZKFdrUkPnRSFTc7YlOjKyjNWj/Wj1NDZG1JR8NlRwCcGKsnyFzzTmCLTf0TJ3i6zducMOMx X-Gm-Message-State: AOJu0YxHsC5TMGppArQDlIUOsTy1LxEx2PZqgBo3Waz2mJ2O47js7N8a HzZ6Q/QXAI40Y4Z4fdBRcPNhdmNgd/AApzfJiosA7s919FiBmz0p1+7Gc5+KNlzHb/hjbnaH558 5khiWpSmYRn5sWra30w== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a81:920c:0:b0:5ff:6ec3:b8da with SMTP id j12-20020a81920c000000b005ff6ec3b8damr564874ywg.1.1707834542765; Tue, 13 Feb 2024 06:29:02 -0800 (PST) Date: Tue, 13 Feb 2024 14:28:56 +0000 In-Reply-To: <20240213142632.2415127-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213142632.2415127-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213142856.2416073-1-ericchancf@google.com> Subject: [PATCH v3 1/4] riscv/barrier: Define __{mb,rmb,wmb} From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790794346249958904 X-GMAIL-MSGID: 1790794346249958904 Introduce __{mb,rmb,wmb}, and rely on the generic definitions for {mb,rmb,wmb}. Although KCSAN is not yet support, it can be made more consistent with generic instrumentation. Signed-off-by: Eric Chan --- arch/riscv/include/asm/barrier.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 110752594228..4c49a8ff2c68 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -20,9 +20,9 @@ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ -#define mb() RISCV_FENCE(iorw,iorw) -#define rmb() RISCV_FENCE(ir,ir) -#define wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw,iorw) +#define __rmb() RISCV_FENCE(ir,ir) +#define __wmb() RISCV_FENCE(ow,ow) /* These barriers do not need to enforce ordering on devices, just memory. */ #define __smp_mb() RISCV_FENCE(rw,rw) From patchwork Tue Feb 13 14:29:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 200449 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp577137dyb; Tue, 13 Feb 2024 06:33:55 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUkyrMO6O7H3dcs4RSGhBAHt6LwHICyvcUHZ0X62AeQi33UxRHhWjcYg0g1YFE5PU/l7rL6QADRPAZATLiCBcCeoetvaA== X-Google-Smtp-Source: AGHT+IFtw5tTMAx41gdniUuf3SgUC2u0SG+53DQXvf4Osu8PkgfBQvyu1RMsZ0i4vZMcbUTJEmbk X-Received: by 2002:a17:902:e543:b0:1da:2a91:8c08 with SMTP id n3-20020a170902e54300b001da2a918c08mr7680691plf.3.1707834835417; Tue, 13 Feb 2024 06:33:55 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707834835; cv=pass; d=google.com; s=arc-20160816; b=KnRcg8n8/4rKX3cWBXCtAe5SaA+YP6OxpbgyXokJAoDnn9weGOWBa/t9owQ9OZX8Rx sp1JKLNvnfxfCEJZ7aetJteKJ8+2VWw+XJdt4+6Fx4Z0pbtFu2O9+jT7KODJFgm/T6V8 ZylsHV8AygvcryEZyKWv1EN5WrgXiQeBkShAymAcnnVci9vks3GRAfP0RJhhLeM2GMwc c8nXTsAxULYnZeJfPRNQjujEGpd2GojkUdPjIQYD/vRAs/TSCWyhb159QyjxhcSaQ1g1 bn6uF2UtT5mlEeHKOEHi43EAX5OedVDb8aTGL3UolLnIKcflhcyllo0G831VatAuNlD3 TMjA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:from:subject:message-id:references:mime-version :list-unsubscribe:list-subscribe:list-id:precedence:in-reply-to:date :dkim-signature; bh=2A5s0YU98xz4fK0cK8V3de3MUudesnEU1GM23Fa1guU=; fh=jSygJ/5NTkCZZkXlhcsFA/j+RLQQPBpU48g2ejdm5a4=; b=L3W8qeRPvugmOMBdvhvmE+vszo0sLavM4hkSdEH0/1LCgJ8w6Xs1WOi8orsUOq0wfa H8uvXAi5c+aY4POO5BmeuQbYbHEKHHRLAoV+D9TrCMkejGGRGW93VwV+NVjbHfaC0x8P Q1WIfpB1DT31V7iBXwPFnqTm0wHynpTgg/mteilUhnkCwliE/2yPaEZrdeTkn6bJCGmd WFUz9D077MKHqoeiLdCp6uki9IFnnTfnWboq9mByKa2ESJIU+IG8+y9tGirZ4Zw7WQV+ 9QaYOc56YJ3vnFvY9b+JPgqDjVnrLpdf1f+0V3YrPCe1eUGjYFxalN4Pn63aELiNF9ld orsg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b="cfS+y//Q"; arc=pass (i=1 spf=pass spfdomain=flex--ericchancf.bounces.google.com dkim=pass dkdomain=google.com dmarc=pass fromdomain=google.com); spf=pass (google.com: domain of linux-kernel+bounces-63678-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-63678-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com X-Forwarded-Encrypted: i=2; AJvYcCWMQKrl5K1OK+pJthDJUxemXtpeoNP9zju7tlL/eyuKa40uTyc+JRvPxjdw4CjLC6DYTFu40hEWOBMj4cvu3hr1sMMMZg== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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AJvYcCUlIsNKCTbjGFZVJRi3pGNuAYdYbHu/n0A3/qD6Fhp1IGlUrFliQIxp10a2qRIZWQIAsR0t136tKYJco6qW8FQJXecw1F04/WpzIKEx X-Gm-Message-State: AOJu0YwR7gEEf9MIGcMiTdFurPS4TYYMeOzQsgWb/6+Xw+Y5iwVmnc3N 4o1JXOMg25LeirWAmSQCKDAkX5n9uyPjsuY9yBnIB+tcmcrKw045168BLdydcRUrK9UoWaokuNQ eKRRkVonf25mYNb6uFw== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a25:69c4:0:b0:dcc:53c6:1133 with SMTP id e187-20020a2569c4000000b00dcc53c61133mr76167ybc.13.1707834565189; Tue, 13 Feb 2024 06:29:25 -0800 (PST) Date: Tue, 13 Feb 2024 14:29:19 +0000 In-Reply-To: <20240213142632.2415127-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213142632.2415127-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213142919.2416728-1-ericchancf@google.com> Subject: [PATCH v3 2/4] riscv/barrier: Define RISCV_FULL_BARRIER From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790794620026737927 X-GMAIL-MSGID: 1790794620026737927 Introduce RISCV_FULL_BARRIER and use in arch_atomic* function. like RISCV_ACQUIRE_BARRIER and RISCV_RELEASE_BARRIER, the fence instruction can be eliminated When SMP is not enabled. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 16 ++++++++-------- arch/riscv/include/asm/cmpxchg.h | 4 ++-- arch/riscv/include/asm/fence.h | 2 ++ 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index f5dfef6c2153..31e6e2e7cc18 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -207,7 +207,7 @@ static __always_inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int " add %[rc], %[p], %[a]\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -228,7 +228,7 @@ static __always_inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, " add %[rc], %[p], %[a]\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -248,7 +248,7 @@ static __always_inline bool arch_atomic_inc_unless_negative(atomic_t *v) " addi %[rc], %[p], 1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -268,7 +268,7 @@ static __always_inline bool arch_atomic_dec_unless_positive(atomic_t *v) " addi %[rc], %[p], -1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -288,7 +288,7 @@ static __always_inline int arch_atomic_dec_if_positive(atomic_t *v) " bltz %[rc], 1f\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -310,7 +310,7 @@ static __always_inline bool arch_atomic64_inc_unless_negative(atomic64_t *v) " addi %[rc], %[p], 1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -331,7 +331,7 @@ static __always_inline bool arch_atomic64_dec_unless_positive(atomic64_t *v) " addi %[rc], %[p], -1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -352,7 +352,7 @@ static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) " bltz %[rc], 1f\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 2f4726d3cfcc..a608e4d1a0a4 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -313,7 +313,7 @@ " bne %0, %z3, 1f\n" \ " sc.w.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" ((long)__old), "rJ" (__new) \ @@ -325,7 +325,7 @@ " bne %0, %z3, 1f\n" \ " sc.d.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" (__old), "rJ" (__new) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 2b443a3a487f..6c26c44dfcd6 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -4,9 +4,11 @@ #ifdef CONFIG_SMP #define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" #define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#define RISCV_FULL_BARRIER "\tfence rw, rw\n" #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER +#define RISCV_FULL_BARRIER #endif #endif /* _ASM_RISCV_FENCE_H */ From patchwork Tue Feb 13 14:29:33 2024 Content-Type: text/plain; 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AJvYcCXV1rcqMx090d7F3clZeYoVtjF6SuYYVMJJ/XY/n/MTRFWtwDErYIOagx66nvxvEAhT2lgYIZ+8F6lz+dzHQ3bJ3akhGNbrFXsHy/8Y X-Gm-Message-State: AOJu0YzU590wg9QvbsNJu2JxOoVIGTtTHz15s5pLuRpvS3e7pixI35Oe 2h6ALnPeY8T/lhCsh5QHuN9+w+hcmkpmZd+3C9vymAreZ8iI0lL9HibIl9+Qel25SxMR+tJza6y sm1DQ6e2EmAttDM9jyw== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:1884:b0:dc7:68b5:4f3d with SMTP id cj4-20020a056902188400b00dc768b54f3dmr2393690ybb.11.1707834578969; Tue, 13 Feb 2024 06:29:38 -0800 (PST) Date: Tue, 13 Feb 2024 14:29:33 +0000 In-Reply-To: <20240213142632.2415127-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213142632.2415127-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213142933.2417154-1-ericchancf@google.com> Subject: [PATCH v3 3/4] riscv/barrier: Consolidate fence definitions From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790794484105329873 X-GMAIL-MSGID: 1790794484105329873 Disparate fence implementations are consolidated into fence.h. And align with the existing form. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 8 ++------ arch/riscv/include/asm/barrier.h | 3 +-- arch/riscv/include/asm/cmpxchg.h | 1 - arch/riscv/include/asm/fence.h | 10 +++++++--- arch/riscv/include/asm/io.h | 8 ++++---- arch/riscv/include/asm/mmio.h | 5 +++-- arch/riscv/include/asm/mmiowb.h | 2 +- 7 files changed, 18 insertions(+), 19 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 31e6e2e7cc18..1b2ae3259f1d 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -17,13 +17,9 @@ #endif #include -#include -#define __atomic_acquire_fence() \ - __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") - -#define __atomic_release_fence() \ - __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory"); +#define __atomic_acquire_fence() RISCV_FENCE(r,rw) +#define __atomic_release_fence() RISCV_FENCE(rw,r) static __always_inline int arch_atomic_read(const atomic_t *v) { diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 4c49a8ff2c68..4f4743d7440d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -11,13 +11,12 @@ #define _ASM_RISCV_BARRIER_H #ifndef __ASSEMBLY__ +#include #define nop() __asm__ __volatile__ ("nop") #define __nops(n) ".rept " #n "\nnop\n.endr\n" #define nops(n) __asm__ __volatile__ (__nops(n)) -#define RISCV_FENCE(p, s) \ - __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ #define __mb() RISCV_FENCE(iorw,iorw) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index a608e4d1a0a4..2fee65cc8443 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -8,7 +8,6 @@ #include -#include #include #define __xchg_relaxed(ptr, new, size) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 6c26c44dfcd6..ca094d72ec20 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -1,10 +1,14 @@ #ifndef _ASM_RISCV_FENCE_H #define _ASM_RISCV_FENCE_H +#define RISCV_FENCE_ASM(p, s) "\tfence " #p "," #s "\n" +#define RISCV_FENCE(p, s) \ + ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) + #ifdef CONFIG_SMP -#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" -#define RISCV_RELEASE_BARRIER "\tfence rw, w\n" -#define RISCV_FULL_BARRIER "\tfence rw, rw\n" +#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r,rw) +#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw,r) +#define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw,rw) #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 42497d487a17..afb5ead7552e 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -47,10 +47,10 @@ * sufficient to ensure this works sanely on controllers that support I/O * writes. */ -#define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory"); -#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory"); -#define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); -#define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); +#define __io_pbr() RISCV_FENCE(io,i) +#define __io_par(v) RISCV_FENCE(i,ior) +#define __io_pbw() RISCV_FENCE(iow,o) +#define __io_paw() RISCV_FENCE(o,io) /* * Accesses from a single hart to a single I/O address must be ordered. This diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index 4c58ee7f95ec..a708968d4a0f 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -12,6 +12,7 @@ #define _ASM_RISCV_MMIO_H #include +#include #include /* Generic IO read/write. These perform native-endian accesses. */ @@ -131,8 +132,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); }) -#define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) +#define __io_ar(v) RISCV_FENCE(i,ir) +#define __io_bw() RISCV_FENCE(w,o) #define __io_aw() mmiowb_set_pending() #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiowb.h index 0b2333e71fdc..3bcae97d4803 100644 --- a/arch/riscv/include/asm/mmiowb.h +++ b/arch/riscv/include/asm/mmiowb.h @@ -7,7 +7,7 @@ * "o,w" is sufficient to ensure that all writes to the device have completed * before the write to the spinlock is allowed to commit. */ -#define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory"); +#define mmiowb() RISCV_FENCE(o,w) #include #include From patchwork Tue Feb 13 14:31:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 200446 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp575496dyb; Tue, 13 Feb 2024 06:31:28 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUn8aruiQZ4VZS6K69FwPTeTmSCe/roqnPJklKtTayudN1hHhnSOEtPRmP5GUjjwNSRyddMmdV3miMTzH8xicRAD2vY7w== X-Google-Smtp-Source: AGHT+IHaryFrGWapGQGKOZ8QkgGpFn+R/aW3iwR0kmKc8i2JmbHQhZjBOb9gA8lPn1IADfNcW3Ue X-Received: by 2002:a17:902:d547:b0:1db:40c1:c1fe with SMTP id z7-20020a170902d54700b001db40c1c1femr1382617plf.35.1707834687871; Tue, 13 Feb 2024 06:31:27 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707834687; cv=pass; d=google.com; s=arc-20160816; b=gr0yaGA43WDH8F2We9L3RWXnVhYoS7mXYFJs9Gv9nkQ3qWXz+IgEmYQU0v1G0HMmFl H02KSfVWLL0dPQQr9pU/AT07t0llZEM1eUI8GtXYrCYh1e9744G+hOCy7b8ZH11ynpuD wKkFTm5DmxWcJOTw+F1edySkgR6jT9NBsVb1auiK2a/RNSujd9/Dh2Bme7Gh+mCj48ci RcyvPggB9c0vfzakWx5Nmqhfx7/uPbWiL6F/+Kzzvl48Z5GK1XYvqDp3Grj5oFtTgPGt P5m+voHzTYZybjzwJyC1mCDdcnKA6KHn6tJyuNaULKSNcG79upGQ3lKmq8sI1UGMOoBr Q2xg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:from:subject:message-id:references:mime-version :list-unsubscribe:list-subscribe:list-id:precedence:in-reply-to:date :dkim-signature; bh=zzWDY0mBU7/wSOckVTmjGeC7uR6OHBXvGcRFd04Rqsk=; fh=Rm86AAWrY0Zie4eGxpjFJizjFORPv+UcSf6UvwRBz1c=; b=l3jzmrDJKglL4HcsBILwKMpyUSpMxHgV8rhkDkDOyJwv49ZwMCIoc0PuG1kNy21tVy pzl0gADFZNwXnZ+yitHEEkMtq49AbMj5tbFYpkUlL2qfwPEnIdcYErVLf6JQfw1zsbNV AMiI6RT45ivCMHs80w+MKWzk9e0EOlY5UO6eyAcUX1sz6BQ2rarXB8nwjUuzMDerAF2s wsMhMo1JM2tMDIGTEDeOgQL0sjLhykByuA/+ELl5seShGOT3f3nCrTS9k2yEj6Q/QkSK 9LOzd9MHjP8/2sM+T7wd/C6AeSAPBDg08+cwuZvyRmYQ6jlleGHDMGmq7q22LrJANIpl Y7Lg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=OrFyut31; arc=pass (i=1 spf=pass spfdomain=flex--ericchancf.bounces.google.com dkim=pass dkdomain=google.com dmarc=pass fromdomain=google.com); spf=pass (google.com: domain of linux-kernel+bounces-63681-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-63681-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com X-Forwarded-Encrypted: i=2; AJvYcCW6dEvJM3NaQRdMXj2suFqvYu7SDMOeqTzTzQantgxCm4xCX11ZV81nHB2FyqT2G8U8ht/0vEH1kEtViquCBiGSlodv4w== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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AJvYcCX9z5c6VJNolB6+eTZlg7AcuogxJMRywVa2bXq2vBwm39/UI/VV5yg4YeGQ9GA4pbveZcr4xR9ogDtED6G9K8xkWWy/i+E2MRStuYlc X-Gm-Message-State: AOJu0Yxhaqf05ut63D5oEU6LxMp1ug03gsefsYaURLBZDREu/NJxDBSN nSeRKpNPOjvQQ4Ya6wtsGwBJdVDplSMQAz0L3N5NTsFFN+Zaie7ZM2pijjAIl1erew1tAAjr1FR hDlnCnsKd3qmmQR4RRA== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:1027:b0:dc6:207c:dc93 with SMTP id x7-20020a056902102700b00dc6207cdc93mr345253ybt.2.1707834671075; Tue, 13 Feb 2024 06:31:11 -0800 (PST) Date: Tue, 13 Feb 2024 14:31:05 +0000 In-Reply-To: <20240213142632.2415127-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213142632.2415127-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213143105.2418044-1-ericchancf@google.com> Subject: [PATCH v3 4/4] riscv/barrier: Resolve checkpath.pl error From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790794465284013451 X-GMAIL-MSGID: 1790794465284013451 The original form would cause checkpath.pl to issue a error. The error message is as follows: ERROR: space required after that ',' (ctx:VxV) +#define __atomic_acquire_fence() RISCV_FENCE(r,rw) ^ correct the form of RISCV_FENCE and RISCV_FENCE_ASM even if they already exist. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 4 ++-- arch/riscv/include/asm/barrier.h | 18 +++++++++--------- arch/riscv/include/asm/fence.h | 6 +++--- arch/riscv/include/asm/io.h | 8 ++++---- arch/riscv/include/asm/mmio.h | 4 ++-- arch/riscv/include/asm/mmiowb.h | 2 +- 6 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 1b2ae3259f1d..19050d13b6c1 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -18,8 +18,8 @@ #include -#define __atomic_acquire_fence() RISCV_FENCE(r,rw) -#define __atomic_release_fence() RISCV_FENCE(rw,r) +#define __atomic_acquire_fence() RISCV_FENCE(r, rw) +#define __atomic_release_fence() RISCV_FENCE(rw, r) static __always_inline int arch_atomic_read(const atomic_t *v) { diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 4f4743d7440d..880b56d8480d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -19,19 +19,19 @@ /* These barriers need to enforce ordering on both devices or memory. */ -#define __mb() RISCV_FENCE(iorw,iorw) -#define __rmb() RISCV_FENCE(ir,ir) -#define __wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw, iorw) +#define __rmb() RISCV_FENCE(ir, ir) +#define __wmb() RISCV_FENCE(ow, ow) /* These barriers do not need to enforce ordering on devices, just memory. */ -#define __smp_mb() RISCV_FENCE(rw,rw) -#define __smp_rmb() RISCV_FENCE(r,r) -#define __smp_wmb() RISCV_FENCE(w,w) +#define __smp_mb() RISCV_FENCE(rw, rw) +#define __smp_rmb() RISCV_FENCE(r, r) +#define __smp_wmb() RISCV_FENCE(w, w) #define __smp_store_release(p, v) \ do { \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(rw,w); \ + RISCV_FENCE(rw, w); \ WRITE_ONCE(*p, v); \ } while (0) @@ -39,7 +39,7 @@ do { \ ({ \ typeof(*p) ___p1 = READ_ONCE(*p); \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(r,rw); \ + RISCV_FENCE(r, rw); \ ___p1; \ }) @@ -68,7 +68,7 @@ do { \ * instances the scheduler pairs this with an mb(), so nothing is necessary on * the new hart. */ -#define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw) +#define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw) #include diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index ca094d72ec20..5b46f96a3ec8 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -6,9 +6,9 @@ ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) #ifdef CONFIG_SMP -#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r,rw) -#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw,r) -#define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw,rw) +#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r, rw) +#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw, r) +#define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw, rw) #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index afb5ead7552e..1c5c641075d2 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -47,10 +47,10 @@ * sufficient to ensure this works sanely on controllers that support I/O * writes. */ -#define __io_pbr() RISCV_FENCE(io,i) -#define __io_par(v) RISCV_FENCE(i,ior) -#define __io_pbw() RISCV_FENCE(iow,o) -#define __io_paw() RISCV_FENCE(o,io) +#define __io_pbr() RISCV_FENCE(io, i) +#define __io_par(v) RISCV_FENCE(i, ior) +#define __io_pbw() RISCV_FENCE(iow, o) +#define __io_paw() RISCV_FENCE(o, io) /* * Accesses from a single hart to a single I/O address must be ordered. This diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index a708968d4a0f..06cadfd7a237 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -132,8 +132,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar(v) RISCV_FENCE(i,ir) -#define __io_bw() RISCV_FENCE(w,o) +#define __io_ar(v) RISCV_FENCE(i, ir) +#define __io_bw() RISCV_FENCE(w, o) #define __io_aw() mmiowb_set_pending() #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiowb.h index 3bcae97d4803..52ce4a399d9b 100644 --- a/arch/riscv/include/asm/mmiowb.h +++ b/arch/riscv/include/asm/mmiowb.h @@ -7,7 +7,7 @@ * "o,w" is sufficient to ensure that all writes to the device have completed * before the write to the spinlock is allowed to commit. */ -#define mmiowb() RISCV_FENCE(o,w) +#define mmiowb() RISCV_FENCE(o, w) #include #include