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Mon, 12 Feb 2024 15:36:32 -0800 (PST) From: Charlie Jenkins Date: Mon, 12 Feb 2024 15:36:26 -0800 Subject: [PATCH v11 1/4] riscv: Remove unnecessary irqflags processor.h include Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-fencei-v11-1-e1327f25fe10@rivosinc.com> References: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> In-Reply-To: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707780989; l=639; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=23qauOezLdGd/qvi+eoGfAUmo21GdLnF/O1XuhUSBhA=; b=3fk1hPn8uk0LHRB8yl3Y0RYndhVQhDbBlNi5Ce1BSrXXKhsMTW4JUlwl8LFpuZbLYzru9RLEH y8tsCF/wTQcAF+CZe6nMI0QqK6iZZlmz8RM55ve7LYSJeVzXo12jwfv X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790738200644492122 X-GMAIL-MSGID: 1790738200644492122 This include is not used. Remove it to avoid a circular dependency in the next patch in the series. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/irqflags.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 08d4d6a5b7e9..6fd8cbfcfcc7 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -7,7 +7,6 @@ #ifndef _ASM_RISCV_IRQFLAGS_H #define _ASM_RISCV_IRQFLAGS_H -#include #include /* read interrupt enabled status */ From patchwork Mon Feb 12 23:36:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 200105 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp226509dyb; Mon, 12 Feb 2024 15:37:52 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWOLARIR65jl3vAXhMseG9ghVK7kK7LyUcduZstHPxCyABwTmypijMEGahLXbFG9o4W6QtKV82w5t2QFw8DqqJPrwliEQ== X-Google-Smtp-Source: AGHT+IEKd+xFPWCJq4bINzl9vxmx55cdeQI3GSOiio+7rmLUJML6sDtWijCvRmmRkUEVHfkMJzzz X-Received: by 2002:a17:90a:db93:b0:297:fb7:fe1 with SMTP id h19-20020a17090adb9300b002970fb70fe1mr4550202pjv.46.1707781072406; Mon, 12 Feb 2024 15:37:52 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707781072; cv=pass; d=google.com; s=arc-20160816; b=asMPxpQmn7+Q2kymQ1kvRdMuuMEnu2j/cty55vuf8fFW+3rANNQeyys41oNlqNsRye uLpCw03PEiraN6F5zXDl4/LHqF/EuHJEFMjaYDTjpCkLYwHnTamYbvL61TQZ2KyJZx+a NDk1JPycI2onq3nfL4Ds0320MejAN2+RAcoCwUOp1XO4mBTXwNVSojTurVXeJmHOxbR9 V55d1ryvVF/gEUhL0q/f5vFvRyNMkMcgBeoqx3I+SmhN/TN35h8o1p9b+EMDhjhIopVW 9dHWVHgf4pGb2RLv+htk6mT2eTl2z9rymDimcf1J+CxL10x2NhlX6jTVEOTfQDOWxTE+ 0eeA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=dASIWM+uTiyyOMlmBksRTVw3Jl25BD2O8RxyTvNPqk4=; fh=jpTOO5YjNuS2WTWSsLX8EK3dDqtWdoOI67tHwMiTQNU=; b=ypsMM/8icI4W/mmXI2omB/So9cnBLU4ctelrHr+7nK7NjTJFjkmxsfdHpNeL9IUSiV bAbaebEmzVWm319VRGnr7HR/CqvB5RiXe3I6g556g91O3cGm1lKo2JUyIhTnihuCpUZV WtSlHA+QTV81g8FB6sEw862IvuKIwBVFehP1A+45ndMAQD0q22/y8tFvUKMWF7R33lLs syDY1IYcO3CoVWKqIDjUTS7L2GaMKrt6FQAnv1BxMaIj8c1vDmy6EzeAuHSdWNy3+z7g GaApiPCqjFc1upz8RND8wIMDIShnT69Hx6vhu9Y+eQsx0vqGW9vx4LA6JUg5/MkqmgD0 vgGg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=zqTUPyez; arc=pass (i=1 spf=pass spfdomain=rivosinc.com dkim=pass dkdomain=rivosinc-com.20230601.gappssmtp.com); spf=pass (google.com: domain of linux-kernel+bounces-62547-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62547-ouuuleilei=gmail.com@vger.kernel.org" X-Forwarded-Encrypted: i=2; AJvYcCVH+26oQFYziDLfmq/7X0exm6MxJovv0Aui8lbP6zLzZY9GPNtzWkRpvTxvjndjjnlIGIn5i5cF6CcuVUrLx2eZVQChbw== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Mon, 12 Feb 2024 15:36:33 -0800 (PST) From: Charlie Jenkins Date: Mon, 12 Feb 2024 15:36:27 -0800 Subject: [PATCH v11 2/4] riscv: Include riscv_set_icache_flush_ctx prctl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-fencei-v11-2-e1327f25fe10@rivosinc.com> References: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> In-Reply-To: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra , Alexandre Ghiti X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707780989; l=11568; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=TKCt+8IZ9ruFBnTgfJxRkDydxZvQ/nlPrN0EVMID0+A=; b=mXok/mb98DSDzfQSJsMFWzjeOw67T47xCMxZXKsQOL+eBtqj6VQDjbSmupvqXHeKGrQt9DCXz RTyTXGZNotGBvzga7ax/Xk2AcIKACM5dP0xS8ZpYk4cSQsMp40CZquV X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790738246188432858 X-GMAIL-MSGID: 1790738246188432858 Support new prctl with key PR_RISCV_SET_ICACHE_FLUSH_CTX to enable optimization of cross modifying code. This prctl enables userspace code to use icache flushing instructions such as fence.i with the guarantee that the icache will continue to be clean after thread migration. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/mmu.h | 2 + arch/riscv/include/asm/processor.h | 12 +++++ arch/riscv/include/asm/switch_to.h | 23 ++++++++ arch/riscv/mm/cacheflush.c | 105 +++++++++++++++++++++++++++++++++++++ arch/riscv/mm/context.c | 18 +++++-- include/uapi/linux/prctl.h | 6 +++ kernel/sys.c | 6 +++ 7 files changed, 167 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 355504b37f8e..60be458e94da 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -19,6 +19,8 @@ typedef struct { #ifdef CONFIG_SMP /* A local icache flush is needed before user execution can resume. */ cpumask_t icache_stale_mask; + /* Force local icache flush on all migrations. */ + bool force_icache_flush; #endif #ifdef CONFIG_BINFMT_ELF_FDPIC unsigned long exec_fdpic_loadmap; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index a8509cc31ab2..46c5c3b91165 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -69,6 +69,7 @@ #endif #ifndef __ASSEMBLY__ +#include struct task_struct; struct pt_regs; @@ -123,6 +124,14 @@ struct thread_struct { struct __riscv_v_ext_state vstate; unsigned long align_ctl; struct __riscv_v_ext_state kernel_vstate; +#ifdef CONFIG_SMP + /* A local icache flush is needed before user execution can resume on one of these cpus. */ + cpumask_t icache_stale_mask; + /* Regardless of the icache_stale_mask, flush the icache on migration */ + bool force_icache_flush; + /* A forced icache flush is not needed if migrating to the previous cpu. */ + unsigned int prev_cpu; +#endif }; /* Whitelist the fstate from the task_struct for hardened usercopy */ @@ -184,6 +193,9 @@ extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) +#define RISCV_SET_ICACHE_FLUSH_CTX(arg1, arg2) riscv_set_icache_flush_ctx(arg1, arg2) +extern int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per_thread); + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 7efdb0584d47..7594df37cc9f 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -72,14 +73,36 @@ static __always_inline bool has_fpu(void) { return false; } extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); +static inline bool switch_to_should_flush_icache(struct task_struct *task) +{ +#ifdef CONFIG_SMP + bool stale_mm = task->mm && task->mm->context.force_icache_flush; + bool stale_thread = task->thread.force_icache_flush; + bool thread_migrated = smp_processor_id() != task->thread.prev_cpu; + + return thread_migrated && (stale_mm || stale_thread); +#else + return false; +#endif +} + +#ifdef CONFIG_SMP +#define __set_prev_cpu(thread) ((thread).prev_cpu = smp_processor_id()) +#else +#define __set_prev_cpu(thread) +#endif + #define switch_to(prev, next, last) \ do { \ struct task_struct *__prev = (prev); \ struct task_struct *__next = (next); \ + __set_prev_cpu(__prev->thread); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ if (has_vector()) \ __switch_to_vector(__prev, __next); \ + if (switch_to_should_flush_icache(__next)) \ + local_flush_icache_all(); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 55a34f2020a8..6513a0ab8655 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -152,3 +153,107 @@ void __init riscv_init_cbo_blocksizes(void) if (cboz_block_size) riscv_cboz_block_size = cboz_block_size; } + +/** + * riscv_set_icache_flush_ctx() - Enable/disable icache flushing instructions in + * userspace. + * @ctx: Set the type of icache flushing instructions permitted/prohibited in + * userspace. Supported values described below. + * + * Supported values for ctx: + * + * * %PR_RISCV_CTX_SW_FENCEI_ON: Allow fence.i in user space. + * + * * %PR_RISCV_CTX_SW_FENCEI_OFF: Disallow fence.i in user space. All threads in + * a process will be affected when ``scope == PR_RISCV_SCOPE_PER_PROCESS``. + * Therefore, caution must be taken; use this flag only when you can guarantee + * that no thread in the process will emit fence.i from this point onward. + * + * @scope: Set scope of where icache flushing instructions are allowed to be + * emitted. Supported values described below. + * + * Supported values for scope: + * + * * %PR_RISCV_SCOPE_PER_PROCESS: Ensure the icache of any thread in this process + * is coherent with instruction storage upon + * migration. + * + * * %PR_RISCV_SCOPE_PER_THREAD: Ensure the icache of the current thread is + * coherent with instruction storage upon + * migration. + * + * When ``scope == PR_RISCV_SCOPE_PER_PROCESS``, all threads in the process are + * permitted to emit icache flushing instructions. Whenever any thread in the + * process is migrated, the corresponding hart's icache will be guaranteed to be + * consistent with instruction storage. This does not enforce any guarantees + * outside of migration. If a thread modifies an instruction that another thread + * may attempt to execute, the other thread must still emit an icache flushing + * instruction before attempting to execute the potentially modified + * instruction. This must be performed by the user-space program. + * + * In per-thread context (eg. ``scope == PR_RISCV_SCOPE_PER_THREAD``) only the + * thread calling this function is permitted to emit icache flushing + * instructions. When the thread is migrated, the corresponding hart's icache + * will be guaranteed to be consistent with instruction storage. + * + * On kernels configured without SMP, this function is a nop as migrations + * across harts will not occur. + */ +int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long scope) +{ +#ifdef CONFIG_SMP + switch (ctx) { + case PR_RISCV_CTX_SW_FENCEI_ON: + switch (scope) { + case PR_RISCV_SCOPE_PER_PROCESS: + current->mm->context.force_icache_flush = true; + break; + case PR_RISCV_SCOPE_PER_THREAD: + current->thread.force_icache_flush = true; + break; + default: + return -EINVAL; + } + break; + case PR_RISCV_CTX_SW_FENCEI_OFF: + cpumask_t *mask; + + switch (scope) { + case PR_RISCV_SCOPE_PER_PROCESS: + bool stale_cpu; + + current->mm->context.force_icache_flush = false; + + /* + * Mark every other hart's icache as needing a flush for + * this MM. Maintain the previous value of the current + * cpu to handle the case when this function is called + * concurrently on different harts. + */ + mask = ¤t->mm->context.icache_stale_mask; + stale_cpu = cpumask_test_cpu(smp_processor_id(), mask); + + cpumask_setall(mask); + assign_bit(cpumask_check(smp_processor_id()), cpumask_bits(mask), stale_cpu); + break; + case PR_RISCV_SCOPE_PER_THREAD: + current->thread.force_icache_flush = false; + + /* + * Mark every other hart's icache as needing a flush for + * this thread. + */ + mask = ¤t->thread.icache_stale_mask; + cpumask_setall(mask); + cpumask_clear_cpu(smp_processor_id(), mask); + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } +#endif + return 0; +} diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 217fd4de6134..2eb13b89cced 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -15,6 +15,7 @@ #include #include #include +#include #ifdef CONFIG_MMU @@ -297,21 +298,28 @@ static inline void set_mm(struct mm_struct *prev, * * The "cpu" argument must be the current local CPU number. */ -static inline void flush_icache_deferred(struct mm_struct *mm, unsigned int cpu) +static inline void flush_icache_deferred(struct mm_struct *mm, unsigned int cpu, + struct task_struct *task) { #ifdef CONFIG_SMP cpumask_t *mask = &mm->context.icache_stale_mask; - if (cpumask_test_cpu(cpu, mask)) { + if (cpumask_test_and_clear_cpu(cpu, mask) || + (task && cpumask_test_and_clear_cpu(cpu, &task->thread.icache_stale_mask))) { cpumask_clear_cpu(cpu, mask); + /* * Ensure the remote hart's writes are visible to this hart. * This pairs with a barrier in flush_icache_mm. */ smp_mb(); - local_flush_icache_all(); - } + /* + * If cache will be flushed in switch_to, no need to flush here. + */ + if (!(task && switch_to_should_flush_icache(task))) + local_flush_icache_all(); + } #endif } @@ -332,5 +340,5 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next, set_mm(prev, next, cpu); - flush_icache_deferred(next, cpu); + flush_icache_deferred(next, cpu, task); } diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 370ed14b1ae0..524d546d697b 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -306,4 +306,10 @@ struct prctl_mm_map { # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc # define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f +#define PR_RISCV_SET_ICACHE_FLUSH_CTX 71 +# define PR_RISCV_CTX_SW_FENCEI_ON 0 +# define PR_RISCV_CTX_SW_FENCEI_OFF 1 +# define PR_RISCV_SCOPE_PER_PROCESS 0 +# define PR_RISCV_SCOPE_PER_THREAD 1 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index e219fcfa112d..69afdd8b430f 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -146,6 +146,9 @@ #ifndef RISCV_V_GET_CONTROL # define RISCV_V_GET_CONTROL() (-EINVAL) #endif +#ifndef RISCV_SET_ICACHE_FLUSH_CTX +# define RISCV_SET_ICACHE_FLUSH_CTX(a, b) (-EINVAL) +#endif /* * this is where the system-wide overflow UID and GID are defined, for @@ -2743,6 +2746,9 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, case PR_RISCV_V_GET_CONTROL: error = RISCV_V_GET_CONTROL(); break; + case PR_RISCV_SET_ICACHE_FLUSH_CTX: + error = RISCV_SET_ICACHE_FLUSH_CTX(arg2, arg3); + break; default: error = -EINVAL; break; From patchwork Mon Feb 12 23:36:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 200103 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp226416dyb; Mon, 12 Feb 2024 15:37:38 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVDkR9v5p5IH7kwa/l98d2xmBfNcdM2E5Ymw+mZA2RbjcphnBEWFqBwtdSRNqjnPNMUXxqaGMoSNPyDHnNo2DO9JqZJxA== X-Google-Smtp-Source: AGHT+IFm9k6l9yCAZXKzL2r6y1pJZNtQfuUgEsN//ju2oE9AYU+wKsz5ia1QXJcO66eiQfvY1ERK X-Received: by 2002:a25:f621:0:b0:dc7:776b:5e4a with SMTP id t33-20020a25f621000000b00dc7776b5e4amr5032822ybd.56.1707781057831; Mon, 12 Feb 2024 15:37:37 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707781057; cv=pass; d=google.com; s=arc-20160816; b=sJejzyO3hPq8ai1sm25+bokE5/TlTpFEsRWQdMDm9ndq93gOLDNlm6oH9C9QiarNgu 27YO6xXQKfisUrfdQGkC4hsNmWZ6X0d7LvuIv+Jec+5mBAdve/6oYAHXdRtTgSG7VZKH 9OtwVtQbXMLFZG4CRqyIiHkp80xUe4eVHHOd6K77QgGlw10cxMXuXCst9S0IEg7S5NQ6 mViPDiOvaXfFYUTIr9ldREONWPpzOoPY6+fRCBDa1CeWISj2tTtKt2gbIL7ne4VcKPrb eK4O42A26t+BIxQlWIDYabZ4A0QGfwk4T5LRat2fmgkeO211vQhbo/z5mAJ8/MBfHjhp 5dJA== ARC-Message-Signature: i=2; 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Mon, 12 Feb 2024 15:36:34 -0800 (PST) From: Charlie Jenkins Date: Mon, 12 Feb 2024 15:36:28 -0800 Subject: [PATCH v11 3/4] documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-fencei-v11-3-e1327f25fe10@rivosinc.com> References: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> In-Reply-To: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra , Alexandre Ghiti X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707780989; l=4601; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=h5IjKPzf39ifTQj2Z0xAqATqlmjtpC61zariLMJKI0A=; b=vJDezW43wOShNn6FckmWv22EMLkCD0nM7x+UHVRHI3N8+Z+FmM5YXkveip/sA8wovq7Ws6bKO BP+ZSS/Sc9LDs5LKYhUoWvOeHEH9nKsMNE7+MESOdiw9PK7Yb73MHqV X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790738230598018894 X-GMAIL-MSGID: 1790738230598018894 Provide documentation that explains how to properly do CMODX in riscv. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra Reviewed-by: Alexandre Ghiti --- Documentation/arch/riscv/cmodx.rst | 98 ++++++++++++++++++++++++++++++++++++++ Documentation/arch/riscv/index.rst | 1 + 2 files changed, 99 insertions(+) diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/cmodx.rst new file mode 100644 index 000000000000..1c0ca06b6c97 --- /dev/null +++ b/Documentation/arch/riscv/cmodx.rst @@ -0,0 +1,98 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================================================================== +Concurrent Modification and Execution of Instructions (CMODX) for RISC-V Linux +============================================================================== + +CMODX is a programming technique where a program executes instructions that were +modified by the program itself. Instruction storage and the instruction cache +(icache) are not guaranteed to be synchronized on RISC-V hardware. Therefore, the +program must enforce its own synchronization with the unprivileged fence.i +instruction. + +However, the default Linux ABI prohibits the use of fence.i in userspace +applications. At any point the scheduler may migrate a task onto a new hart. If +migration occurs after the userspace synchronized the icache and instruction +storage with fence.i, the icache on the new hart will no longer be clean. This +is due to the behavior of fence.i only affecting the hart that it is called on. +Thus, the hart that the task has been migrated to may not have synchronized +instruction storage and icache. + +There are two ways to solve this problem: use the riscv_flush_icache() syscall, +or use the ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` prctl() and emit fence.i in +userspace. The syscall performs a one-off icache flushing operation. The prctl +changes the Linux ABI to allow userspace to emit icache flushing operations. + +As an aside, "deferred" icache flushes can sometimes be triggered in the kernel. +At the time of writing, this only occurs during the riscv_flush_icache() syscall +and when the kernel uses copy_to_user_page(). These deferred flushes happen only +when the memory map being used by a hart changes. If the prctl() context caused +an icache flush, this deferred icache flush will be skipped as it is redundant. +Therefore, there will be no additional flush when using the riscv_flush_icache() +syscall inside of the prctl() context. + +prctl() Interface +--------------------- + +Call prctl() with ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` as the first argument. The +remaining arguments will be delegated to the riscv_set_icache_flush_ctx +function detailed below. + +.. kernel-doc:: arch/riscv/mm/cacheflush.c + :identifiers: riscv_set_icache_flush_ctx + +Example usage: + +The following files are meant to be compiled and linked with each other. The +modify_instruction() function replaces an add with 0 with an add with one, +causing the instruction sequence in get_value() to change from returning a zero +to returning a one. + +cmodx.c:: + + #include + #include + + extern int get_value(); + extern void modify_instruction(); + + int main() + { + int value = get_value(); + printf("Value before cmodx: %d\n", value); + + // Call prctl before first fence.i is called inside modify_instruction + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX_ON, PR_RISCV_CTX_SW_FENCEI, PR_RISCV_SCOPE_PER_PROCESS); + modify_instruction(); + // Call prctl after final fence.i is called in process + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX_OFF, PR_RISCV_CTX_SW_FENCEI, PR_RISCV_SCOPE_PER_PROCESS); + + value = get_value(); + printf("Value after cmodx: %d\n", value); + return 0; + } + +cmodx.S:: + + .option norvc + + .text + .global modify_instruction + modify_instruction: + lw a0, new_insn + lui a5,%hi(old_insn) + sw a0,%lo(old_insn)(a5) + fence.i + ret + + .section modifiable, "awx" + .global get_value + get_value: + li a0, 0 + old_insn: + addi a0, a0, 0 + ret + + .data + new_insn: + addi a0, a0, 1 diff --git a/Documentation/arch/riscv/index.rst b/Documentation/arch/riscv/index.rst index 4dab0cb4b900..eecf347ce849 100644 --- a/Documentation/arch/riscv/index.rst +++ b/Documentation/arch/riscv/index.rst @@ -13,6 +13,7 @@ RISC-V architecture patch-acceptance uabi vector + cmodx features From patchwork Mon Feb 12 23:36:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 200104 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp226467dyb; Mon, 12 Feb 2024 15:37:45 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXp4J91CvfshwUt454+PXgtLtsgI9JaE9rBksD9YPGVaYv9DGASaRmhnrxJF1MOn7MSlS1uYIEeAIIpjnknx4mOd0zl5A== X-Google-Smtp-Source: AGHT+IFguNdfjrSUYSHSD+dX44SZKb2zuZZSw/2FXDIzLiMGHFomM2jkSb9rME++ZuxBARfgHKBP X-Received: by 2002:a17:90b:80b:b0:296:24cf:bae6 with SMTP id bk11-20020a17090b080b00b0029624cfbae6mr5342039pjb.27.1707781065030; Mon, 12 Feb 2024 15:37:45 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707781065; cv=pass; d=google.com; s=arc-20160816; b=ZgCBe/PEWYox5niWDiF+ei+RX5xHc+M4do9w+u/mh4o/e0g0iaqsnBDfusrveT5H4D f1vKmn+UfNVmZvN2UAS/0lhMvjcvAyC4/hV+gED3z3VLT1vEnkWougnpRUJVTExjN1F7 OwpYx2475cpXyAY1WVPXHOHBJ+D/KLh+HjZ1nTYzIshkLblU1Ufsgi7ia5iipOA9pdrZ Rh004epWZ8DMScK8GPVck9afo9JTjlqgHJRVk2wa6tO1WGPt/vWLZLoZX8n72DOTduTu a8u0Jw4P70SZfdVX2O4ZT3L8Yj2iQh1d8xHcN7BJ/OSDff6OpLXORkGQ3nvP7+2GRgiR xj2A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=XqFsnYbayaROauH/yeBk3F9rNPdoEfeRLt6dO0Xr65g=; fh=VnkfFlDUf4L0mHUM/l5kf13vBYEFOhsIBn+momHUDQE=; b=MB1/QzdUQ5LM5kI/yqtoadkfq6E7S2qARwf+AOKKgb2NBypyDxajzxi32xXBDkl1nz 5ZIQxFULIeT+UWgCG2qunNIRT34a3DenUzWwMtYPOnHloGzo2wbnWXwGfr3fvo/2ldgr KPjmkfYm9N+S3T/RMlFjB0rZOhPTK3/fyEGt6xX10Miy3yEc9GUmtHH1ztURnUn3CHSI OlRHJTLoCCsGpa6UcNDEoeCfTMujiipAdSBl81STvyLcDwCArek3V5m0n266N4RaFXCk dQEWHuhiLnZ/ynpNq35lk39REWTHXXAtBmvArAHgWKgseYMq4rbLApZH3thLmj9aTF42 FthQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=Q35k1rqB; arc=pass (i=1 spf=pass spfdomain=rivosinc.com dkim=pass dkdomain=rivosinc-com.20230601.gappssmtp.com); spf=pass (google.com: domain of linux-kernel+bounces-62546-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62546-ouuuleilei=gmail.com@vger.kernel.org" X-Forwarded-Encrypted: i=2; AJvYcCUkgIQoGu3F2RNYhkwyfsAbJ+6W5rqG6a8rZksf50Ztuv8aswl+bVISLthcfUYgyKqz1Yq0PjhzLQtid80CylJdididNw== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Mon, 12 Feb 2024 15:36:36 -0800 (PST) From: Charlie Jenkins Date: Mon, 12 Feb 2024 15:36:29 -0800 Subject: [PATCH v11 4/4] cpumask: Add assign cpu Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-fencei-v11-4-e1327f25fe10@rivosinc.com> References: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> In-Reply-To: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707780989; l=1797; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=teNltxEe5ATnvQPKeLgPp6b3k0t1rOkLmnDUUB6OJdA=; b=EiKlcL1ulk4DvUiCSUgvbFtR389U08UGs9J+Mx1NjicMNyA7ytjbg4bgirWaWZZtdE5HGgwHU EVUxZnpx4C/A+JHiRo45OTnP3oYSGtoMtT2ZFchA7WKDMysLkz7sWPx X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790738238090472910 X-GMAIL-MSGID: 1790738238090472910 Standardize an assign_cpu function for cpumasks. Signed-off-by: Charlie Jenkins --- arch/riscv/mm/cacheflush.c | 2 +- include/linux/cpumask.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6513a0ab8655..d10c2cba8aff 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -234,7 +234,7 @@ int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long scope) stale_cpu = cpumask_test_cpu(smp_processor_id(), mask); cpumask_setall(mask); - assign_bit(cpumask_check(smp_processor_id()), cpumask_bits(mask), stale_cpu); + cpumask_assign_cpu(smp_processor_id(), mask, stale_cpu); break; case PR_RISCV_SCOPE_PER_THREAD: current->thread.force_icache_flush = false; diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h index cfb545841a2c..1b85e09c4ba5 100644 --- a/include/linux/cpumask.h +++ b/include/linux/cpumask.h @@ -492,6 +492,22 @@ static __always_inline void __cpumask_clear_cpu(int cpu, struct cpumask *dstp) __clear_bit(cpumask_check(cpu), cpumask_bits(dstp)); } +/** + * cpumask_assign_cpu - assign a cpu in a cpumask + * @cpu: cpu number (< nr_cpu_ids) + * @dstp: the cpumask pointer + * @bool: the value to assign + */ +static __always_inline void cpumask_assign_cpu(int cpu, struct cpumask *dstp, bool value) +{ + assign_bit(cpumask_check(cpu), cpumask_bits(dstp), value); +} + +static __always_inline void __cpumask_assign_cpu(int cpu, struct cpumask *dstp, bool value) +{ + __assign_bit(cpumask_check(cpu), cpumask_bits(dstp), value); +} + /** * cpumask_test_cpu - test for a cpu in a cpumask * @cpu: cpu number (< nr_cpu_ids)