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Signed-off-by: Christophe Kerello --- .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 14f1833d37c9..12e6afeceffd 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -23,7 +23,9 @@ maintainers: properties: compatible: - const: st,stm32mp1-fmc2-ebi + enum: + - st,stm32mp1-fmc2-ebi + - st,stm32mp25-fmc2-ebi reg: maxItems: 1 From patchwork Mon Feb 12 17:48:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Kerello X-Patchwork-Id: 199961 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp73001dyb; Mon, 12 Feb 2024 09:52:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IEjP9ETFLIKMwDo+PA+O2DQSIJRoJiuYea4A9BdsYCHmF+wWhGYawu9B7nEDbdq3FZ9Q84d X-Received: by 2002:aa7:ce12:0:b0:561:d726:201 with SMTP id d18-20020aa7ce12000000b00561d7260201mr1075924edv.10.1707760323044; Mon, 12 Feb 2024 09:52:03 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707760323; cv=pass; d=google.com; s=arc-20160816; b=id+hvODluQpyfKVX/xNZi9dZ7tlYKYWj9Wq60tEXz74LKKNUZ1I1eG/QsQ+mAOn/xG D5nfaLbB/dx9ZF3nqCym86R5XeIBRLj2d0JIyEkYIIxJ2CYmUfA7JrG4shKR/tKybzOG ZDVwNFqMv+YxuO6CsoFb/MGFxHacKYdoQuf1hvjRsTlrrDdXblF96apUvyLz2sZxCcoT C7bmcGuSyXkSYYgKLeoVAlYXoA077pizibntOsZTmWYPAvmMM6fiXpJvqD0LZ772xRWh 8uMXcR/AGEQkdfmtHLjmXf7pc3VDpQiRiywz/WcM7CNXg/TNKHT/M0MDz5tWdhKGWX2Y LGGg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=X5FzM+bKH9CfiJVb/5vMppNol/5mtkgXoVYxjRsJvyc=; fh=612RSkYqV/jrmiA59josNZZtyuFHCi2dx3pBmzAsmBM=; b=0SDuZq6pegLxdySZqOC2Yy8/ACHqeykbp+lrqZSQE/xcE5n0HGdNh2ekEmqDpk5tBY Tf102p7b0n1AYJQ0Fuy/xMvnfo2rDeoyPAc/lQWoQy8zkE/x6sQ2f6fFpWWD2DISdYMG 9IRRZ9UhJOrzV1tUUomkSxQfIZ6HVNmtgBFbkmeVjnAA2/jM01fUaP6tHHH88Yx4C7Zb wfutta65BNIKNPE5avpsV9nksAl8+C57K3V78bvjnyMFrA8LnXaB/V2tSr8x4Fk0wVI0 ekgStf/TzW5JFCVzhNzSuRR2x3cEV5ZqA/WXV0G87uGH1YPYJAfmLbeWM73r4tGC5kVb fCwA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b="z2/7CTCJ"; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-62134-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62134-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com X-Forwarded-Encrypted: i=2; AJvYcCVIQN28WH3T8Y4l0m6WiagitY4W+NFECi+hhYzYAjjPAeywaPketCLxF9BwpU39fIih7sZiv/ZE0wrHITSu3a3HSxqcuA== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Mon, 12 Feb 2024 18:50:08 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 66E49275757; Mon, 12 Feb 2024 18:49:07 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:49:07 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Patrick Delaunay , Christophe Kerello Subject: [PATCH 02/12] dt-bindings: memory-controller: st,stm32: add 'power-domains' property Date: Mon, 12 Feb 2024 18:48:12 +0100 Message-ID: <20240212174822.77734-3-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790716488228578763 X-GMAIL-MSGID: 1790716488228578763 From: Patrick Delaunay On STM32MP25 SOC, STM32 FMC2 memory controller is in a power domain. Allow a single 'power-domains' entry for STM32 FMC2. Signed-off-by: Patrick Delaunay Signed-off-by: Christophe Kerello --- .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 12e6afeceffd..84ac6f50a6fc 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -36,6 +36,9 @@ properties: resets: maxItems: 1 + power-domains: + maxItems: 1 + "#address-cells": const: 2 From patchwork Mon Feb 12 17:48:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Kerello X-Patchwork-Id: 199962 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp73015dyb; Mon, 12 Feb 2024 09:52:05 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVAB7+h5WuJ+or6QjVJIx9B/GjZKqH39q3iahPrqwUIBrhwF5WBLY7kzTj4/jtAvqTfkilgfqqJ9HEMCV9eey1rnQbqQw== X-Google-Smtp-Source: AGHT+IFLGxdxeyUkWPcmFmLZJuBU4Z/UPidDh6YdMDWgIw5h5+6jn+KAvyOZq6GDinxsiRgNTAXn X-Received: by 2002:a0c:e393:0:b0:68c:aa25:c0ce with SMTP id a19-20020a0ce393000000b0068caa25c0cemr7219989qvl.30.1707760325711; Mon, 12 Feb 2024 09:52:05 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707760325; cv=pass; d=google.com; s=arc-20160816; b=cdqc4eptfi6Kohuhc+97X9QgVnvLdH+boupVkiUxkvD37gaybxpO6gQNtOjojWBq4t fQoT4xv6dAkquegW1EHGpMb0nICWFmnSYn/N0+/oxvVR886dBOHbbcIt9Vb2pT3+Jo6n k4guPMxwKpgg5YEOO1OsuKFNvBAlu3sdqaIVhpP7vTZIVIwP93dZ28N6bN/CUSs6iF9O I+RYcbL+6ljw0qPRl48pe+PzcOjuhPEkaFpL5Fqk5s93Oi7aVl7UBgdPGcCVyquZrHl3 /QfBAAw3GaTj+almxJddqlzsaZyYixcoryyrW7q9SRey/UKrSeLZQLgjEmE0F8wbGYgy rWmQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=OFS/WeJd4jRcMqQNxQdciKfLU7r6D+lgxuZRfC3hr4E=; fh=TOUmD+tY//E4gzGrUcqfchV5B1bl/7DM/GdzoQnZkPg=; b=QAamd4c3y4Aijcs9cZiipA0HIG3O6X4h2VFRQtgfUofZcJEDwXmeNcSCXLT+U1sNe6 oa8pQ5ppENKcljoUCry3d6fPDqUlLG6gYzMEXvGsFmODD+w98mpXrttFfPjxT6yR+EEH i4vykVwpOKIZzhS+UjR5BiHeTgi6NjI1S9OUF4l4UkVbmpnBcCGVgapbSWgq6TMReb1H hGfd8TWTpBaa4ncHIdgtgd7T0CadL8fyYXPjh7MBAxyyCsaHJ59zkrZ0uSSgt+r99Ayy q3ZfXr7gGAV6FgoadvnFp+AUOzCll/jqlxeYN9xAxdwvYrVdQe95cb3AGfWF+rEa7IHh POxQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=mqEayElp; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-62135-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62135-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com X-Forwarded-Encrypted: i=2; AJvYcCW5wyQNSjzaNRL5N/d3vpQTFTrDVhebJJZqKlqJL6lM8/bw4SHOMvt97fl1bUp7vALNX3l1+jYKrVDMuwCg+BlJ5MmuNQ== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Mon, 12 Feb 2024 18:50:11 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1CB1627F260; Mon, 12 Feb 2024 18:49:22 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:49:21 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 03/12] memory: stm32-fmc2-ebi: add a platform data structure Date: Mon, 12 Feb 2024 18:48:13 +0100 Message-ID: <20240212174822.77734-4-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790716491505440128 X-GMAIL-MSGID: 1790716491505440128 Before the introduction of MP25 support, let's use a platform data structure for parameters that will differ. The MP1 SOCs have only one signal to manage all the controllers (NWAIT). The MP25 SOC has one RNB signal for the NAND controller and one NWAIT signal for the memory controller. Signed-off-by: Christophe Kerello --- drivers/memory/stm32-fmc2-ebi.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index 47d0ea5f1616..5f82686689ee 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -132,10 +132,15 @@ enum stm32_fmc2_ebi_cpsize { FMC2_CPSIZE_1024 = 1024 }; +struct stm32_fmc2_ebi_data { + bool rnb_for_nand; +}; + struct stm32_fmc2_ebi { struct device *dev; struct clk *clk; struct regmap *regmap; + const struct stm32_fmc2_ebi_data *data; u8 bank_assigned; u32 bcr[FMC2_MAX_EBI_CE]; @@ -988,6 +993,9 @@ static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) unsigned int cs; u32 bcr; + if (ebi->data->rnb_for_nand) + return false; + for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { if (!(ebi->bank_assigned & BIT(cs))) continue; @@ -1108,6 +1116,10 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev) ebi->dev = dev; + ebi->data = of_device_get_match_data(dev); + if (!ebi->data) + return -EINVAL; + ebi->regmap = device_node_to_regmap(dev->of_node); if (IS_ERR(ebi->regmap)) return PTR_ERR(ebi->regmap); @@ -1187,8 +1199,15 @@ static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend, stm32_fmc2_ebi_resume); +static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp1_data = { + .rnb_for_nand = false, +}; + static const struct of_device_id stm32_fmc2_ebi_match[] = { - {.compatible = "st,stm32mp1-fmc2-ebi"}, + { + .compatible = "st,stm32mp1-fmc2-ebi", + .data = &stm32_fmc2_ebi_mp1_data, + }, {} }; MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match); From patchwork Mon Feb 12 17:48:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Kerello X-Patchwork-Id: 199960 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp72766dyb; Mon, 12 Feb 2024 09:51:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IE2kfNzLNnRawzAC3A7QieuWrJwvJMOg4kpIDYbUVz8qpeZ1JvDrVJsq3IEk6Jo4sNmZbrU X-Received: by 2002:a17:906:492:b0:a38:63d4:2273 with SMTP id f18-20020a170906049200b00a3863d42273mr4870259eja.35.1707760294510; Mon, 12 Feb 2024 09:51:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707760294; cv=pass; d=google.com; s=arc-20160816; b=UOaplDPk3TGrsB716yQSv6oaotjlwf9nhH6bowCVbKpetbdHSkje3t1qBVAZuslJRD y1wEyJ3tuYF3l/ZonK25jm9qbeVw9hkLBWDlSfjsGcSY8IX3+w4/mq0CZpXuFz2tDcDf 7gAOIqK7KobWqUsCKHaaFZ1jUeGJQV//yX8tHKFXxoz+Nt/G3x5oWv7cNPe2z82mDiR6 FC+H5KGgub0OGZpzGT0MpzLWgqmaztjdfMhzGd2AEVN7keMs682qYqEtO87WrwCAav2j KwUkGhVuxxoKbJ8swoIEH/dWfELwDZv2apQTl8k8yfhgyBJNlH515XCbGBzMxN17FnyP cXjA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=r6RWTYufSQBKqRLetLHxbThC+14OuOlj1dpd6iOn9yk=; fh=neWx6BX66A8A1/66AcG6Gs0dhLz8kIQ9SVITmAf2wEw=; b=DdT8NSqHm4ICt7U7sNhZUIxut/+/jFvjGHNVaD2tcVSkTBOdUKRpALU83ouAG1O3Vs Eg+dolUgtACGIXO5tM0oLUELhpM+eVqcODNMbbdy2bnMFwkM+78FYA/9eeS0f95BviH/ OkOXffGtEMf0nFfTehaGqNhso1PNUIMG75JbrdgbxoSoG+ASWh6xRy2MJXZKintSDynm 8blmOI5k8YBxilFKfaNC0sGzNtYlj6FQsdFT+zQJRTVYklIN6+MiGgQUyShnHFrZ/P+H yGjFVQD3BVgeFSR3CZeULh0D85TdbWtOfQLtaMIHbh8lHobl+YowqLggz21IHK4nJU5X 0I5A==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=see1PXtW; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-62132-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62132-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com X-Forwarded-Encrypted: i=2; AJvYcCV6XeXHkExOQbRqcnGAn3L41METl4ec1QQYJhbVRCD+d4Dl54vyZxnrdt+/92io7EqhZ8acvGI2Eq90kF2AYxTehqoTzA== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Mon, 12 Feb 2024 18:50:19 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 51D0B27F265; Mon, 12 Feb 2024 18:49:37 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:49:37 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 04/12] memory: stm32-fmc2-ebi: add MP25 support Date: Mon, 12 Feb 2024 18:48:14 +0100 Message-ID: <20240212174822.77734-5-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790716458480822685 X-GMAIL-MSGID: 1790716458480822685 Add MP25 SOC support. RNB and NWAIT signals are differentiated. Signed-off-by: Christophe Kerello --- drivers/memory/stm32-fmc2-ebi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index 5f82686689ee..d79dcb6c239a 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -1203,11 +1203,19 @@ static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp1_data = { .rnb_for_nand = false, }; +static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp25_data = { + .rnb_for_nand = true, +}; + static const struct of_device_id stm32_fmc2_ebi_match[] = { { .compatible = "st,stm32mp1-fmc2-ebi", .data = &stm32_fmc2_ebi_mp1_data, }, + { + .compatible = "st,stm32mp25-fmc2-ebi", + .data = &stm32_fmc2_ebi_mp25_data, + }, {} }; MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match); From patchwork Mon Feb 12 17:48:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Kerello X-Patchwork-Id: 199976 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp91011dyb; Mon, 12 Feb 2024 10:20:45 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUr3aDJ02AKhsjAYQl/XcLX1KVe40dCzl767wTXRMHEbsLlPRDmsz0NFjU5skNSW/PFHSryavshwDiwXTCv370kWM84mA== X-Google-Smtp-Source: AGHT+IFzJnjhxXngavb7kf6h7OcTKVkQczbpWeMLZwiBhpa59Wzl22T61feu4KtwaCCb7cRMmWa2 X-Received: by 2002:aa7:808e:0:b0:6e0:8d87:290d with SMTP id v14-20020aa7808e000000b006e08d87290dmr5540011pff.11.1707762044941; Mon, 12 Feb 2024 10:20:44 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707762044; cv=pass; d=google.com; s=arc-20160816; b=Aa+dOJsSBZVjWoEpl5KG53Cr/xb2oNaHHEe+INIkz1HqsSajXyDlxcziBbJgFvzOZL 4WzMfukqZoFSeSHy/+G24BrAAvhK/RwDsvfNFKpEhFrqq/sDX7oarCY2EInC6nlRjujv DBCN23Kz2+9cKi+rF7fLg6NnTQcFNyPNDZcJ3tzVEsvUqCCImpQYlQI2z7tTun6a3u6i eg4DL5kBIqfvR4Jjk3sF3WGFaHYi+sPKEPDTjnupHEXr1ZY4QNByQzf5hi+zsQxWnPbP ysjCsyIWIDBYHh69gJMjy/NuviGG50ljcLHJr5/Bapsh6xq1rjumCgd1QGnfv+Vmv7Dz rcfA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Z0aItHEQT/Gc8o+rIaDNT6jpPrbSuTRgt5neklE4F6w=; fh=nUl663xG+aA/vETn4/Pg2ZX9w54K8H9Y3mludP7PFZ4=; b=G+p/qJIHU8phZPiwb508QgzNjhkAHvhHc6OCnw9OIGSOZ1txwxxh4eXznItqML4PCV ubXM8N3+Wj+eZvQMOJX8OPwfWXuNFbZJmSlUakNzuF5Sjv7uQcrKRpnOMsVWLepUQ0Pg U+56D4KDLvvMZ302b67QaZ3pZceOZgy4Hp2UhpOSMkBumc4cB8MfTQ5AqvvwHdpRUDAp aLE8+S3YaWOMQCH2A6JxVBR7Bbi+5d9BH4GZ4qgF3ifpZ3A7Vke+V6P9h/OX9KfV4sR+ Rdo4UlCPZSth3PIC/GMvan2Gh9pLWt52bgiRsQjaVJhq7oPCmHLskabOIUGdx/EdVEvK sStA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=8N5fGBp9; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-62136-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62136-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com X-Forwarded-Encrypted: i=2; AJvYcCVOLHu5lKF/Z0MpUN4pSeCVhFXpYu5a5/jD2pw4xE9dEBMu9b/rUHZb4SXH29HgFFV5EHpRmDr5OOeaJ1z4pnDfcYkoDg== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Mon, 12 Feb 2024 18:50:35 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id F0BDE27F268; Mon, 12 Feb 2024 18:49:51 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:49:51 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 05/12] memory: stm32-fmc2-ebi: update the driver to support revision 2 Date: Mon, 12 Feb 2024 18:48:15 +0100 Message-ID: <20240212174822.77734-6-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790718293844033217 X-GMAIL-MSGID: 1790718293844033217 Add the support of the revision 2 of FMC2 IP. - PCSCNTR register has been removed, - CFGR register has been added, - the bit used to enable the IP has moved from BCR1 to CFGR, - the timeout for CEx deassertion has moved from PCSCNTR to BCRx, - the continuous clock enable has moved from BCR1 to CFGR, - the clk divide ratio has moved from BCR1 to CFGR. Signed-off-by: Christophe Kerello --- drivers/memory/stm32-fmc2-ebi.c | 206 +++++++++++++++++++++++++------- 1 file changed, 163 insertions(+), 43 deletions(-) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index d79dcb6c239a..066722274a45 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -20,8 +20,10 @@ #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1) #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) #define FMC2_PCSCNTR 0x20 +#define FMC2_CFGR 0x20 #define FMC2_BWTR1 0x104 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) +#define FMC2_VERR 0x3f4 /* Register: FMC2_BCR1 */ #define FMC2_BCR1_CCLKEN BIT(20) @@ -42,6 +44,7 @@ #define FMC2_BCR_ASYNCWAIT BIT(15) #define FMC2_BCR_CPSIZE GENMASK(18, 16) #define FMC2_BCR_CBURSTRW BIT(19) +#define FMC2_BCR_CSCOUNT GENMASK(21, 20) #define FMC2_BCR_NBLSET GENMASK(23, 22) /* Register: FMC2_BTRx/FMC2_BWTRx */ @@ -58,6 +61,15 @@ #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0) #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16) +/* Register: FMC2_CFGR */ +#define FMC2_CFGR_CLKDIV GENMASK(19, 16) +#define FMC2_CFGR_CCLKEN BIT(20) +#define FMC2_CFGR_FMC2EN BIT(31) + +/* Register: FMC2_VERR */ +#define FMC2_VERR_MAJREV GENMASK(7, 4) +#define FMC2_VERR_MAJREV_2 2 + #define FMC2_MAX_EBI_CE 4 #define FMC2_MAX_BANKS 5 @@ -74,6 +86,11 @@ #define FMC2_BCR_MTYP_PSRAM 0x1 #define FMC2_BCR_MTYP_NOR 0x2 +#define FMC2_BCR_CSCOUNT_0 0x0 +#define FMC2_BCR_CSCOUNT_1 0x1 +#define FMC2_BCR_CSCOUNT_64 0x2 +#define FMC2_BCR_CSCOUNT_256 0x3 + #define FMC2_BXTR_EXTMOD_A 0x0 #define FMC2_BXTR_EXTMOD_B 0x1 #define FMC2_BXTR_EXTMOD_C 0x2 @@ -85,7 +102,7 @@ #define FMC2_BXTR_DATAST_MAX 0xff #define FMC2_BXTR_BUSTURN_MAX 0xf #define FMC2_BXTR_DATAHLD_MAX 0x3 -#define FMC2_BTR_CLKDIV_MAX 0xf +#define FMC2_REG_CLKDIV_MAX 0xf #define FMC2_BTR_DATLAT_MAX 0xf #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff @@ -101,7 +118,8 @@ enum stm32_fmc2_ebi_register_type { FMC2_REG_BCR = 1, FMC2_REG_BTR, FMC2_REG_BWTR, - FMC2_REG_PCSCNTR + FMC2_REG_PCSCNTR, + FMC2_REG_CFGR, }; enum stm32_fmc2_ebi_transaction_type { @@ -132,6 +150,13 @@ enum stm32_fmc2_ebi_cpsize { FMC2_CPSIZE_1024 = 1024 }; +enum stm32_fmc2_ebi_cscount { + FMC2_CSCOUNT_0 = 0, + FMC2_CSCOUNT_1 = 1, + FMC2_CSCOUNT_64 = 64, + FMC2_CSCOUNT_256 = 256 +}; + struct stm32_fmc2_ebi_data { bool rnb_for_nand; }; @@ -142,11 +167,13 @@ struct stm32_fmc2_ebi { struct regmap *regmap; const struct stm32_fmc2_ebi_data *data; u8 bank_assigned; + u8 majrev; u32 bcr[FMC2_MAX_EBI_CE]; u32 btr[FMC2_MAX_EBI_CE]; u32 bwtr[FMC2_MAX_EBI_CE]; u32 pcscntr; + u32 cfgr; }; /* @@ -274,15 +301,29 @@ static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi, const struct stm32_fmc2_prop *prop, int cs) { - u32 bcr, bcr1; + u32 bcr, cfgr; regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); - if (cs) - regmap_read(ebi->regmap, FMC2_BCR1, &bcr1); - else - bcr1 = bcr; - if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN))) + if (ebi->majrev < FMC2_VERR_MAJREV_2) { + u32 bcr1; + + if (cs) + regmap_read(ebi->regmap, FMC2_BCR1, &bcr1); + else + bcr1 = bcr; + + if (bcr & FMC2_BCR_BURSTEN && + (!cs || !(bcr1 & FMC2_BCR1_CCLKEN))) + return 0; + + return -EINVAL; + } + + regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); + + if (bcr & FMC2_BCR_BURSTEN && + (!cs || !(cfgr & FMC2_CFGR_CCLKEN))) return 0; return -EINVAL; @@ -311,15 +352,29 @@ static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi, int cs, u32 setup) { u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup); - u32 bcr, btr, clk_period; + u32 btr, clk_period; - regmap_read(ebi->regmap, FMC2_BCR1, &bcr); - if (bcr & FMC2_BCR1_CCLKEN || !cs) - regmap_read(ebi->regmap, FMC2_BTR1, &btr); - else - regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); + if (ebi->majrev < FMC2_VERR_MAJREV_2) { + u32 bcr; - clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; + regmap_read(ebi->regmap, FMC2_BCR1, &bcr); + if (bcr & FMC2_BCR1_CCLKEN || !cs) + regmap_read(ebi->regmap, FMC2_BTR1, &btr); + else + regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); + + clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; + } else { + u32 cfgr; + + regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); + if (cfgr & FMC2_CFGR_CCLKEN) { + clk_period = FIELD_GET(FMC2_CFGR_CLKDIV, cfgr) + 1; + } else { + regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); + clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; + } + } return DIV_ROUND_UP(nb_clk_cycles, clk_period); } @@ -339,6 +394,9 @@ static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg) case FMC2_REG_PCSCNTR: *reg = FMC2_PCSCNTR; break; + case FMC2_REG_CFGR: + *reg = FMC2_CFGR; + break; default: return -EINVAL; } @@ -672,10 +730,26 @@ static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi, int cs, u32 setup) { u32 val; + u32 reg = FMC2_BTR(cs); + u32 mask = FMC2_BTR_CLKDIV; - val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1; - val = FIELD_PREP(FMC2_BTR_CLKDIV, val); - regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val); + if (ebi->majrev >= FMC2_VERR_MAJREV_2) { + u32 cfgr; + + regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); + + if (cfgr & FMC2_CFGR_CCLKEN) { + reg = FMC2_CFGR; + mask = FMC2_CFGR_CLKDIV; + } + } + + val = setup ? clamp_val(setup - 1, 1, FMC2_REG_CLKDIV_MAX) : 1; + if (reg == FMC2_CFGR) + val = FIELD_PREP(FMC2_CFGR_CLKDIV, val); + else + val = FIELD_PREP(FMC2_BTR_CLKDIV, val); + regmap_update_bits(ebi->regmap, reg, mask, val); return 0; } @@ -697,27 +771,58 @@ static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi, const struct stm32_fmc2_prop *prop, int cs, u32 setup) { - u32 old_val, new_val, pcscntr; + u32 val; + u32 reg = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_PCSCNTR : + FMC2_BCR(cs); + u32 mask = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_PCSCNTR_CSCOUNT : + FMC2_BCR_CSCOUNT; - if (setup < 1) - return 0; + if (ebi->majrev < FMC2_VERR_MAJREV_2) { + u32 old_val, pcscntr; - regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr); + if (setup < 1) + return 0; - /* Enable counter for the bank */ - regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, - FMC2_PCSCNTR_CNTBEN(cs), - FMC2_PCSCNTR_CNTBEN(cs)); + regmap_read(ebi->regmap, reg, &pcscntr); - new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX); - old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr); - if (old_val && new_val > old_val) - /* Keep current counter value */ - return 0; + /* Enable counter for the bank */ + regmap_update_bits(ebi->regmap, reg, + FMC2_PCSCNTR_CNTBEN(cs), + FMC2_PCSCNTR_CNTBEN(cs)); + + val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX); + old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr); + if (old_val && val > old_val) + /* Keep current counter value */ + return 0; + + val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, val); + } else { + if (setup == FMC2_CSCOUNT_0) + val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_0); + else if (setup == FMC2_CSCOUNT_1) + val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_1); + else if (setup <= FMC2_CSCOUNT_64) + val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_64); + else + val = FIELD_PREP(FMC2_BCR_CSCOUNT, + FMC2_BCR_CSCOUNT_256); + } + + regmap_update_bits(ebi->regmap, reg, mask, val); - new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val); - regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, - FMC2_PCSCNTR_CSCOUNT, new_val); + return 0; +} + +static int stm32_fmc2_ebi_set_cclk(struct stm32_fmc2_ebi *ebi, + const struct stm32_fmc2_prop *prop, + int cs, u32 setup) +{ + u32 reg = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1 : FMC2_CFGR; + u32 mask = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1_CCLKEN : + FMC2_CFGR_CCLKEN; + + regmap_update_bits(ebi->regmap, reg, mask, setup ? mask : 0); return 0; } @@ -732,10 +837,8 @@ static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = { { .name = "st,fmc2-ebi-cs-cclk-enable", .bprop = true, - .reg_type = FMC2_REG_BCR, - .reg_mask = FMC2_BCR1_CCLKEN, .check = stm32_fmc2_ebi_check_cclk, - .set = stm32_fmc2_ebi_set_bit_field, + .set = stm32_fmc2_ebi_set_cclk, }, { .name = "st,fmc2-ebi-cs-mux-enable", @@ -831,7 +934,7 @@ static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = { }, { .name = "st,fmc2-ebi-cs-clk-period-ns", - .reset_val = FMC2_BTR_CLKDIV_MAX + 1, + .reset_val = FMC2_REG_CLKDIV_MAX + 1, .check = stm32_fmc2_ebi_check_clk_period, .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, .set = stm32_fmc2_ebi_set_clk_period, @@ -959,7 +1062,10 @@ static void stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi) regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]); } - regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); + if (ebi->majrev < FMC2_VERR_MAJREV_2) + regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); + else + regmap_read(ebi->regmap, FMC2_CFGR, &ebi->cfgr); } static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi) @@ -972,7 +1078,10 @@ static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi) regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]); } - regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr); + if (ebi->majrev < FMC2_VERR_MAJREV_2) + regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr); + else + regmap_write(ebi->regmap, FMC2_CFGR, ebi->cfgr); } static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi) @@ -1011,13 +1120,20 @@ static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi) { - regmap_update_bits(ebi->regmap, FMC2_BCR1, - FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); + u32 reg = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1 : FMC2_CFGR; + u32 mask = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1_FMC2EN : + FMC2_CFGR_FMC2EN; + + regmap_update_bits(ebi->regmap, reg, mask, mask); } static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi) { - regmap_update_bits(ebi->regmap, FMC2_BCR1, FMC2_BCR1_FMC2EN, 0); + u32 reg = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1 : FMC2_CFGR; + u32 mask = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1_FMC2EN : + FMC2_CFGR_FMC2EN; + + regmap_update_bits(ebi->regmap, reg, mask, 0); } static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi, @@ -1108,6 +1224,7 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct stm32_fmc2_ebi *ebi; struct reset_control *rstc; + u32 verr; int ret; ebi = devm_kzalloc(&pdev->dev, sizeof(*ebi), GFP_KERNEL); @@ -1141,6 +1258,9 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev) reset_control_deassert(rstc); } + regmap_read(ebi->regmap, FMC2_VERR, &verr); + ebi->majrev = FIELD_GET(FMC2_VERR_MAJREV, verr); + ret = stm32_fmc2_ebi_parse_dt(ebi); if (ret) goto err_release; From patchwork Mon Feb 12 17:48:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Kerello X-Patchwork-Id: 199963 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp73387dyb; Mon, 12 Feb 2024 09:52:57 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVmQims9+Vax6tofX//NpGEAWdetp2FiU+jhmJt/35Kp1Dh+LexL9ceuSAZzGrv5tHXKES1ONhBwQ/hVQPoxjqN0AYvOg== X-Google-Smtp-Source: AGHT+IHcMgSicy1Nwoh46ksvfY/O+ZLQv+iB3JKNdRh/Zz4W2Oxk3MtkVeb6IlmB33JqUwzUYQ2F X-Received: by 2002:a17:906:c44d:b0:a3c:b7d5:22dd with SMTP id ck13-20020a170906c44d00b00a3cb7d522ddmr1982279ejb.33.1707760377406; Mon, 12 Feb 2024 09:52:57 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707760377; cv=pass; d=google.com; s=arc-20160816; b=W1Or9a6Z9acQtp2O3DOgqSrPBC+nrf+aJwBP7xDqTaZPs1OrZlKV2IJGzbB8QebqRY r5biXaIRdFhoOt47OAE44zZ8Ti4PGpOlT3PSwHrWBJqoj4U39hoEKz46PS+XRnnydb8D iDfGHP0cTn7HLOmnskSBPNQDSnzdGG1a3LyUddpXJSNZRbvlaY+oaEoTWiSxxuQtzxDP xtq0VjS0j/9JqW8w8HlTg5RMmmJbaK8crgZOrJBJKuG7k48Rgluls6mxPVU5PtkAS9RK icZrPu4NXIhu8OKx9rCD/CJzjRj3Zo0XaJZFRexbrFiUAfpoz1y/VBaYELQwuO+zIPnJ GD7w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=oqXVrdxeLLdwEVpu6l9p1qshhiLG7j1mEMNw7OfRL04=; fh=u2KHJf2RcQ9S1W9W3+nVTVTjiJ86LiZxPIsn8SSGzY4=; b=JntsB2Fb36yqhg1Pex/L6WEjyf1Cv3yhzSVFZX5Jqfc8Tm3hK9iqegoLz1kWteRZ17 vGA1Tjoh/3aCPVwuBDeqVFblpZwLDD4KtkqKkkacuuKlUq+tRvyq/gCjgIPDvWm7KFXJ qMlkROlTRCnU5gHIfx7IvHZsItTkHxq8tR6E1nPoRLblH2vYEzY5zgmvQ8ClkmPLCkXd OXlrorwXVmHgrfbsRtB2S2Fme4U4yjmaYkSqBfI9RmSwmECu0Jt2tVT0GwW8CrU1DUAx U4/GosX6eCMI+1fOWE6G4fiGGVmYQbz+hruSpEZW6NfaHspQ5zkCBfNQAfQ4QPVAWvAH LZgQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=uyHTah+O; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-62137-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62137-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com X-Forwarded-Encrypted: i=2; AJvYcCWQ3rlr0P7OVSLIRNacz+ni/1LqgGD/e6pqfz5XcFkg1K6nSIIoddKWOfXlGR2DEgsJ9CKMxHaan27AhLRByGGWm1iYnA== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Mon, 12 Feb 2024 18:50:52 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6F99527F295; Mon, 12 Feb 2024 18:50:07 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:50:07 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 06/12] memory: stm32-fmc2-ebi: add RIF support Date: Mon, 12 Feb 2024 18:48:16 +0100 Message-ID: <20240212174822.77734-7-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790716545715157909 X-GMAIL-MSGID: 1790716545715157909 The FMC2 revision 2 supports security and isolation compliant with the Resource Isolation Framework (RIF). From RIF point of view, the FMC2 is composed of several independent resources, listed below, which can be assigned to different security and compartment domains: - 0: Common FMC_CFGR register. - 1: EBI controller for Chip Select 1. - 2: EBI controller for Chip Select 2. - 3: EBI controller for Chip Select 3. - 4: EBI controller for Chip Select 4. - 5: NAND controller. Signed-off-by: Christophe Kerello --- drivers/memory/stm32-fmc2-ebi.c | 178 +++++++++++++++++++++++++++++++- 1 file changed, 174 insertions(+), 4 deletions(-) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index 066722274a45..04248c15832f 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -21,8 +21,14 @@ #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) #define FMC2_PCSCNTR 0x20 #define FMC2_CFGR 0x20 +#define FMC2_SR 0x84 #define FMC2_BWTR1 0x104 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) +#define FMC2_SECCFGR 0x300 +#define FMC2_CIDCFGR0 0x30c +#define FMC2_CIDCFGR(x) ((x) * 0x8 + FMC2_CIDCFGR0) +#define FMC2_SEMCR0 0x310 +#define FMC2_SEMCR(x) ((x) * 0x8 + FMC2_SEMCR0) #define FMC2_VERR 0x3f4 /* Register: FMC2_BCR1 */ @@ -66,12 +72,27 @@ #define FMC2_CFGR_CCLKEN BIT(20) #define FMC2_CFGR_FMC2EN BIT(31) +/* Register: FMC2_SR */ +#define FMC2_SR_ISOST GENMASK(1, 0) + +/* Register: FMC2_CIDCFGR */ +#define FMC2_CIDCFGR_CFEN BIT(0) +#define FMC2_CIDCFGR_SEMEN BIT(1) +#define FMC2_CIDCFGR_SCID GENMASK(6, 4) +#define FMC2_CIDCFGR_SEMWLC1 BIT(17) + +/* Register: FMC2_SEMCR */ +#define FMC2_SEMCR_SEM_MUTEX BIT(0) +#define FMC2_SEMCR_SEMCID GENMASK(7, 5) + /* Register: FMC2_VERR */ #define FMC2_VERR_MAJREV GENMASK(7, 4) #define FMC2_VERR_MAJREV_2 2 #define FMC2_MAX_EBI_CE 4 #define FMC2_MAX_BANKS 5 +#define FMC2_MAX_RESOURCES 6 +#define FMC2_CID1 1 #define FMC2_BCR_CPSIZE_0 0x0 #define FMC2_BCR_CPSIZE_128 0x1 @@ -167,7 +188,9 @@ struct stm32_fmc2_ebi { struct regmap *regmap; const struct stm32_fmc2_ebi_data *data; u8 bank_assigned; + u8 sem_taken; u8 majrev; + bool access_granted; u32 bcr[FMC2_MAX_EBI_CE]; u32 btr[FMC2_MAX_EBI_CE]; @@ -733,6 +756,11 @@ static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi, u32 reg = FMC2_BTR(cs); u32 mask = FMC2_BTR_CLKDIV; + if (!ebi->access_granted) { + dev_err(ebi->dev, "CFGR access forbidden\n"); + return -EACCES; + } + if (ebi->majrev >= FMC2_VERR_MAJREV_2) { u32 cfgr; @@ -822,6 +850,11 @@ static int stm32_fmc2_ebi_set_cclk(struct stm32_fmc2_ebi *ebi, u32 mask = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1_CCLKEN : FMC2_CFGR_CCLKEN; + if (!ebi->access_granted) { + dev_err(ebi->dev, "CFGR access forbidden\n"); + return -EACCES; + } + regmap_update_bits(ebi->regmap, reg, mask, setup ? mask : 0); return 0; @@ -990,6 +1023,107 @@ static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = { }, }; +static int stm32_fmc2_ebi_check_rif(struct stm32_fmc2_ebi *ebi, u32 resource) +{ + u32 seccfgr, cidcfgr, semcr; + int cid; + + if (ebi->majrev < FMC2_VERR_MAJREV_2) + return 0; + + if (resource >= FMC2_MAX_RESOURCES) + return -EINVAL; + + regmap_read(ebi->regmap, FMC2_SECCFGR, &seccfgr); + if (seccfgr & BIT(resource)) { + if (resource) + dev_err(ebi->dev, "resource %d is configured as secure\n", + resource); + + return -EACCES; + } + + regmap_read(ebi->regmap, FMC2_CIDCFGR(resource), &cidcfgr); + if (!(cidcfgr & FMC2_CIDCFGR_CFEN)) + /* CID filtering is turned off: access granted */ + return 0; + + if (!(cidcfgr & FMC2_CIDCFGR_SEMEN)) { + /* Static CID mode */ + cid = FIELD_GET(FMC2_CIDCFGR_SCID, cidcfgr); + if (cid != FMC2_CID1) { + if (resource) + dev_err(ebi->dev, "static CID%d set for resource %d\n", + cid, resource); + + return -EACCES; + } + + return 0; + } + + /* Pass-list with semaphore mode */ + if (!(cidcfgr & FMC2_CIDCFGR_SEMWLC1)) { + if (resource) + dev_err(ebi->dev, "CID1 is block-listed for resource %d\n", + resource); + + return -EACCES; + } + + regmap_read(ebi->regmap, FMC2_SEMCR(resource), &semcr); + if (!(semcr & FMC2_SEMCR_SEM_MUTEX)) { + regmap_update_bits(ebi->regmap, FMC2_SEMCR(resource), + FMC2_SEMCR_SEM_MUTEX, FMC2_SEMCR_SEM_MUTEX); + regmap_read(ebi->regmap, FMC2_SEMCR(resource), &semcr); + } + + cid = FIELD_GET(FMC2_SEMCR_SEMCID, semcr); + if (cid != FMC2_CID1) { + if (resource) + dev_err(ebi->dev, "resource %d is already used by CID%d\n", + resource, cid); + + return -EACCES; + } + + ebi->sem_taken |= BIT(resource); + + return 0; +} + +static void stm32_fmc2_ebi_put_sems(struct stm32_fmc2_ebi *ebi) +{ + unsigned int resource; + + if (ebi->majrev < FMC2_VERR_MAJREV_2) + return; + + for (resource = 0; resource < FMC2_MAX_RESOURCES; resource++) { + if (!(ebi->sem_taken & BIT(resource))) + continue; + + regmap_update_bits(ebi->regmap, FMC2_SEMCR(resource), + FMC2_SEMCR_SEM_MUTEX, 0); + } +} + +static void stm32_fmc2_ebi_get_sems(struct stm32_fmc2_ebi *ebi) +{ + unsigned int resource; + + if (ebi->majrev < FMC2_VERR_MAJREV_2) + return; + + for (resource = 0; resource < FMC2_MAX_RESOURCES; resource++) { + if (!(ebi->sem_taken & BIT(resource))) + continue; + + regmap_update_bits(ebi->regmap, FMC2_SEMCR(resource), + FMC2_SEMCR_SEM_MUTEX, FMC2_SEMCR_SEM_MUTEX); + } +} + static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi, struct device_node *dev_node, const struct stm32_fmc2_prop *prop, @@ -1057,6 +1191,9 @@ static void stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi) unsigned int cs; for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { + if (!(ebi->bank_assigned & BIT(cs))) + continue; + regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]); regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]); regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]); @@ -1064,7 +1201,7 @@ static void stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi) if (ebi->majrev < FMC2_VERR_MAJREV_2) regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); - else + else if (ebi->access_granted) regmap_read(ebi->regmap, FMC2_CFGR, &ebi->cfgr); } @@ -1073,6 +1210,9 @@ static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi) unsigned int cs; for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { + if (!(ebi->bank_assigned & BIT(cs))) + continue; + regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]); regmap_write(ebi->regmap, FMC2_BTR(cs), ebi->btr[cs]); regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]); @@ -1080,7 +1220,7 @@ static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi) if (ebi->majrev < FMC2_VERR_MAJREV_2) regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr); - else + else if (ebi->access_granted) regmap_write(ebi->regmap, FMC2_CFGR, ebi->cfgr); } @@ -1124,7 +1264,8 @@ static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi) u32 mask = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1_FMC2EN : FMC2_CFGR_FMC2EN; - regmap_update_bits(ebi->regmap, reg, mask, mask); + if (ebi->access_granted) + regmap_update_bits(ebi->regmap, reg, mask, mask); } static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi) @@ -1133,7 +1274,8 @@ static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi) u32 mask = ebi->majrev < FMC2_VERR_MAJREV_2 ? FMC2_BCR1_FMC2EN : FMC2_CFGR_FMC2EN; - regmap_update_bits(ebi->regmap, reg, mask, 0); + if (ebi->access_granted) + regmap_update_bits(ebi->regmap, reg, mask, 0); } static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi, @@ -1190,6 +1332,13 @@ static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2_ebi *ebi) return -EINVAL; } + ret = stm32_fmc2_ebi_check_rif(ebi, bank + 1); + if (ret) { + dev_err(dev, "bank access failed: %d\n", bank); + of_node_put(child); + return ret; + } + if (bank < FMC2_MAX_EBI_CE) { ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank); if (ret) { @@ -1261,6 +1410,23 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev) regmap_read(ebi->regmap, FMC2_VERR, &verr); ebi->majrev = FIELD_GET(FMC2_VERR_MAJREV, verr); + /* Check if CFGR register can be modified */ + ret = stm32_fmc2_ebi_check_rif(ebi, 0); + if (!ret) + ebi->access_granted = true; + + /* In case of CFGR is secure, just check that the FMC2 is enabled */ + if (!ebi->access_granted) { + u32 sr; + + regmap_read(ebi->regmap, FMC2_SR, &sr); + if (sr & FMC2_SR_ISOST) { + dev_err(dev, "FMC2 is not ready to be used.\n"); + ret = -EACCES; + goto err_release; + } + } + ret = stm32_fmc2_ebi_parse_dt(ebi); if (ret) goto err_release; @@ -1273,6 +1439,7 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev) err_release: stm32_fmc2_ebi_disable_banks(ebi); stm32_fmc2_ebi_disable(ebi); + stm32_fmc2_ebi_put_sems(ebi); clk_disable_unprepare(ebi->clk); return ret; @@ -1285,6 +1452,7 @@ static void stm32_fmc2_ebi_remove(struct platform_device *pdev) of_platform_depopulate(&pdev->dev); stm32_fmc2_ebi_disable_banks(ebi); stm32_fmc2_ebi_disable(ebi); + stm32_fmc2_ebi_put_sems(ebi); clk_disable_unprepare(ebi->clk); } @@ -1293,6 +1461,7 @@ static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev) struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev); stm32_fmc2_ebi_disable(ebi); + stm32_fmc2_ebi_put_sems(ebi); clk_disable_unprepare(ebi->clk); pinctrl_pm_select_sleep_state(dev); @@ -1310,6 +1479,7 @@ static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev) if (ret) return ret; + stm32_fmc2_ebi_get_sems(ebi); stm32_fmc2_ebi_set_setup(ebi); stm32_fmc2_ebi_enable(ebi); From patchwork Mon Feb 12 17:48:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Kerello X-Patchwork-Id: 199975 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp89338dyb; Mon, 12 Feb 2024 10:18:02 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVZp5lzYYDc/8PuYKrOqqinz0JWD4UpSynMwXfVYsg+6ZPAZt8jxDZdcAjmbhezrSWpZyKLd+NGZ+sd56o/zDgz/BW7Bg== X-Google-Smtp-Source: AGHT+IHS4xoep95xdJIlRzxCiPwXpgtgRxsrBj4xWmf2XuwUHRtMjL/IxLhUAqa/tAooOI+Z0qGX X-Received: by 2002:a05:6a21:8cc9:b0:19e:ca6a:118e with SMTP id ta9-20020a056a218cc900b0019eca6a118emr4616326pzb.36.1707761882517; Mon, 12 Feb 2024 10:18:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707761882; cv=pass; d=google.com; s=arc-20160816; b=J+eYG68MP6UW9LqAi0W4xKaVwpI+GX/tEp3ECbGDC7oq4qHD0zcBMS05VwGGoIALit XLc55mF2AYVE96tqNF+XtbM/Oi5hDjoXUTTno0zdfeSsd6/NajprqKpC8gaxsvFra11U jS9qBnMVo50VfUyS8Zm9CzmnhD1MEcCqoXmzEoz62/FS9RsCYud7Jzxb4XN3cxFu+mem x3PPqGd2m0PX/9y9ao94bjVnMSz2nZAfetS+AhAf5VS7YTf/I8DgxgDxJYO6KHb9sqtf Ae7WFXg0+kezioKdkbGSukINgoDW8KZb+HpZesQcHhumTL2MTUGUoic4bw2r6LTBz3yq pi3A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=yBt3J1JvC9JWaK1tn/1K6Z3tKSfz+E4rgFKGPurOxBY=; fh=Txg9wzQSMH2QEwQAqGrgwO4AEbL3azBFV274xDnK9Js=; b=AN36AA3z7ijYY/k7pHb0XN4d7sTCRM0cYCuLLMrtSyZNCDsxxh3wQiPKJ/x1QEMeTe gMW3VBFWsDRa8Bovrpoa2S180GTcrbb2hn1uh8tWRfW3LBqgXgSKs7Wi/yBvmAxMdgWn r1n7XwRi6TFgDcdk/MsMC+odxTuzaNombnFWelM004RXArdTlTZzX1BekKJQ8JQ2A/qM gXrIzdQJVXBF5j9eLY8N3avc4feY+syiTTzXK6yVk9rE+a0h8Hf8EyA+ndskipNjL9Gm 3QHm0xciPB39A2FM1WtspoFg/MK83SkXsPGyqnVSm2RYy3v25jBZps74XHBnKZyRED1G xy4Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=xZx3E2ww; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-62138-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62138-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com X-Forwarded-Encrypted: i=2; AJvYcCVb5yn+VAXzXSnMOAemEEZWyzBO1xVEGcPGh0k3CGjR/P8Sl7NNGHq+Qq0FVeGJ/nmO1XSPYq5Y0zuj/ZoyjE62yGSgCg== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Mon, 12 Feb 2024 18:51:07 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 15F5927F261; Mon, 12 Feb 2024 18:50:22 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:50:21 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 07/12] memory: stm32-fmc2-ebi: add runtime PM support Date: Mon, 12 Feb 2024 18:48:17 +0100 Message-ID: <20240212174822.77734-8-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790718123476412252 X-GMAIL-MSGID: 1790718123476412252 Add runtime PM support in FMC2 ebi driver to be able to manage GENPD support when it will be enabled. Signed-off-by: Christophe Kerello --- drivers/memory/stm32-fmc2-ebi.c | 40 ++++++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index 04248c15832f..8c30e56be3b0 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -1381,6 +1382,7 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev) return -ENOMEM; ebi->dev = dev; + platform_set_drvdata(pdev, ebi); ebi->data = of_device_get_match_data(dev); if (!ebi->data) @@ -1398,10 +1400,14 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev) if (PTR_ERR(rstc) == -EPROBE_DEFER) return -EPROBE_DEFER; - ret = clk_prepare_enable(ebi->clk); + ret = devm_pm_runtime_enable(dev); if (ret) return ret; + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + if (!IS_ERR(rstc)) { reset_control_assert(rstc); reset_control_deassert(rstc); @@ -1432,7 +1438,6 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev) goto err_release; stm32_fmc2_ebi_save_setup(ebi); - platform_set_drvdata(pdev, ebi); return 0; @@ -1440,7 +1445,7 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev) stm32_fmc2_ebi_disable_banks(ebi); stm32_fmc2_ebi_disable(ebi); stm32_fmc2_ebi_put_sems(ebi); - clk_disable_unprepare(ebi->clk); + pm_runtime_put_sync_suspend(dev); return ret; } @@ -1453,7 +1458,23 @@ static void stm32_fmc2_ebi_remove(struct platform_device *pdev) stm32_fmc2_ebi_disable_banks(ebi); stm32_fmc2_ebi_disable(ebi); stm32_fmc2_ebi_put_sems(ebi); + pm_runtime_put_sync_suspend(&pdev->dev); +} + +static int __maybe_unused stm32_fmc2_ebi_runtime_suspend(struct device *dev) +{ + struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev); + clk_disable_unprepare(ebi->clk); + + return 0; +} + +static int __maybe_unused stm32_fmc2_ebi_runtime_resume(struct device *dev) +{ + struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev); + + return clk_prepare_enable(ebi->clk); } static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev) @@ -1462,7 +1483,7 @@ static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev) stm32_fmc2_ebi_disable(ebi); stm32_fmc2_ebi_put_sems(ebi); - clk_disable_unprepare(ebi->clk); + pm_runtime_put_sync_suspend(dev); pinctrl_pm_select_sleep_state(dev); return 0; @@ -1475,8 +1496,8 @@ static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev) pinctrl_pm_select_default_state(dev); - ret = clk_prepare_enable(ebi->clk); - if (ret) + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) return ret; stm32_fmc2_ebi_get_sems(ebi); @@ -1486,8 +1507,11 @@ static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend, - stm32_fmc2_ebi_resume); +static const struct dev_pm_ops stm32_fmc2_ebi_pm_ops = { + SET_RUNTIME_PM_OPS(stm32_fmc2_ebi_runtime_suspend, + stm32_fmc2_ebi_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(stm32_fmc2_ebi_suspend, stm32_fmc2_ebi_resume) +}; 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Mon, 12 Feb 2024 18:51:22 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4C6B327F266; Mon, 12 Feb 2024 18:50:37 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:50:37 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 08/12] dt-bindings: mtd: st,stm32: add MP25 support Date: Mon, 12 Feb 2024 18:48:18 +0100 Message-ID: <20240212174822.77734-9-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790716592693770589 X-GMAIL-MSGID: 1790716592693770589 Add 2 new compatible strings to support MP25 SOC. MP25 SOC supports up to 4 chip select. Signed-off-by: Christophe Kerello --- .../bindings/mtd/st,stm32-fmc2-nand.yaml | 58 ++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml index e72cb5bacaf0..33a753c8877b 100644 --- a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml @@ -14,10 +14,12 @@ properties: enum: - st,stm32mp15-fmc2 - st,stm32mp1-fmc2-nfc + - st,stm32mp25-fmc2 + - st,stm32mp25-fmc2-nfc reg: minItems: 6 - maxItems: 7 + maxItems: 13 interrupts: maxItems: 1 @@ -92,6 +94,60 @@ allOf: - description: Chip select 1 command - description: Chip select 1 address space + - if: + properties: + compatible: + contains: + const: st,stm32mp25-fmc2 + then: + properties: + reg: + items: + - description: Registers + - description: Chip select 0 data + - description: Chip select 0 command + - description: Chip select 0 address space + - description: Chip select 1 data + - description: Chip select 1 command + - description: Chip select 1 address space + - description: Chip select 2 data + - description: Chip select 2 command + - description: Chip select 2 address space + - description: Chip select 3 data + - description: Chip select 3 command + - description: Chip select 3 address space + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + required: + - clocks + + - if: + properties: + compatible: + contains: + const: st,stm32mp25-fmc2-nfc + then: + properties: + reg: + items: + - description: Chip select 0 data + - description: Chip select 0 command + - description: Chip select 0 address space + - description: Chip select 1 data + - description: Chip select 1 command + - description: Chip select 1 address space + - description: Chip select 2 data + - description: Chip select 2 command + - description: Chip select 2 address space + - description: Chip select 3 data + - description: Chip select 3 command + - description: Chip select 3 address space + required: - compatible - reg From patchwork Mon Feb 12 17:48:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Kerello X-Patchwork-Id: 199966 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp73788dyb; Mon, 12 Feb 2024 09:54:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IHBD8qDsDlqul0GGZmBNzpmB+uW5ojIEp4hQsJX6UZUaPLRajpo+lPbmxrONj+0r0V1ebzp X-Received: by 2002:a17:906:3b9a:b0:a3c:d053:1272 with SMTP id u26-20020a1709063b9a00b00a3cd0531272mr1252026ejf.15.1707760444676; Mon, 12 Feb 2024 09:54:04 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707760444; cv=pass; d=google.com; s=arc-20160816; b=freqN2kqAubPZbs71XEdLZxHn1u32yZtOtPKI/umSGYcVFt7cbW/Uyee2KNAubnAsT WYSiv4F3ytX7wD235Y0V4YhjeLveUJVuFuIkRKefdxH6reJDXMppHC1iAjifLjBEQfjg qZJnpvRFw6BTJx+PpNJ+e8Ti6jiiE1hfnAnldnAyXpacXdJFh8cWWkREcoapRu5BSs46 DLCiu/WT5jiXLOM4h33Qc4ZYwurUWGR3aJWzE3HTRNxK2rer8VGf/EmYkTuBJSjJh08I LgX3XwGhwH8O7neXkRz5qJs6s+86G8EaxdllRb+bxDWRs+nZ4JhDaP7vss99BGFbgXcX R7FA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=7EgcsVO6falgJZLPBOMxl9PtlOXDfK5LsUZXJt7kC2w=; fh=RhTg+iZ6T+zChqgXFRizf5y7tzKVpWgaIVOkjO1Gzeo=; b=FmqvV2OquVW2k/DOi5LejdbVo2De7oq6zDUt/O66pZvAJRHXkod4ARG9Xw3Lw0un/q xTNhG89A85k5mZBBtlYraayEqZllInACRLtjGtxwFNhkq7+xSw12aoJLKjaVlPWO1P5/ SmryptAsNU+5t3VemU0b2FxNalZCh7xcMmFivo0iDTfDgH/7BNAZm8N+MkNlFa7FjFbo Uhei39Bea4HtbbxyXvmn/9QqxldzYYzCU5NaTc+IH08PmVbNYO9K3s9VAxWToTVZp8mL amk5c8vpgsDzhbQgp5JrF0s+BHteT1RAwlvjVMaw5T4X7kpn2wJMm4P6yZA1j8JC8sRA HS8w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=dfJ186Zk; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-62140-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62140-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com X-Forwarded-Encrypted: i=2; AJvYcCUQsSMHSWE5A7WByZk0aSeosuJ5QuCsYuy8EtMR4gDrAXqCNNoGx10Tgaxs4U1ZIOc/dqSlf3NAfWiqc41lL1Eyg/Bn4Q== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Mon, 12 Feb 2024 18:51:34 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D898C257A8E; Mon, 12 Feb 2024 18:50:51 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:50:51 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 09/12] mtd: rawnand: stm32_fmc2: use dma_get_slave_caps to get DMA max burst Date: Mon, 12 Feb 2024 18:48:19 +0100 Message-ID: <20240212174822.77734-10-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790716616099649492 X-GMAIL-MSGID: 1790716616099649492 use dma_get_slave_caps API to get the max burst size of a DMA channel. For MP1 SOCs, MDMA is used and the max burst size is 128. For MP25 SOC, DMA3 is used and the max burst size is 64. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 29 +++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 88811139aaf5..a7db7b675514 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -264,6 +264,8 @@ struct stm32_fmc2_nfc { struct sg_table dma_ecc_sg; u8 *ecc_buf; int dma_ecc_len; + u32 tx_dma_max_burst; + u32 rx_dma_max_burst; struct completion complete; struct completion dma_data_complete; @@ -347,20 +349,26 @@ static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr) stm32_fmc2_nfc_setup(chip); stm32_fmc2_nfc_timings_init(chip); - if (nfc->dma_tx_ch && nfc->dma_rx_ch) { + if (nfc->dma_tx_ch) { memset(&dma_cfg, 0, sizeof(dma_cfg)); - dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel]; dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel]; - dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_cfg.src_maxburst = 32; - dma_cfg.dst_maxburst = 32; + dma_cfg.dst_maxburst = nfc->tx_dma_max_burst / + dma_cfg.dst_addr_width; ret = dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg); if (ret) { dev_err(nfc->dev, "tx DMA engine slave config failed\n"); return ret; } + } + + if (nfc->dma_rx_ch) { + memset(&dma_cfg, 0, sizeof(dma_cfg)); + dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel]; + dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_cfg.src_maxburst = nfc->rx_dma_max_burst / + dma_cfg.src_addr_width; ret = dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg); if (ret) { @@ -1545,6 +1553,7 @@ static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr, static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc) { + struct dma_slave_caps caps; int ret = 0; nfc->dma_tx_ch = dma_request_chan(nfc->dev, "tx"); @@ -1557,6 +1566,11 @@ static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc) goto err_dma; } + ret = dma_get_slave_caps(nfc->dma_tx_ch, &caps); + if (ret) + return ret; + nfc->tx_dma_max_burst = caps.max_burst; + nfc->dma_rx_ch = dma_request_chan(nfc->dev, "rx"); if (IS_ERR(nfc->dma_rx_ch)) { ret = PTR_ERR(nfc->dma_rx_ch); @@ -1567,6 +1581,11 @@ static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc) goto err_dma; } + ret = dma_get_slave_caps(nfc->dma_rx_ch, &caps); + if (ret) + return ret; + nfc->rx_dma_max_burst = caps.max_burst; + nfc->dma_ecc_ch = dma_request_chan(nfc->dev, "ecc"); if (IS_ERR(nfc->dma_ecc_ch)) { ret = PTR_ERR(nfc->dma_ecc_ch); From patchwork Mon Feb 12 17:48:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Kerello X-Patchwork-Id: 199967 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp74099dyb; Mon, 12 Feb 2024 09:54:48 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU8InRxRtj8c6AaNb6+SAHy6/sDev2b5EROn+8ejoosdTn7an+0wglsIjt4Ay8rh/N1U5NtAdTMyojk6v5gTU8G2rlfTA== X-Google-Smtp-Source: AGHT+IGvlxGWrAAD+B5HuznTviGDmxutJQuwip1LWSGuJtU84drqZ4SHTwS2CCeAHvHu5zExTLb+ X-Received: by 2002:a05:6402:281:b0:560:e6d:4ce9 with SMTP id l1-20020a056402028100b005600e6d4ce9mr4093552edv.41.1707760488061; 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Mon, 12 Feb 2024 18:51:50 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 15EAF231529; Mon, 12 Feb 2024 18:51:07 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:51:06 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 10/12] mtd: rawnand: stm32_fmc2: add a platform data structure Date: Mon, 12 Feb 2024 18:48:20 +0100 Message-ID: <20240212174822.77734-11-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790716661596509995 X-GMAIL-MSGID: 1790716661596509995 Before the introduction of MP25 SOC, let's use a platform data structure for parameters that will differ (number of chip select). The FMC2 NAND can support up to 4 chips select. On MP1 SOCs, only 2 chip select are available. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 32 +++++++++++++++++++++----- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index a7db7b675514..c5bdb43f7221 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -37,7 +38,7 @@ #define FMC2_MAX_SG 16 /* Max chip enable */ -#define FMC2_MAX_CE 2 +#define FMC2_MAX_CE 4 /* Max ECC buffer length */ #define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG) @@ -243,6 +244,10 @@ static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip) return container_of(chip, struct stm32_fmc2_nand, chip); } +struct stm32_fmc2_nfc_data { + int max_ncs; +}; + struct stm32_fmc2_nfc { struct nand_controller base; struct stm32_fmc2_nand nand; @@ -256,6 +261,7 @@ struct stm32_fmc2_nfc { phys_addr_t data_phys_addr[FMC2_MAX_CE]; struct clk *clk; u8 irq_state; + const struct stm32_fmc2_nfc_data *data; struct dma_chan *dma_tx_ch; struct dma_chan *dma_rx_ch; @@ -1809,7 +1815,7 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, return ret; } - if (cs >= FMC2_MAX_CE) { + if (cs >= nfc->data->max_ncs) { dev_err(nfc->dev, "invalid reg value: %d\n", cs); return -EINVAL; } @@ -1915,6 +1921,10 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev) nand_controller_init(&nfc->base); nfc->base.ops = &stm32_fmc2_nfc_controller_ops; + nfc->data = of_device_get_match_data(dev); + if (!nfc->data) + return -EINVAL; + ret = stm32_fmc2_nfc_set_cdev(nfc); if (ret) return ret; @@ -1936,7 +1946,7 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev) if (nfc->dev == nfc->cdev) start_region = 1; - for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE; + for (chip_cs = 0, mem_region = start_region; chip_cs < nfc->data->max_ncs; chip_cs++, mem_region += 3) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; @@ -2092,7 +2102,7 @@ static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev) stm32_fmc2_nfc_wp_disable(nand); - for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) { + for (chip_cs = 0; chip_cs < nfc->data->max_ncs; chip_cs++) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; @@ -2105,9 +2115,19 @@ static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend, stm32_fmc2_nfc_resume); +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp1_data = { + .max_ncs = 2, +}; + static const struct of_device_id stm32_fmc2_nfc_match[] = { - {.compatible = "st,stm32mp15-fmc2"}, - {.compatible = "st,stm32mp1-fmc2-nfc"}, + { + .compatible = "st,stm32mp15-fmc2", + .data = &stm32_fmc2_nfc_mp1_data, + }, + { + .compatible = "st,stm32mp1-fmc2-nfc", + .data = &stm32_fmc2_nfc_mp1_data, + }, {} }; MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match); From patchwork Mon Feb 12 17:48:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Kerello X-Patchwork-Id: 199977 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp92374dyb; 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Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index c5bdb43f7221..d71ec12cd5b1 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -1878,11 +1878,14 @@ static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc2_nfc *nfc) struct device *dev = nfc->dev; bool ebi_found = false; - if (dev->parent && of_device_is_compatible(dev->parent->of_node, - "st,stm32mp1-fmc2-ebi")) + if (dev->parent && (of_device_is_compatible(dev->parent->of_node, + "st,stm32mp1-fmc2-ebi") || + of_device_is_compatible(dev->parent->of_node, + "st,stm32mp25-fmc2-ebi"))) ebi_found = true; - if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc")) { + if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc") || + of_device_is_compatible(dev->of_node, "st,stm32mp25-fmc2-nfc")) { if (ebi_found) { nfc->cdev = dev->parent; @@ -2119,6 +2122,10 @@ static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp1_data = { .max_ncs = 2, }; +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp25_data = { + .max_ncs = 4, +}; + static const struct of_device_id stm32_fmc2_nfc_match[] = { { .compatible = "st,stm32mp15-fmc2", @@ -2128,6 +2135,14 @@ static const struct of_device_id stm32_fmc2_nfc_match[] = { .compatible = "st,stm32mp1-fmc2-nfc", .data = &stm32_fmc2_nfc_mp1_data, }, + { + .compatible = "st,stm32mp25-fmc2", + .data = &stm32_fmc2_nfc_mp25_data, + }, + { + .compatible = "st,stm32mp25-fmc2-nfc", + .data = &stm32_fmc2_nfc_mp25_data, + }, {} }; MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match); From patchwork Mon Feb 12 17:48:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Kerello X-Patchwork-Id: 199968 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp74403dyb; Mon, 12 Feb 2024 09:55:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IH8v3B63sC44WlBxdHnNE4H88/vJfabs8d1JoAz+gdu0iLXkQKXxlXPgJMlsTWLNQnThMcr X-Received: by 2002:a17:906:f1d1:b0:a37:2ed2:cba1 with SMTP id gx17-20020a170906f1d100b00a372ed2cba1mr5200234ejb.22.1707760530043; Mon, 12 Feb 2024 09:55:30 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707760530; cv=pass; d=google.com; s=arc-20160816; b=FyTAppZfv6hvbW1pilyF/pP4OteWOBVZ8Tgn59Vao4XQL2nT8OwnGz6/Whphk4U7X5 N4MKnkMUWgfJ/qvSATsLUt7FTBAxpvPMNT2x4BGVwcZ+FgsXGryELvUuW5gOkYr3p2cV rixiLeinmZOEpDpWRRFtSzNinYH3UdHfUjsyKa1vfiSBVvhb5hSiglODQiCiQm/Rc/1g G4uzfxPeyz0qluTcWHJnDmNZTu3c7xdUxOFlnDCRW0/RXpyS/AUMaalINnx66ZNYR3Fd VuUY0+ghi5DZ8b4VkyxcKLcfz8dzKeNVgSFXzlVoZlWfbXzmaziud7sAPHuI7p5daiiV wc6g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=RXMt+Y7BsrK1R0K7F39FqII/k6oBa+2vVyGkF3jcPCU=; fh=Zx3eufGVH9D1u2kf5d/5mjszZhiV+QeK99uYfFuNH0Y=; b=QNAj633lyPjgyMtSuO6NT3SatpGoddfPlNknTQvjw4zWH9LB100ecxIh9C2lP5PL/Q 7AFwvzaScpLNTPYhTZVpvgkCVTrJJI8tO/5GHPaLX7GjqPNT4WnvU19HzxiEGoTaqGFz 3UDz7vAWvuhP3iDo9dbz/rjdsQfHYJop+oAYgKLjsW3+KnPNVsLEcO+Mq6Cpf7ZMdjTb jFjRo011Zjx9zAkTdnDyirfB9OGcX4r4FVporpE1Isb7G3BK59RWrsGe44/WPIDf/bzx b+Xwg+kCFRUQ9oTt0O2LjJVd0INbLwLgZkH7Ou0tQOZv0LSB6xHOvQ4N2E6Mwe6t9B7C 8W8A==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=Z7QnM6jf; arc=pass (i=1 spf=pass spfdomain=foss.st.com dkim=pass dkdomain=foss.st.com dmarc=pass fromdomain=foss.st.com); spf=pass (google.com: domain of linux-kernel+bounces-62144-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62144-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com X-Forwarded-Encrypted: i=2; AJvYcCWD0fDrrkR4foxjltXLnece60c1G03YTaKimV1YP+hjV/bFQt5SH+veNa3MXz0NVEYgLS4c1grsL69acNyYwe+34adVpg== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Mon, 12 Feb 2024 18:52:19 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3B9C9257A8E; Mon, 12 Feb 2024 18:51:37 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:51:36 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 12/12] mtd: rawnand: stm32_fmc2: update the driver to support revision 2 Date: Mon, 12 Feb 2024 18:48:22 +0100 Message-ID: <20240212174822.77734-13-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790716705644354924 X-GMAIL-MSGID: 1790716705644354924 Add the support of the revision 2 of FMC2 IP. For the NAND controller, the bit used to enable the IP has moved. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index d71ec12cd5b1..877255b0d0fc 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -54,6 +54,7 @@ /* FMC2 Controller Registers */ #define FMC2_BCR1 0x0 +#define FMC2_CFGR 0x20 #define FMC2_PCR 0x80 #define FMC2_SR 0x84 #define FMC2_PMEM 0x88 @@ -83,10 +84,14 @@ #define FMC2_BCHDSR2 0x284 #define FMC2_BCHDSR3 0x288 #define FMC2_BCHDSR4 0x28c +#define FMC2_VERR 0x3f4 /* Register: FMC2_BCR1 */ #define FMC2_BCR1_FMC2EN BIT(31) +/* Register: FMC2_CFGR */ +#define FMC2_CFGR_FMC2EN BIT(31) + /* Register: FMC2_PCR */ #define FMC2_PCR_PWAITEN BIT(1) #define FMC2_PCR_PBKEN BIT(2) @@ -208,6 +213,10 @@ #define FMC2_BCHDSR4_EBP7 GENMASK(12, 0) #define FMC2_BCHDSR4_EBP8 GENMASK(28, 16) +/* Register: FMC2_VERR */ +#define FMC2_VERR_MAJREV GENMASK(7, 4) +#define FMC2_VERR_MAJREV_2 2 + enum stm32_fmc2_ecc { FMC2_ECC_HAM = 1, FMC2_ECC_BCH4 = 4, @@ -1397,9 +1406,20 @@ static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc) pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT); /* Enable FMC2 controller */ - if (nfc->dev == nfc->cdev) - regmap_update_bits(nfc->regmap, FMC2_BCR1, - FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); + if (nfc->dev == nfc->cdev) { + u32 verr; + u8 majrev; + + regmap_read(nfc->regmap, FMC2_VERR, &verr); + majrev = FIELD_GET(FMC2_VERR_MAJREV, verr); + + if (majrev < FMC2_VERR_MAJREV_2) + regmap_update_bits(nfc->regmap, FMC2_BCR1, + FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); + else + regmap_update_bits(nfc->regmap, FMC2_CFGR, + FMC2_CFGR_FMC2EN, FMC2_CFGR_FMC2EN); + } regmap_write(nfc->regmap, FMC2_PCR, pcr); regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);