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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.03.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:03:37 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 01/12] spi: dt-bindings: introduce FIFO depth properties Date: Mon, 12 Feb 2024 14:03:20 +0000 Message-ID: <20240212140331.915498-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702458574232449 X-GMAIL-MSGID: 1790702458574232449 There are SPI IPs that can be configured by the integrator with a specific FIFO depth depending on the system's capabilities. For example, the samsung USI SPI IP can be configured by the integrator with a TX/RX FIFO from 8 byte to 256 bytes. Introduce the ``fifo-depth`` property for such instances of IPs where the same FIFO depth is used for both RX and TX. Introduce ``rx-fifo-depth`` and ``tx-fifo-depth`` properties for cases where the RX FIFO depth is different from the TX FIFO depth. Make the dedicated RX/TX properties dependent on each other and mutual exclusive with the other. Signed-off-by: Tudor Ambarus Reviewed-by: Rob Herring --- .../bindings/spi/spi-controller.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml index 524f6fe8c27b..add39884d226 100644 --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml @@ -69,6 +69,21 @@ properties: Should be generally avoided and be replaced by spi-cs-high + ACTIVE_HIGH. + fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the RX and TX data FIFOs in bytes. + + rx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the RX data FIFO in bytes. + + tx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the TX data FIFO in bytes. + num-cs: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -116,6 +131,10 @@ patternProperties: - compatible - reg +dependencies: + rx-fifo-depth: [ tx-fifo-depth ] + tx-fifo-depth: [ rx-fifo-depth ] + allOf: - if: not: @@ -129,6 +148,14 @@ allOf: properties: "#address-cells": const: 0 + - not: + required: + - fifo-depth + - rx-fifo-depth + - not: + required: + - fifo-depth + - tx-fifo-depth additionalProperties: true From patchwork Mon Feb 12 14:03:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 199830 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2449875dyd; Mon, 12 Feb 2024 06:09:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IFADLJuvVz0UEuri17OZXW2LU6T6zJJuoo3bKnSEWmvQR4xTZs1n1M6Ebzayz91rNoZAE5w X-Received: by 2002:a05:6214:1bc6:b0:68c:9d40:d1c with SMTP id m6-20020a0562141bc600b0068c9d400d1cmr10105172qvc.0.1707746966118; Mon, 12 Feb 2024 06:09:26 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707746966; cv=pass; d=google.com; s=arc-20160816; b=UrZ4xbLAqa79n2nfbsJU3lD1jNdpr1ZzwJGas+Qj3zag46uQA+42B2EFM1SxaidAEZ NTzSmVeUMP11qhe9bk6KV8ucae1C3iKQb79AXMaT8+/ULVFlo6NDamVo5QNfRK29+LoL NfmNyJceKQ+xtFNzoPzpi2QKkcqAj8ADPSV03iGMFc7yrSNq38/eJfBvkcoaAQh1cFEL 6Pnxb6m/Cu+2Jwwb8OkiQZnL69kAdBNcBfCXWIfM/o4Wmdrk2BW1zN3tZch2meS0CBsT QFDS4AXPSq+5kK1k0EnJGvQCRyEmRcQkwkoenPT/CKI5aCN+quepvxuFr2Ln8kmBR9a4 jPCQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=/YEBZ5QgPmZi1uvEzjonJi8xfKR7wdfW/zkTSEaERIc=; fh=Q20M++GIxQnFux1h4Lu77MXY42Eccyse8dJjKkFM5lA=; b=1DFSpMLvwAgZrh3FZvJRdlWh+3z8BmElFqA8ywycRAWQqgfpBeNBQgC/XKIGn43t4q bIiF6s9J/8sge+2FvKpCtEjCH+v8Aodp9tljgMUOIRkn2iPaDgrd7DH3HnnLCmyuhsx0 1kA7GYVAJhPxMDWugsfg5Yj09CASwXCk1cEHsQDE94YCszO+1gJpeH9YzJDyHzfG3zwx Jq0h+rtlQtEOADzPe+0GVpRqG3YdD+3qZiPwrh44OtWdDdtokFpdBFwSJYhj6l4yMEec 203RD6uUkum1HinJpf7pE61h31QASQHYQJQNgXLHQ4m44+XUEK8CujqSUswxcMG02smf 5V5g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qhMfyoMh; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61788-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61788-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCXiE34bj7hR0VGNP+FcF8wt7WDKJIdI3OH9rsqUV4ijyK5s/90tlag/ngnr77JtsG6MOYgCdQLjtvr2Ts3TDsuvroR0vA== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.03.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:03:43 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 02/12] spi: s3c64xx: define a magic value Date: Mon, 12 Feb 2024 14:03:21 +0000 Message-ID: <20240212140331.915498-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702482731117709 X-GMAIL-MSGID: 1790702482731117709 Define a magic value, it will be used in the next patch as well. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 6f29dca68491..6ff3b25b6feb 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -78,6 +78,7 @@ #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) +#define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) @@ -108,7 +109,8 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) +#define TX_FIFO_LVL(v, i) (((v) >> S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT) & \ + FIFO_LVL_MASK(i)) #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ FIFO_LVL_MASK(i)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) From patchwork Mon Feb 12 14:03:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 199831 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2450147dyd; Mon, 12 Feb 2024 06:09:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IFq3LKtGyHYH2Y30jsUp+jTkh9AAzt7LvtaRUxOtU/srRHb+rbE5nZWHPAdzvGgK+KXP9YH X-Received: by 2002:a37:ef19:0:b0:785:b247:e723 with SMTP id j25-20020a37ef19000000b00785b247e723mr6374782qkk.40.1707746992331; Mon, 12 Feb 2024 06:09:52 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707746992; cv=pass; d=google.com; s=arc-20160816; b=mBmpzeCgqJOyTSEsa2ebeZR6+YmYhlHOEaFM4j2tuS/r/1TaL/cGQL8fNcauXQSHDH 2ntub06+ANKnqO5Bj52sEdTMiMjufk7dc8Jzr305E7JAP4HBaZHFs61KZBaInVnOna8O gi39LBFx+GDJ7gNeCDJAfDj+W8xWs7MNrb7yAxmPmrg/KDKw5AmJdWSbqulO9QutnWK8 jVDkws4EGPcwU97p60INVAZCgKQt3jwmwY8vX+uwDkD8WqMT/g/fzIizwl/YW0LI1pUc YLyZkcp8ivOVPR3dYIRqCz0NbquLccjVrQVhR6oPkCepvce6JWIWq8pvLpl78pL76gEn X3Ow== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=3UCCMmhJgpPZWbOVTAspr0xjn11XvYuA37qXyTRrUkA=; fh=IPXl4HH40cO1CC0qC0ul5wm0Tk4ijZpTzXRgfOj3MDg=; b=QLDyJi2CBBlEmLOhkoUbJfhT6K133zpklzGMJ2GI8Y3CbI+XWbEhyQnYfBN2STeCzZ aul4ARYl/ODcPQidQq3JNyA+LZqcT3QCNydVlSC60ub2/myS/yxkyB5bhB2yzAHR6dG6 PRtyfDVrO88HOXG2r3pItGUKdbPhvxKJICW8jWATzY3X2gTEY6fq5DWocjuv/KMiWb+1 KRgJkZdlyybam02WzXKvwj8xRYf6qbh7Hs3D7oIgSaLAbfB5IpwsqvN8rXTnK7U8pA5K y5oTC+QbkDf5zvUOp/emYNPKQUCb9YfoX77bfYMqkTilau0ya970uFoMdT2DpLROhObH l1Yg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XWAQxyB8; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61789-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61789-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCVbsCI0ST8IGmXslwgZEP2jjG3vonyBcDIKwnYl4GO5pghxtoLTMzQZA5Q3+lBDfLe/WpNAor74gHVpnsqacxx7ISU3zg== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.03.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:03:47 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 03/12] spi: s3c64xx: allow full FIFO masks Date: Mon, 12 Feb 2024 14:03:22 +0000 Message-ID: <20240212140331.915498-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702510465511186 X-GMAIL-MSGID: 1790702510465511186 The driver is wrong because is using partial register field masks for the SPI_STATUS.{RX, TX}_FIFO_LVL register fields. We see s3c64xx_spi_port_config.fifo_lvl_mask with different values for different instances of the same IP. Take s5pv210_spi_port_config for example, it defines: .fifo_lvl_mask = { 0x1ff, 0x7F }, fifo_lvl_mask is used to determine the FIFO depth of the instance of the IP. In this case, the integrator uses a 256 bytes FIFO for the first SPI instance of the IP, and a 64 bytes FIFO for the second instance. While the first mask reflects the SPI_STATUS.{RX, TX}_FIFO_LVL register fields, the second one is two bits short. Using partial field masks is misleading and can hide problems of the driver's logic. Allow platforms to specify the full FIFO mask, regardless of the FIFO depth. Introduce {rx, tx}_fifomask to represent the SPI_STATUS.{RX, TX}_FIFO_LVL register fields. It's a shifted mask defining the field's length and position. We'll be able to deprecate the use of @rx_lvl_offset, as the shift value can be determined from the mask. The existing compatibles shall start using {rx, tx}_fifomask so that they use the full field mask and to avoid shifting the mask to position, and then shifting it back to zero in the {TX, RX}_FIFO_LVL macros. @rx_lvl_offset will be deprecated in a further patch, after we have the infrastructure to deprecate @fifo_lvl_mask as well. No functional change intended. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 40 +++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 6ff3b25b6feb..338ca3f03ea5 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -3,6 +3,7 @@ // Copyright (c) 2009 Samsung Electronics Co., Ltd. // Jaswinder Singh +#include #include #include #include @@ -109,10 +110,10 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT) & \ - FIFO_LVL_MASK(i)) -#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ - FIFO_LVL_MASK(i)) +#define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \ + __ffs((sdd)->tx_fifomask)) +#define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \ + __ffs((sdd)->rx_fifomask)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff @@ -136,6 +137,10 @@ struct s3c64xx_spi_dma_data { * struct s3c64xx_spi_port_config - SPI Controller hardware info * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. + * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. * @clk_div: Internal clock divider * @quirks: Bitmask of known quirks @@ -154,6 +159,8 @@ struct s3c64xx_spi_dma_data { struct s3c64xx_spi_port_config { int fifo_lvl_mask[MAX_SPI_PORTS]; int rx_lvl_offset; + u32 rx_fifomask; + u32 tx_fifomask; int tx_st_done; int quirks; int clk_div; @@ -184,6 +191,10 @@ struct s3c64xx_spi_port_config { * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data * @port_id: Port identification number + * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. + * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. */ struct s3c64xx_spi_driver_data { void __iomem *regs; @@ -203,6 +214,8 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; + u32 rx_fifomask; + u32 tx_fifomask; }; static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) @@ -1183,6 +1196,23 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; } +static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) +{ + const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; + + if (port_conf->rx_fifomask) + sdd->rx_fifomask = port_conf->rx_fifomask; + else + sdd->rx_fifomask = FIFO_LVL_MASK(sdd) << + port_conf->rx_lvl_offset; + + if (port_conf->tx_fifomask) + sdd->tx_fifomask = port_conf->tx_fifomask; + else + sdd->tx_fifomask = FIFO_LVL_MASK(sdd) << + S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT; +} + static int s3c64xx_spi_probe(struct platform_device *pdev) { struct resource *mem_res; @@ -1231,6 +1261,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } + s3c64xx_spi_set_fifomask(sdd); + sdd->cur_bpw = 8; sdd->tx_dma.direction = DMA_MEM_TO_DEV; From patchwork Mon Feb 12 14:03:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 199832 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2450363dyd; Mon, 12 Feb 2024 06:10:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IHicKj84jfZv5N+H7oX/0MPgDZa5K/CytboMsSw0YI2XlG+iRSEhX/zQP9eNlTBTqI1qXiQ X-Received: by 2002:a05:6402:2293:b0:561:a444:8e49 with SMTP id cw19-20020a056402229300b00561a4448e49mr2426930edb.0.1707747007180; Mon, 12 Feb 2024 06:10:07 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707747007; cv=pass; d=google.com; s=arc-20160816; b=Bcqbx2Pr5FC10SuIAMi+18m2VnF+M14rLpR7k0aVE5C7anB4KMmXmXQzy1tZ5zZUK2 i/CT6z0BWIVtdFZ6dr452fTbso35AvpJxp6XkNqJKV78OMsdd5e0vpZXC677B6AQ9joL zP92R9K/TDArqaFuXGgy6r/QyLEHpvap/gA6yhGi9bZo8TP/LreCBHSscQsZTc3QDVw+ H7AqqDV46KZ4SQ2UaSdLwvWyYeDRfzqiIZTEXAULuTdTqz6cfad+9Ef0XUBazDkliA6c zUOnNzIWx84wY82PO3Qx6e//dNJlFZz573fSEGzAL4v5j16d0MhfhSvUgx8fblA0MT8R HTVA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=NGH79biiaV6ew1Z0cXAg/aqisf4dNxuTnwEmj4C4qiQ=; fh=Ipl3V1/Rsg3S9lcBXzWsPF02ule+XgzvRoMRb14W0cs=; b=Jh1MZLflF7QQljDqRwNbBLRxuA2uAoFvA40uKVLN9lLoiRUqxNEdlTAxhUIw9/U4me 9yyKtjVAB6hcFn0u7iRD86vPJ+RyOKTqSiZpKrYYOzvYrazC6kGsByLdJ0mmym7ptej4 5PeC4GxiHxrkevzpq/0iJFyJ6g/eLUH/YuIAFDQpQ0KleI5cJvwYT3zo5vbRFsmQpMG1 ov2SGpdWaqZn/NJs1WsXBBEZ2qCdrn48wvhrIQJNonYL5mq44f0TQP5jwm5JA8jU/u+o TV3xADKNlM+XODBBUIZYGdtHKCxElUG0FQPw4+gA0D/mNU/AWIWB8sPDiCkNLn4ryiN8 +nYQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KJOCP7YT; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61790-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61790-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCW66RWE9gvpar3THjhVFi2cXd670mlY+Rbg/IMa84XhkVS9BIKyh4byvSpRrbts5iBn+lcmyl6DlLNSrj5r8o62O9xfUw== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.03.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:03:49 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 04/12] spi: s3c64xx: determine the fifo depth only once Date: Mon, 12 Feb 2024 14:03:23 +0000 Message-ID: <20240212140331.915498-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702525940876764 X-GMAIL-MSGID: 1790702525940876764 Determine the FIFO depth only once, at probe time. ``sdd->fifo_depth`` can be set later on with the FIFO depth specified in the device tree. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 338ca3f03ea5..72572e23cde5 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -191,6 +191,7 @@ struct s3c64xx_spi_port_config { * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data * @port_id: Port identification number + * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's @@ -214,6 +215,7 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; + unsigned int fifo_depth; u32 rx_fifomask; u32 tx_fifomask; }; @@ -424,7 +426,7 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host, struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); if (sdd->rx_dma.ch && sdd->tx_dma.ch) - return xfer->len > FIFO_DEPTH(sdd); + return xfer->len > sdd->fifo_depth; return false; } @@ -548,7 +550,7 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, void __iomem *regs = sdd->regs; unsigned long val = 1; u32 status; - u32 max_fifo = FIFO_DEPTH(sdd); + u32 max_fifo = sdd->fifo_depth; if (timeout_ms) val = msecs_to_loops(timeout_ms); @@ -655,7 +657,7 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, * For any size less than the fifo size the below code is * executed atleast once. */ - loops = xfer->len / FIFO_DEPTH(sdd); + loops = xfer->len / sdd->fifo_depth; buf = xfer->rx_buf; do { /* wait for data to be received in the fifo */ @@ -792,7 +794,7 @@ static int s3c64xx_spi_transfer_one(struct spi_controller *host, struct spi_transfer *xfer) { struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); - const unsigned int fifo_len = FIFO_DEPTH(sdd); + const unsigned int fifo_len = sdd->fifo_depth; const void *tx_buf = NULL; void *rx_buf = NULL; int target_len = 0, origin_len = 0; @@ -1261,6 +1263,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } + sdd->fifo_depth = FIFO_DEPTH(sdd); + s3c64xx_spi_set_fifomask(sdd); sdd->cur_bpw = 8; @@ -1352,7 +1356,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n", sdd->port_id, host->num_chipselect); dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", - mem_res, FIFO_DEPTH(sdd)); + mem_res, sdd->fifo_depth); pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); From patchwork Mon Feb 12 14:03:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 199833 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2450707dyd; Mon, 12 Feb 2024 06:10:39 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXX4ySnUAlxWQFqlMEKgWB1KPIElSb6S40f1Plluc7xphghmuM5J6rmvFYjpVzdieIfAeIKUznEv/d3ZlxaglCx/A+Slg== X-Google-Smtp-Source: AGHT+IGbMfZAvdj8pgsv+Nn4wo31zhDLgVvcQ0YrzOFlqglPVM0V2SWh8hTVY5oxnCan8X9PHQmD X-Received: by 2002:a2e:9848:0:b0:2d0:5543:dcd3 with SMTP id e8-20020a2e9848000000b002d05543dcd3mr4235732ljj.3.1707747039559; Mon, 12 Feb 2024 06:10:39 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707747039; cv=pass; d=google.com; s=arc-20160816; b=XMhnfd/YSBQTdgRXmKEZtPh/bYIIgVCtjaFVZtzk8ydQcRHD5P5QwjAtKdjgN5CBNM wzG9/HCdccPjoYEzekv2pH5jsATmjzGfcPf5FRD62IB2m1nCWvSlnpAg2zlsFkzfjVGD aPgoxahv9ZSBGEJ6QPPnuVGarJ6WZ8yYaMbJJUavYLyz1BZq712g44mE5WfPLSLAxs2G uKYtHSix2PBcmprVJjOOaK0PutWVGe/KrcG3GJiVm9vr3t+ruQSWO+t87nxCAL+yiChC NR2BK2HXmPCSQc1LFORqTfk1ZsDOAAEKSE6w6aMimeCHGQ0MlQ/zHCOGxZnbWmEPUBwV ptkw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=VwdchoB+O7sv0WsEEn/4CtktSHX1kT968ZrMEmEikx8=; fh=VECY4iavURXFko9Si2TFmZ3uAd+0R9vjgKcZzpt113Y=; b=uZ+J9bwe/nQEpMudLDaQFE6WLv5mWJKBBsBnOVYxOQq+Tr3Sz2ACRRNy4IHpzA3/rF 1Kxfeo9x5nOqatyZp4kkjTu1XoA8b5KHTwIRZFcO2cSEXSc9jYP0mCmYxt7HY7hsYamc qX9KtsBqWnAb3jMkOIsTl3m297Y3BXjR8bH21LRwSd/NXn+x52GDyoiqVukoKLHNyzw0 2cUXW4r36HiKi6j6EjdylQ5X7pI2zfWvDkDFz6hK/kkpIc0b4wWuEsyS6N2Z9vNaKEYM FED9zJuWnrM1BebM8DCsjxPxcwArnEdO1XOfwx9gM0yERB38Qud9xGDicttE+bxe+LRK QCXg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JRE8NM8b; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61791-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61791-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCWPY4cQ3qDVtYwsR2axwliqx+HZ0JEC9apRTEBa9R9M1t55LCwwLKW/GwvEveRO87KLHV45OxVKCeHOeQKA3WpoNsV1WQ== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.03.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:03:52 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 05/12] spi: s3c64xx: retrieve the FIFO depth from the device tree Date: Mon, 12 Feb 2024 14:03:24 +0000 Message-ID: <20240212140331.915498-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702559456860866 X-GMAIL-MSGID: 1790702559456860866 There are SoCs that configure different FIFO depths for their instances of the SPI IP. See the fifo_lvl_mask defined for exynos4_spi_port_config for example: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, The first instance of the IP is configured with 256 bytes FIFOs, whereas the last two are configured with 64 bytes FIFOs. Instead of mangling with the .fifo_lvl_mask and its dependency of the DT alias ID, allow such SoCs to determine the FIFO depth via the ``fifo-depth`` DT property. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 72572e23cde5..b1c63f75021d 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1263,7 +1263,9 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } - sdd->fifo_depth = FIFO_DEPTH(sdd); + if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", + &sdd->fifo_depth)) + sdd->fifo_depth = FIFO_DEPTH(sdd); s3c64xx_spi_set_fifomask(sdd); From patchwork Mon Feb 12 14:03:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 199834 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2450993dyd; Mon, 12 Feb 2024 06:11:04 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVabmcKGaMfXyUZORbJ8kRucy4igDQh9v72+zKofoxBMtR+zSZBzAAtASZs2l4MwKOV91zB28u8AdZmQlQU3xTZEbgCUw== X-Google-Smtp-Source: AGHT+IG/21TzImyTSk0qzftPrk0P4B8JrEVugy3F3VwoYdmPeh6dXy/hRK/gXy+osh1xR9F+PRTs X-Received: by 2002:a05:6870:970a:b0:219:a686:4b8f with SMTP id n10-20020a056870970a00b00219a6864b8fmr9093183oaq.32.1707747064757; Mon, 12 Feb 2024 06:11:04 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707747064; cv=pass; d=google.com; s=arc-20160816; b=kjoOI7UHq1j9EPxfv1w8CdBVmHG5LU1GSgXWuhJwu3VFOYgV7ONm7/f+saEDL0KK+t dSQVgAQCXisSQFmC3wK6XpmL6+tk0jqgno87U4Zd3kKJ1QyhMUH2e9b/WkfZDO0eoWaa a4/pFk+rZHyJCLXzsEh7sqTddU6SCMygZ6KxGPr5wpwn/2gOF0wD4WZTMa/8WkE4eebS ARIj4y0HZ+3MAjY1hl/91MpMX5KN3aiBbM9lwvR1UhoQuQBkaHHtAynjewdMTEl+oICr OKFH2LCdO1zz1iCVzpCSo6lfdLlUo7KlQF6eNpJT5LMUkbO84OD+bDwAWOLd78+ptdue obQg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=BwyqOxCBKuWUKHqwJM3+S1e7+XETwlW6DJMJjNuYLS0=; fh=uY6muPE0Jp2B8jvL+JmKwHHaGTYSyd2q+wuXccZClDY=; b=eP2gJkrrjsTVqLOvwNjRLRnvPlmujYqZHURawlZgYn+DAjHuwWfRClR6WXashu/d5O X4JvMXV48eT3rT79O/araP9YAcH79VtjCNs/a5c3CIRKtqDjeePScXC+RdTQ7+XrxuPJ wb54QtUqAdYiIK8nvD//qJKlDDK/QcANjILAS9NE9T/b0roCABpZyFU3GoiL4hvAd+TQ vD8jAckHfMxclQSLX3UQQ525KzHvaxuIFEthsKZNnhk6Y+b53naWpA0SuVKAHGEUcXKd eKNm3FRJRCyEDGY7adgcFYMb16u3ZHMpg+wJNQvUuhs8VkcqzIDiWQwMId+Fb4AzqQ3d cqTg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=egvck0U6; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61792-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61792-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCWxxZ/ZGuwg6rwpeH2ohgKiWjnxE97C8B2gdGO8HeuO+RHnUV7GI9Dprtr1Xz91VacZbC0SX88q44BYm0R2ej4bDfwN2Q== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:03:54 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 06/12] spi: s3c64xx: allow FIFO depth to be determined from the compatible Date: Mon, 12 Feb 2024 14:03:25 +0000 Message-ID: <20240212140331.915498-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702586238986208 X-GMAIL-MSGID: 1790702586238986208 There are SoCs that use the same FIFO depth for all the instances of the SPI IP. See the fifo_lvl_mask defined for gs101 for example: .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, Instead of specifying the FIFO depth with the same value for all 16 nodes in this case, allow such SoCs to infer the FIFO depth from the compatible. There are other SoCs than can benefit of this, see: {gs101, fsd, exynos850, s3c641, s3c2443}_spi_port_config. The FIFO depth inferred from the compatible has a higher precedence than the one that might be specified via device tree, the driver shall know better. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index b1c63f75021d..68f95c04d092 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -137,6 +137,7 @@ struct s3c64xx_spi_dma_data { * struct s3c64xx_spi_port_config - SPI Controller hardware info * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's @@ -159,6 +160,7 @@ struct s3c64xx_spi_dma_data { struct s3c64xx_spi_port_config { int fifo_lvl_mask[MAX_SPI_PORTS]; int rx_lvl_offset; + unsigned int fifo_depth; u32 rx_fifomask; u32 tx_fifomask; int tx_st_done; @@ -1263,8 +1265,10 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } - if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", - &sdd->fifo_depth)) + if (sdd->port_conf->fifo_depth) + sdd->fifo_depth = sdd->port_conf->fifo_depth; + else if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", + &sdd->fifo_depth)) sdd->fifo_depth = FIFO_DEPTH(sdd); s3c64xx_spi_set_fifomask(sdd); From patchwork Mon Feb 12 14:03:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 199835 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2451201dyd; Mon, 12 Feb 2024 06:11:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IGXx45ijfHtmH/Ow2RlA1jjfET3VD3KnTUY21KMI2uJGLgNv/La8e8sc0e/OESQ/mPcORXi X-Received: by 2002:a05:6214:1d2f:b0:68c:88b3:4cb6 with SMTP id f15-20020a0562141d2f00b0068c88b34cb6mr7874580qvd.63.1707747083592; Mon, 12 Feb 2024 06:11:23 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707747083; cv=pass; d=google.com; s=arc-20160816; b=AB+DI+fVcBCuRztX8Kw9bn+MOsK8g0wtnwVc/qEGAfBIg8f/Q612oGcA3nyp2v+gET WJfLyg6uW9s2HswwumJUWwl6mpEL3woRoY/cNyBwh2W1gQJgfjVAsAeuaolZ9zxOKXXr 2t3uSqTh9YaISFtIQCOuOl1Kzj74HKu9UocPeCptEtSqLAEILcbIj5xaqGplo7yG02Bi 3yYG9/Z740dzzpPv0GWpYh5HNcLV2JzIfJQAUTALkltHR/o9kFkBgyxPplRyIciR6OmM 05d0wZDXkH322PBtUsG1ZvB96b1X471wiGMT8r+H7Lvh+1xNKl2V3e12eqzWjR6aycJI wQcg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=TbvKAanWHb5NHCc78DYWj3IudYbRJBQeeD4twXOiMjs=; fh=pwhOJnsZWmTBbbiCAbI0MCRYF/EhsGqRdqZ2tL2xwCA=; b=ZMhLqM90LD8piqtMU8q4WeFgOuDmaNk32Ym8bp/OlCe2MzVvDgrKj3GsrpCAg/mXsV OKHjgVSSFCaNOZzdpF1ghxU6JbQKgd0vdLPe4Z3Tsxk/JXmDfsW++4KEWXTxweZsTAIN qejzFg68abifq8vCqDdTatMPCZtZbo+hwBGyyuh7VUM7gRScom+Vl1RGgouCnOS+OPnL LpZRs/7MU71Dxo6kBXYOX7MBSN5Kkvt+F4rEZBP2oz6haoCP6+RGgrNCeBLQaBK6F7n1 UxObARFt6aOIxjIYwK4qqiKwceCpZm3foLIBqvz6L6zGND+zvJ9T8Nb/Z1ZG1VUWHVMy 7Dlg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kdlNehZG; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61794-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61794-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCWuzGGusFlOPldDGX4B8AyyBtaMkLdKY/44XI3Eq0r6SeOAMSggBiXOW4IVf+sSw2BragKDNKl4tekGnnYN5WT3znPKTA== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.03.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:03:56 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 07/12] spi: s3c64xx: let the SPI core determine the bus number Date: Mon, 12 Feb 2024 14:03:26 +0000 Message-ID: <20240212140331.915498-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702606002598281 X-GMAIL-MSGID: 1790702606002598281 Let the core determine the bus number, either by getting the alias ID (as the driver forces now), or by allocating a dynamic bus number when the alias is absent. Prepare the driver to allow dt aliases to be absent. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 68f95c04d092..ac47755beb02 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1279,7 +1279,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->rx_dma.direction = DMA_DEV_TO_MEM; host->dev.of_node = pdev->dev.of_node; - host->bus_num = sdd->port_id; + host->bus_num = -1; host->setup = s3c64xx_spi_setup; host->cleanup = s3c64xx_spi_cleanup; host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; @@ -1360,7 +1360,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) } dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n", - sdd->port_id, host->num_chipselect); + host->bus_num, host->num_chipselect); dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", mem_res, sdd->fifo_depth); From patchwork Mon Feb 12 14:03:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 199836 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2451390dyd; Mon, 12 Feb 2024 06:11:42 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWte0mOMHnptsUqSx7SeyQAC5FJ7dVqNRA64KdX8y6kx+6m1nGwpIZ7c9BMan1/WSQj5rZLUbgnjdo6QvMpDm5cdcsFXQ== X-Google-Smtp-Source: AGHT+IFe4xmS+hhLuoRNLlU9MLpjNBbHob52GvEDTVXDzRamLDbJmJ8INH+tILGl34J2UEdjt5k1 X-Received: by 2002:aa7:c543:0:b0:55f:fe4e:1f17 with SMTP id s3-20020aa7c543000000b0055ffe4e1f17mr4857692edr.7.1707747102266; Mon, 12 Feb 2024 06:11:42 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707747102; cv=pass; d=google.com; s=arc-20160816; b=A5kJGySbfiLRZwA1PcHaPg4lI6B2bNoMRO4exhE2nDPxTS/WY9uaaR4rD62nOFSPZL sKqOStnlLyHtdcIKDHkmw06h/wc8wYuqjGMBKcOmHDKEaW0Fg71W43TgVXqEwb6Yh/AZ YASX2y0w4AogL2n5ye9RL9WSH+AYzf3C7FLKkxEV/1eSIL45ENQfIy+VRBJyL8dzT0b/ WB1U5A087M7Or0x1D6loSigBVCxnckLLehXa6ypodhuW3zR5b00iHA5cnBqpTMXuhVwX Zv34WTLCcwzGKWAfZper0Zr5pwBzzcPrdI4DJ4njxnoCfXUrk30Dfc20ChfyTKGZq3It i8XQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=OTrzZqM2Ss1d3JLf/TDWyYpLJTs2h0kZukw/0ZYCnhU=; fh=r3R+fAu6QuDHxKlPG8xvpBZOogImXO+RqODWV5TT0z4=; b=KMf79510PRjvewk5ceKbZOaA27KJt49B2XfWmPYZ452Dq+1y9rxcmrZpfVxmNhXKXh J0K2wTJSJ6LgIQZPdXjGrXgFBDdGaXm7x5jFYUH6Zvru43zr2yhr3+OOspsyHbyVFQSD pjKfOZOd5ZAMFxz7bwRh9RZfkrGNzmHiTJmgmzXIBiV6A4dEhJZHAvCuagh/6WT+Ir3b 4YOVUi65qBjVD3FRYo6K55U42k/V07zZhq6YuiVNabNHfdryrbf4Qw9I5lVa63qw62Y/ IETPyf2fw7PTGm3PET6sj2uBZshLv8iZm0aJmMexjii806bn900J2nLZjzue1paxB0DK 8n4Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KTz7MiLs; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61795-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61795-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCXbLdOJ1quZksmJDb8WOftxgu53IGDdpQWTCt/SCcTFk0+UPa3NkfLLkPwNhhrA1QYJXuJLRllwxVFv8Tr3v8t0D3QoGw== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.03.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:03:58 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 08/12] spi: s3c64xx: introduce s3c64xx_spi_set_port_id() Date: Mon, 12 Feb 2024 14:03:27 +0000 Message-ID: <20240212140331.915498-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702625697338526 X-GMAIL-MSGID: 1790702625697338526 Prepare driver to get rid of the of alias ID dependency. Split the port_id logic into a dedicated method. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 37 +++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index ac47755beb02..40de325bd094 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1200,6 +1200,27 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; } +static int s3c64xx_spi_set_port_id(struct platform_device *pdev, + struct s3c64xx_spi_driver_data *sdd) +{ + int ret; + + if (pdev->dev.of_node) { + ret = of_alias_get_id(pdev->dev.of_node, "spi"); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to get alias id\n"); + sdd->port_id = ret; + } else { + if (pdev->id < 0) + return dev_err_probe(&pdev->dev, -EINVAL, + "Negative platform ID is not allowed\n"); + sdd->port_id = pdev->id; + } + + return 0; +} + static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) { const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; @@ -1252,18 +1273,10 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->host = host; sdd->cntrlr_info = sci; sdd->pdev = pdev; - if (pdev->dev.of_node) { - ret = of_alias_get_id(pdev->dev.of_node, "spi"); - if (ret < 0) - return dev_err_probe(&pdev->dev, ret, - "Failed to get alias id\n"); - sdd->port_id = ret; - } else { - if (pdev->id < 0) - return dev_err_probe(&pdev->dev, -EINVAL, - "Negative platform ID is not allowed\n"); - sdd->port_id = pdev->id; - } + + ret = s3c64xx_spi_set_port_id(pdev, sdd); + if (ret) + return ret; if (sdd->port_conf->fifo_depth) sdd->fifo_depth = sdd->port_conf->fifo_depth; From patchwork Mon Feb 12 14:03:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 199837 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2451718dyd; Mon, 12 Feb 2024 06:12:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IGNe/oTVTcBnaM91gx84arRJL1xMYE13lsBqohauCU3w1q/1QJjYcR+NHozKzbnGPC7lcpP X-Received: by 2002:a17:906:f111:b0:a3c:cd77:87f9 with SMTP id gv17-20020a170906f11100b00a3ccd7787f9mr1005912ejb.58.1707747133243; Mon, 12 Feb 2024 06:12:13 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707747133; cv=pass; d=google.com; s=arc-20160816; b=evItMciKWVocYj+6xnNYffTvXJweIjdIkYRVSXNSCUy1LOfcKCSnH2Tc+0gVSMK8Hf wqBoOwRYM83ussDFlJUSBsM0EXol9BNqZGgTyx/mJ9kCruTLhu9Dcsr2oAnMUQxvfDWX OcEs7weI4fCQmvtMkra9rhG3bRrZJpgA5mduQWVnA0S5yMoBnStUBroauN/gUbOn6eAj XyxNCWreyliOrt1vyoOO+rNhKOC7fMUfX9fD3T3Nsey7081yQ+isz7iC7WADPXOyASAr li/VSIG14+YB9yeX5vcN3tInxCm9WVPgCKgGz5yp5Ysz4u+m+bqFLiMALMiHqP3wk3Jv 1Dmw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=mLhU5Fpjpt+G1J97uCF7eZiB9eQQAYSw34EErx851iQ=; fh=C3DXo+lVeSBD23TIokvZmLfzwPjPp8uoUbgrZy7DL94=; b=Cxni42DL7IhtbLGVq95a9HpIK3Dhk97QVhJfZTE8gUNWzIbWLADx/VcHliZ+teuRU6 C6a0jM24JuPMTt1Ctp4hSgB+am8forxbjVt8yvfcCCWTs9ZStufQkdg3TmIvfli/rFjm tY4HphiABdUYL5PTgfcjCb3g8JddEPZwcFrQkMWy/1ovc2nk1gFCjMLmK5kVVwk/A6XJ jvXutAnOU5PhU8Yuqe+J0185aQVIYTF3O7kmM+ZU2CkEsFld12vFpzmVg7TFd/4dMZSa gn3rJFpqhBBi7eYX/PiIR8XVfIYMLLTprhp5ge+zlHjtr6SzQ9QTVq6li+WakqJ+cNXK LP8w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D3snOylN; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61796-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61796-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCU+d4JvUkMGPTHq4Ep+ODmwhG3esZJW8QXWaqYZu3JVThxdV4Q88UR4CsY1X79MZtcWhcuGLSJfZzNN5EsdUjXDPxW/mA== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:04:00 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 09/12] spi: s3c64xx: get rid of the OF alias ID dependency Date: Mon, 12 Feb 2024 14:03:28 +0000 Message-ID: <20240212140331.915498-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702658172714786 X-GMAIL-MSGID: 1790702658172714786 Compatibles that set ``port_conf->{rx, tx}_fifomask`` are now safe to get rid of the OF alias ID dependency. Let the driver probe even without the alias for these. With this we also protect the FIFO_LVL_MASK calls from s3c64xx_spi_set_fifomask(). Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 40de325bd094..d2d1c9767145 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1203,8 +1203,12 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( static int s3c64xx_spi_set_port_id(struct platform_device *pdev, struct s3c64xx_spi_driver_data *sdd) { + const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; int ret; + if (port_conf->rx_fifomask && port_conf->tx_fifomask) + return 0; + if (pdev->dev.of_node) { ret = of_alias_get_id(pdev->dev.of_node, "spi"); if (ret < 0) From patchwork Mon Feb 12 14:03:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 199859 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2470937dyd; Mon, 12 Feb 2024 06:44:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IHucyFZKkHBb5MBx8wPlh6MtR+TOTKOkI9nMf0anxNQODL2l8Hn+57ripZdmfPcPTwjUsYg X-Received: by 2002:a05:6a21:3a44:b0:19e:cbe9:64b with SMTP id zu4-20020a056a213a4400b0019ecbe9064bmr2697288pzb.50.1707749079418; Mon, 12 Feb 2024 06:44:39 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707749079; cv=pass; d=google.com; s=arc-20160816; b=h2g5JC7F0ITACY21He4wus+Bcw0XJWiFhia6ArpB2vrsuPOjPdsEvoaP27RVkfjAEI D/qIB8CrV343B6v66YV33xR2QNgTasaZq3NhxJnw/KU+JZmBQqM47O94zjpnBSCkSg8V fpP9vsVS1MDP8TgBauJYsKWNJ3Zf2w5PQdPG7InVupDhGVu5WUHMYxe0oOU23BbguKoW dleyAUWg2zMe0JoLZa96sS7uK376ukRFRtpDknnkn1t5pJNde7yT3vCxGIDCgVY+T8R9 7zFZSz561rGlx/k8X0VClauXxaODWG625DEFNp/xsxVbhlgjv8tfpNVk3Df5NyHAxlBc 4jww== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=fm5OjWDCnevgUex+kbg78oFWzlDeXhj9v/6Ap/z4iAc=; fh=W9vt6ZOxGHScl5IUmRz/EaEBGsyBGARiOsjmAgC3yCU=; b=jiDOWE0R3eN1sl2FL8ZmQNjXmd9W4JeLPKs4uyj5XTe94LKouPVU/AInJP1hl3celB Mscf5EHK7EC9kZErpTrO3AtGsGmlvXluepVVpCjmTaWYJ5MfcazWZp0UEooVwB0Zrhr8 G508tXgigiUTWMcn5OJWarqhThSGSRvAUFFqLeej48otiBfqy55poUq8MQ9gpK67S4fw VbNj2J4laE/YfLEdd4ZaJzZmLixt5viD+J9a3oUB7uSRqyCndI4rHLe7Pj/Xau2XbJKc bpxbXSRzxiQP4BBWXaF7DqXRAHwBUbezySkiBX279It+8zjGieESSeenNWi2iraZbVjU Tzxg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="p/YU6no2"; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61797-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61797-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCWyRnm8BAbOA2gRs6szKcRuyimIIxqLIKuuA+q0BmQtcZ8mhEZQ/S5IHr4t5YVH1kvUNhffvMj/drSXlrRUlbQXDMo82g== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.04.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:04:01 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 10/12] spi: s3c64xx: deprecate fifo_lvl_mask, rx_lvl_offset and port_id Date: Mon, 12 Feb 2024 14:03:29 +0000 Message-ID: <20240212140331.915498-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790704698432026460 X-GMAIL-MSGID: 1790704698432026460 Deprecate fifo_lvl_mask, rx_lvl_offset and port_id. One shall use {rx, tx}_fifomask instead. Add messages to each port configuration. Suggested-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index d2d1c9767145..128f4a7c4bd9 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -135,8 +135,8 @@ struct s3c64xx_spi_dma_data { /** * struct s3c64xx_spi_port_config - SPI Controller hardware info - * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. - * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @fifo_lvl_mask: [DEPRECATED] use @{rx, tx}_fifomask instead. + * @rx_lvl_offset: [DEPRECATED] use @{rx,tx}_fifomask instead. * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. @@ -192,7 +192,7 @@ struct s3c64xx_spi_port_config { * @rx_dma: Local receive DMA data (e.g. chan and direction) * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data - * @port_id: Port identification number + * @port_id: [DEPRECATED] use @{rx,tx}_fifomask instead. * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. @@ -1508,7 +1508,9 @@ static const struct dev_pm_ops s3c64xx_spi_pm = { }; static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 13, .tx_st_done = 21, .clk_div = 2, @@ -1516,14 +1518,18 @@ static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { }; static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7F }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 13, .tx_st_done = 21, .clk_div = 2, }; static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7F }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1531,7 +1537,9 @@ static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1541,7 +1549,9 @@ static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1551,7 +1561,9 @@ static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1562,7 +1574,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 4, @@ -1573,8 +1587,10 @@ static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 4, @@ -1586,7 +1602,9 @@ static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { }; static const struct s3c64xx_spi_port_config fsd_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1597,8 +1615,10 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { }; static const struct s3c64xx_spi_port_config gs101_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + /* rx_lvl_offset is deprecated. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.04.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:04:02 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 11/12] spi: s3c64xx: switch gs101 to new port config data Date: Mon, 12 Feb 2024 14:03:30 +0000 Message-ID: <20240212140331.915498-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702682684137530 X-GMAIL-MSGID: 1790702682684137530 Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port config data. Advantages of the change: - drop dependency on the OF alias ID. - FIFO depth is inferred from the compatible. GS101 integrates 16 SPI IPs, all with 64 bytes FIFO depths. - use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial masks is misleading and can hide problems of the driver logic. S3C64XX_SPI_ST_TX_FIFO_RDY_V2 was defined based on the USI's SPI_VERSION.USI_IP_VERSION register field, which has value 2 at reset. MAX_SPI_PORTS is updated to reflect the maximum number of ports for the rest of the compatibles. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 128f4a7c4bd9..784786407d2e 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -20,7 +20,7 @@ #include #include -#define MAX_SPI_PORTS 16 +#define MAX_SPI_PORTS 12 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) #define AUTOSUSPEND_TIMEOUT 2000 @@ -79,6 +79,8 @@ #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) +#define S3C64XX_SPI_ST_RX_FIFO_RDY_V2 GENMASK(23, 15) +#define S3C64XX_SPI_ST_TX_FIFO_RDY_V2 GENMASK(14, 6) #define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) @@ -1615,11 +1617,9 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { }; static const struct s3c64xx_spi_port_config gs101_spi_port_config = { - /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ - .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, - 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, - /* rx_lvl_offset is deprecated. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.04.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:04:04 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 12/12] spi: s3c64xx: switch exynos850 to new port config data Date: Mon, 12 Feb 2024 14:03:31 +0000 Message-ID: <20240212140331.915498-13-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790702694825970225 X-GMAIL-MSGID: 1790702694825970225 Exynos850 has the same version of USI SPI (v2.1) as GS101. Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port config data. Backward compatibility with DT is not broken because when alises are set: - the SPI core will set the bus number according to the alias ID - the FIFO depth is always the same size for exynos850 (64 bytes) no matter the alias ID number. Advantages of the change: - drop dependency on the OF alias ID. - FIFO depth is inferred from the compatible. Exynos850 integrates 3 SPI IPs, all with 64 bytes FIFO depths. - use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial masks is misleading and can hide problems of the driver logic. Just compiled tested. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 784786407d2e..9fcbe040cb2f 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1576,10 +1576,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { - /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ - .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, - /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ - .rx_lvl_offset = 15, + .fifo_depth = 64, + .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, + .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, .tx_st_done = 25, .clk_div = 4, .high_speed = true,