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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745475; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pM6whmgyRwSqq5DhU05BK7t5rD5rPlWu1apIXMRZECI=; b=DawKnAGWiKXF0FSl4Sd28dy7tSWbsS9R1KLVoe+V4yFPbSIP8wOP3BE3bT64jf6cqe1jlf 8xsTa/OKgwb7eq2PqqByT8w3gmCtaBgG9a6PTV3GZfGu/gIWBMmY1uiM/sITT86ZIUdTsx 7LF/DYVEUUdLS/qM8l8LHPpT8IbtMGqBUv5s/+XieiCt0bf7/NEwcFrloOxhMAwYHhYKcA CVLe8sEHuNjkHT32aArX8gjbCsHC9HtonUl9aIxhbYQ57h47zfQPWW9NMvaZnnw5FvYn4M 9WT95vBiJVcgxK4CEELa4OVs6CCW7yZkrJpmMSvJugWqrigDRBCN3vmLB22aJg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:32 +0100 Subject: [PATCH v6 01/13] clk: fixed-factor: add optional accuracy support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-1-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790703112030479525 X-GMAIL-MSGID: 1790703112030479525 Fixed factor clock reports the parent clock accuracy. Add flags and acc fields to `struct clk_fixed_factor` to support setting a fixed accuracy. The default if no flag is set is not changed: use the parent clock accuracy. Signed-off-by: Théo Lebrun --- drivers/clk/clk-fixed-factor.c | 28 +++++++++++++++++++++------- include/linux/clk-provider.h | 12 +++++++++++- 2 files changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index b3e66202b942..bc2644a9bd7d 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -57,10 +57,22 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static unsigned long clk_factor_recalc_accuracy(struct clk_hw *hw, + unsigned long parent_accuracy) +{ + struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); + + if (fix->flags & CLK_FIXED_FACTOR_FIXED_ACCURACY) + return fix->acc; + + return parent_accuracy; +} + const struct clk_ops clk_fixed_factor_ops = { .round_rate = clk_factor_round_rate, .set_rate = clk_factor_set_rate, .recalc_rate = clk_factor_recalc_rate, + .recalc_accuracy = clk_factor_recalc_accuracy, }; EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); @@ -81,7 +93,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, int index, unsigned long flags, unsigned int mult, unsigned int div, - bool devm) + unsigned long acc, unsigned int fixflags, bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; @@ -105,6 +117,8 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, fix->mult = mult; fix->div = div; fix->hw.init = &init; + fix->acc = acc; + fix->flags = fixflags; init.name = name; init.ops = &clk_fixed_factor_ops; @@ -152,7 +166,7 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index, - flags, mult, div, true); + flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index); @@ -174,7 +188,7 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, unsigned long flags, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, - -1, flags, mult, div, true); + -1, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw); @@ -184,7 +198,7 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, { return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, -1, flags, mult, div, - false); + 0, 0, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw); @@ -193,7 +207,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, false); + flags, mult, div, 0, 0, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); @@ -240,7 +254,7 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, true); + flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); @@ -267,7 +281,7 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0, - 0, mult, div, false); + 0, mult, div, 0, 0, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 1293c38ddb7f..7ddc952c8c67 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1084,18 +1084,28 @@ void of_fixed_factor_clk_setup(struct device_node *node); * @hw: handle between common and hardware-specific interfaces * @mult: multiplier * @div: divider + * @acc: fixed accuracy in ppb + * @flags: behavior modifying flags * * Clock with a fixed multiplier and divider. The output frequency is the * parent clock rate divided by div and multiplied by mult. - * Implements .recalc_rate, .set_rate and .round_rate + * Implements .recalc_rate, .set_rate, .round_rate and .recalc_accuracy + * + * Flags: + * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the + * parent clk accuracy. */ struct clk_fixed_factor { struct clk_hw hw; unsigned int mult; unsigned int div; + unsigned long acc; + unsigned int flags; }; +#define CLK_FIXED_FACTOR_FIXED_ACCURACY BIT(0) + #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) extern const struct clk_ops clk_fixed_factor_ops; From patchwork Mon Feb 12 13:44:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199804 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2438216dyd; Mon, 12 Feb 2024 05:51:47 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWMsHUgl/AbGDLxCWARhOPx+hcE5NQjrU3J4DKI/usvWrOUrdKC/GnmACkiaInqDDaMOypH85ROZcBrK5NdN24b+6bCOg== X-Google-Smtp-Source: AGHT+IHBefFdGVyBJatVoNBqM6JfNrKNxeZV+sdKB58SnvpkTsL2O96kyiIbWglbFetG9QGqcMMG X-Received: by 2002:a05:620a:1483:b0:785:d958:e7f5 with SMTP id w3-20020a05620a148300b00785d958e7f5mr1658855qkj.52.1707745907288; Mon, 12 Feb 2024 05:51:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707745907; cv=pass; d=google.com; s=arc-20160816; b=Plb085e5tg9+4AUEs6WaiaZM39VEih7yfBk5c3R0r5VQQLpU5ufujoSvLzlTT6dgrx 4bebnyN9wBlPhD1AZhmeNqsQb5K/MQK7OEJPeAccK+BTxfB29Y635HDqhsPJBZnlppnn mEbPdt6u4WemCUJPLQ2pGLjAbrDff5S3osErkIAf1PQpZqGShEIL/X7I5kfT5OCYQnoK zMpl3qVv52JnrrrQdH9a7eNjk7b3E+qNKYjDP1uK5u4M4LivtKAC6OIAiKN+I8D24IlC 2JXynrAlpc7T7A7HmJWwKTKUR2hrxV598Jat26/ZT+1F7DKUDS1jBk+Yrq6Bt2TEJSPG GWsA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=Hzzlts4PGXFUuRWYcplGsnHuTe6WB3sA9fR+Y6Zs2Sk=; fh=Qo2T+sOnF564pC2fq/ZnXx+mb0I/lep89Fw5HUqmLUQ=; b=iK/HCTsGCk1HWLmVJBZ49yg8KN2lkBeRBdBXcLaRmLuBKOWspVJ46Z9aMsw+iGALBW lc67qDiqR95h1TycCZ6+BEbjlnHzOg/vkSui/52ZpGNui6aV/+6vHdsgZE1vwdG0LjN7 cDv+aB+vKG28QDfu5inAA9WRSmkErjsfENbB9IPg3XwZCdgDWNLmFwkynkn55cWIrmlV oTncbTnBzmIBddveSxadk7D5kXJZGoIxSBvWylX7QwDnYLuAMD1xIcEd1NRSer//ATSN pAoS+idm1wxpM7784Hnm0JxZuE8o3iD/F3dHwFFIIluM3RRuzY4yGwof26eihCxlhbdj /A0A==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=fXcTEQsx; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-61731-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61731-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=2; AJvYcCWrPbwWhTbfH+UYO6x5EtmUaQjEUKZULHy1WncCtN3BVkWj7Qsq2loRBSadmarJA8Re4w0NaLufYZshjUUCLcYdrQKcJA== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745476; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Hzzlts4PGXFUuRWYcplGsnHuTe6WB3sA9fR+Y6Zs2Sk=; b=fXcTEQsxMaxf8lVMmX27YQgDauQSyrLPXbAa9V3fmmFGGTBd5Jpf25/Dye1EfsvJ4uglwQ QddJQiQ4Vt8Ik22rJXM4OHPPV4NBJHDyKR9tDmuT6pGrd5RXkRMtcwMQTFoAmL+OeW7dHf SwxjQ1D1b4Ge9kWtKE7NtnOg+GQu2RKHlffGX3MaoCOfdNjIeg8K/doqsTELhbasHoB8Y7 YLJsf2aQceOcjeKrnacqZnHJfkAOGqjlDPbkkGKq3UP4oMR+XI/rRGOC1zvVAQJHmyLZyD ouJZieoQ7qDFPsyT8n9EPaw0oQbkUusLLBn027rDj4qNxHcmQcaGnQ6ckMVb8Q== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:33 +0100 Subject: [PATCH v6 02/13] clk: fixed-factor: add fwname-based constructor functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-2-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790701372667882764 X-GMAIL-MSGID: 1790701372667882764 Add four functions to register clk_hw based on the fw_name field in clk_parent_data, ie the value in the DT property `clock-names`. There are variants for devm or not and passing an accuracy or not passing one: - clk_hw_register_fixed_factor_fwname - clk_hw_register_fixed_factor_with_accuracy_fwname - devm_clk_hw_register_fixed_factor_fwname - devm_clk_hw_register_fixed_factor_with_accuracy_fwname The `struct clk_parent_data` init is extracted from __clk_hw_register_fixed_factor to each calling function. It is required to allow each function to pass whatever field they want, not only index. Signed-off-by: Théo Lebrun --- drivers/clk/clk-fixed-factor.c | 85 +++++++++++++++++++++++++++++++++++------- include/linux/clk-provider.h | 14 +++++++ 2 files changed, 85 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index bc2644a9bd7d..fe0500a1af3e 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -91,13 +91,12 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void * static struct clk_hw * __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, - const struct clk_hw *parent_hw, int index, + const struct clk_hw *parent_hw, const struct clk_parent_data *pdata, unsigned long flags, unsigned int mult, unsigned int div, unsigned long acc, unsigned int fixflags, bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; - struct clk_parent_data pdata = { .index = index }; struct clk_hw *hw; int ret; @@ -128,7 +127,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, else if (parent_hw) init.parent_hws = &parent_hw; else - init.parent_data = &pdata; + init.parent_data = pdata; init.num_parents = 1; hw = &fix->hw; @@ -165,7 +164,9 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index, + const struct clk_parent_data pdata = { .index = index }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index); @@ -187,8 +188,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { + const struct clk_parent_data pdata = { .index = -1 }; + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, - -1, flags, mult, div, 0, 0, true); + &pdata, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw); @@ -196,9 +199,10 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, - parent_hw, -1, flags, mult, div, - 0, 0, false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, + &pdata, flags, mult, div, 0, 0, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw); @@ -206,11 +210,37 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, 0, 0, false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, 0, 0, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, 0, 0, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_fwname); + +struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, acc, + CLK_FIXED_FACTOR_FIXED_ACCURACY, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy_fwname); + struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) @@ -253,16 +283,43 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, 0, 0, true); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, 0, 0, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_fwname); + +struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, acc, + CLK_FIXED_FACTOR_FIXED_ACCURACY, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_with_accuracy_fwname); + #ifdef CONFIG_OF static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) { struct clk_hw *hw; const char *clk_name = node->name; + const struct clk_parent_data pdata = { .index = 0 }; u32 div, mult; int ret; @@ -280,8 +337,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); - hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0, - 0, mult, div, 0, 0, false); + hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, + &pdata, 0, mult, div, 0, 0, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 7ddc952c8c67..4a537260f655 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1116,10 +1116,24 @@ void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc); struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div); From patchwork Mon Feb 12 13:44:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199846 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2459144dyd; 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745477; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FcFUqpSnnhPRAS/CSWnN37MHwsy8eP/c7jhpSXCs+BM=; b=m8wPylnsEuPb3HFEHxoXGVrvA3luLSdYElwowgJjp5b4/JcRzu3nvCI18/DlzEI1k/YYmU AzV8w7AIEdzUtpa2vPmh3zGae82sT165EC8B4hyUHlKK7xHA7AinfZGBj+xHOe0Bq2sZlG k7mWB8HInhw/MhdDHIlLXKnye+SFMyp/BjYfCgVW23tZRKOJ0OjeFZNlqLWB5qjrq8nPDW +3CnhL5KcnOVGyh8uoDtZeDimWOatkABQJEOMHy9BRPdF3YS2F0dw9tHQ35oE74tmDF/eB 8Oo6U3sUS08tyv++q4guFQw22vhSukZb5nxv1B4mfrhllyQIpUip7919wpoOww== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:34 +0100 Subject: [PATCH v6 03/13] dt-bindings: clock: mobileye,eyeq5-clk: add bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-3-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790703398041413886 X-GMAIL-MSGID: 1790703398041413886 Add DT schema bindings for the EyeQ5 clock controller driver. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Théo Lebrun --- .../bindings/clock/mobileye,eyeq5-clk.yaml | 51 ++++++++++++++++++++++ MAINTAINERS | 2 + include/dt-bindings/clock/mobileye,eyeq5-clk.h | 22 ++++++++++ 3 files changed, 75 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml b/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml new file mode 100644 index 000000000000..2d4f2cde1e58 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 clock controller + +description: + The EyeQ5 clock controller handles 10 read-only PLLs derived from the main + crystal clock. It also exposes one divider clock, a child of one of the PLLs. + Its registers live in a shared region called OLB. + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +properties: + compatible: + const: mobileye,eyeq5-clk + + reg: + maxItems: 2 + + reg-names: + items: + - const: plls + - const: ospi + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + description: + Input parent clock to all PLLs. Expected to be the main crystal. + + clock-names: + items: + - const: ref + +required: + - compatible + - reg + - reg-names + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index bc5e34d1eaaf..bd21d03e1771 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14788,10 +14788,12 @@ M: Gregory CLEMENT M: Théo Lebrun L: linux-mips@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml F: Documentation/devicetree/bindings/mips/mobileye.yaml F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S +F: include/dt-bindings/clock/mobileye,eyeq5-clk.h F: include/dt-bindings/soc/mobileye,eyeq5.h MODULE SUPPORT diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h new file mode 100644 index 000000000000..26d8930335e4 --- /dev/null +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H +#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H + +#define EQ5C_PLL_CPU 0 +#define EQ5C_PLL_VMP 1 +#define EQ5C_PLL_PMA 2 +#define EQ5C_PLL_VDI 3 +#define EQ5C_PLL_DDR0 4 +#define EQ5C_PLL_PCI 5 +#define EQ5C_PLL_PER 6 +#define EQ5C_PLL_PMAC 7 +#define EQ5C_PLL_MPC 8 +#define EQ5C_PLL_DDR1 9 + +#define EQ5C_DIV_OSPI 10 + +#endif From patchwork Mon Feb 12 13:44:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199805 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2438277dyd; Mon, 12 Feb 2024 05:51:55 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXpAX+iE4wchjMVR1Ay04sdu82OWDgnFdcnaOcs5YRNGLtFLUGbaqm7+3iTbelxhV08D4ydTk1D5pjSbk84RfRLQ4Bxog== X-Google-Smtp-Source: AGHT+IGP4++WFYX0Y6/let7Nyq+iCuGxTjKIUQ5vougi1XbFfdjaA+Yu9iU8fdLQT8lrWawQzhJq X-Received: by 2002:a17:906:68cc:b0:a3c:908b:cee0 with SMTP id y12-20020a17090668cc00b00a3c908bcee0mr2532279ejr.12.1707745915632; Mon, 12 Feb 2024 05:51:55 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707745915; cv=pass; d=google.com; s=arc-20160816; b=AUnDlPjwGnZTQvCVmahrmY0i2iQpy4YXu3sERNyEH2J3zDx9b/zZfyDVOnUA+KYM3G fnisGztxBCWev9YCXbRaSB1aRm6e7vUffj4rctXoyI4TdIdOdD3NGuLnNLpTqi5VTLdH 34KuO7Y3bwskY6K0/1+M1Dmuqjth2qKTQptTNWa279VOIvBuTdHWFJNSoVO2hYVRDQwI dPaqfEKuAuKe+QNFMH7PyHiDl59rgTstY6RJq0LfT0aKp11CaeDEoYMckjJCMle3PFQM hArqLA57qkUZ7JlCqD7zux4BL0zALjPpt069KtDDJWekjtD+gPw2ESP+qfQXoKzvFSnz 4lEA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=fVRiwoVL+FY+QeHP/uLuwMZlHHrs6BkXmWBVxMFaIRQ=; fh=/tFUXgSInMJn1HP6A+G4TGbmgzI4BVzAWEqtf4cvhi0=; b=dJEZjztZzpIeWJGkfGr8mrzn1xs13DPUHeXYw+wD57g32Nc+uxrNnKIN/7IrCNSaDt iSSO7lrdx0soMhQSUtruPgbliME/AtrSPPkYo6TOkfkKgD8OoC7Av2wQf9GHJeF3lJQL wOfDxuJtdIurxLPeNxAaoNXRW+cCVXDl/aX/1UpcT13ERQPMgH+khONKqBTJ1JuSVB65 7yJn3w33aLmU1wa4LZFn+i10MrNZ9D1V9c83HAN2V/OAGuoSa8QsCjNBi3GsWQ6j4LAY LMF3PjMy5tedGYk0QYxkDH4vPZJX2ruxlWFWrs/pnlUZMWOPZH5Po+rpWn6BK1sG7Rt1 KBeA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=HbLZutwL; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-61733-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61733-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=2; AJvYcCWduJ/lpyXgHUDc+M14Dm64z0HEuaYEQOifJX6fiNdXX6hGK29jntx2UDHBAsGbO+Ab1b1Bv2VCQfiYL94iPIqnEDJAnA== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745477; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fVRiwoVL+FY+QeHP/uLuwMZlHHrs6BkXmWBVxMFaIRQ=; b=HbLZutwL23yXXpEj+p+4z9oeNqkN5LBy34pMVVPU3l78+eWRxSJZ0EApRpCsJp+d3LIM1d qzxb1cK2EKcCFdaNm8Yk7Tn6HroAYWti7jNbLhKDkLA9GlLG3ly0AaO5lceiIPMnAthWwD oanGD4ABYoWWXGwxiW48rG8s/MX/Xwhva5HrVIpIaA1h9eSiArsjJ3nXZuPD4BsbeE7yF8 psq9PzpXBMq424R3dgZzalOKfcfoX7Yq3LVvP+rHcIkUnsphZ3zoiHNWw2Y14aoakjWE8S tF6XW2naMJ4ALxCrn7O07/sWfeqa9YVRP5CnEBXXpUew1Jhr6KnZTOi4xhm09w== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:35 +0100 Subject: [PATCH v6 04/13] dt-bindings: reset: mobileye,eyeq5-reset: add bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-4-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790701381085256195 X-GMAIL-MSGID: 1790701381085256195 Add DT-Schema bindings for the EyeQ5 reset controller. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Théo Lebrun --- .../bindings/reset/mobileye,eyeq5-reset.yaml | 43 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml b/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml new file mode 100644 index 000000000000..062b4518347b --- /dev/null +++ b/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mobileye,eyeq5-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 reset controller + +description: + The EyeQ5 reset driver handles three reset domains. Its registers live in a + shared region called OLB. + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +properties: + compatible: + const: mobileye,eyeq5-reset + + reg: + maxItems: 3 + + reg-names: + items: + - const: d0 + - const: d1 + - const: d2 + + "#reset-cells": + const: 2 + description: + The first cell is the domain (0 to 2 inclusive) and the second one is the + reset index inside that domain. + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index bd21d03e1771..00ff22e2ee54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14790,6 +14790,7 @@ L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml F: Documentation/devicetree/bindings/mips/mobileye.yaml +F: Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S From patchwork Mon Feb 12 13:44:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199843 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2456393dyd; Mon, 12 Feb 2024 06:19:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IFtXgN+YLo538pQHnz63s6mYgj5HwV28kFgWtt+g8O6XJkrHuVMNpU/Xg/5+TdklSeqbMlf X-Received: by 2002:a17:902:e84f:b0:1d6:fe15:b588 with SMTP id t15-20020a170902e84f00b001d6fe15b588mr8470754plg.64.1707747571434; Mon, 12 Feb 2024 06:19:31 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707747571; cv=pass; d=google.com; s=arc-20160816; b=tywgsaq6/lIDdJf8c0JMMsaRk8inWCGlKo7mNmd78W2Gwxb2lgVjtMWemnehfjwEUP bgEWgaFWNu8XQ0iZynW0Blw+9xJczJLtXnYOi3ngjUgO8h9ZIxSk1JVPVEXsxZ/KrO6e HN/x1t10mRA7UZz9IYORtVtMBlnOV6EOaLKZYYK+y6S0nqQPRVvMYiBjDQaJzzRE0N2G qotsHlvHvALgPXURgE7IN9PiErGfFNCjfRYBEeMY7CYMzd/bqm5yQcmNYWohx+VlA1nM jH2adXIXmLxBcTmTaNaQwe9ptskghRQoR6FJ94+umNQOUnPssNqDP5M/NDh7AEV4eZHS l0DQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=L4AXFWUTgUDOxGt9eT5+j/1vmomTCgQeTDVRK1b+zv0=; fh=59LRUV42JyvLYyPamE1ABpomazXSyEGeuarurk2nIiI=; b=qTn3MmDp0zXkESU60xUz8Dzl1HmsA699ixt8PyPGkj/SnjC4sPsNbazW74hVRqe6DV VS7Un5Glgp8OY0vMfGkD6I6IF9JqQNxgzPy4rxhGDB9UAszH77xEexdwm/W33rplY3DF eZccIFnwgTj5d+Ey/T3oWhKIufGJXwtTkVFPhR3R9csFO3gqaMmGcZwgNpN/d3WgB5tD pdHKunSJ+Z6wGDTnQpqmg6n+jMTcQnWsqeV+zj6Vt9XmsYvtWPiAAKQAykRXVW9rpmtt g41yn5xQcSLJ1FaETUEM1rX6WkqHhJw/NBPqD6JlMKjA6/G6meqOhRCRSHKzqm8I4D/C 8Zcw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=hAFD4F7T; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-61734-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61734-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=2; AJvYcCW0MySp5MIBjN5MfilKmiwcT1YB/4gdN++z4Rf3Nl6ysnq+Vwzk1pKI3aj2hA7jeTLg+KeIukJX6dIFHL8GL1F6HvV8Qg== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745478; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L4AXFWUTgUDOxGt9eT5+j/1vmomTCgQeTDVRK1b+zv0=; b=hAFD4F7TCcy8SUEQ3fLGSHEDrqSxyIaNgJNdE6kH1oVWzXLOQFU7h8pwq7A6Sy3fMjpjaM dme0wuCq/0QIIyG7Ywnm/kVOC2uke++LFgI7SugYq4qr0U8zdVJEkPqc3i3EHn30C52SrN iaB9R2DEeUE9qBMPg4zZ5vJbN+UIzd4bzvAd4PbfaY4VXL0YGcBLWMtkFcvBa+Wa2MV1QX W+Z0y7uUKx2fal+QtpPiBLP0bDkTevTk2iLc1du4+4QCZSNXe/mIBkOut82HonmfnBCMzP E2hTvbaKZPTJG2Dh9xo/g6crjx4wG/5RZtKn+Hnf/pdXhJNwudR+QOakMwAGmg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:36 +0100 Subject: [PATCH v6 05/13] dt-bindings: pinctrl: mobileye,eyeq5-pinctrl: add bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-5-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790703117261871968 X-GMAIL-MSGID: 1790703117261871968 Add dt-schema type bindings for the Mobileye EyeQ5 pin controller. Reviewed-by: Rob Herring Signed-off-by: Théo Lebrun Reviewed-by: Linus Walleij --- .../bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml | 242 +++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 243 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml new file mode 100644 index 000000000000..5f00604bf48c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 pin controller + +description: > + The EyeQ5 pin controller handles the two pin banks of the system. It belongs + to a system-controller block called OLB. + + Pin control is about bias (pull-down, pull-up), drive strength and muxing. Pin + muxing supports two functions for each pin: first is GPIO, second is + pin-dependent. + + Pins and groups are bijective. + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +$ref: pinctrl.yaml# + +properties: + compatible: + enum: + - mobileye,eyeq5-pinctrl + + reg: + maxItems: 1 + +patternProperties: + "-pins?$": + type: object + description: Pin muxing configuration. + $ref: pinmux-node.yaml# + additionalProperties: false + properties: + pins: true + function: + enum: [gpio, + # Bank A + timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0, + spi1, refclk0, + # Bank B + timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0] + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + required: + - pins + - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + pins: + items: # PA0 - PA28, PB0 - PB22 + pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$' + - if: + properties: + function: + const: timer0 + then: + properties: + pins: + items: + enum: [PA0, PA1] + - if: + properties: + function: + const: timer1 + then: + properties: + pins: + items: + enum: [PA2, PA3] + - if: + properties: + function: + const: timer2 + then: + properties: + pins: + items: + enum: [PA4, PA5] + - if: + properties: + function: + const: timer5 + then: + properties: + pins: + items: + enum: [PA6, PA7, PA8, PA9] + - if: + properties: + function: + const: uart0 + then: + properties: + pins: + items: + enum: [PA10, PA11] + - if: + properties: + function: + const: uart1 + then: + properties: + pins: + items: + enum: [PA12, PA13] + - if: + properties: + function: + const: can0 + then: + properties: + pins: + items: + enum: [PA14, PA15] + - if: + properties: + function: + const: can1 + then: + properties: + pins: + items: + enum: [PA16, PA17] + - if: + properties: + function: + const: spi0 + then: + properties: + pins: + items: + enum: [PA18, PA19, PA20, PA21, PA22] + - if: + properties: + function: + const: spi1 + then: + properties: + pins: + items: + enum: [PA23, PA24, PA25, PA26, PA27] + - if: + properties: + function: + const: refclk0 + then: + properties: + pins: + items: + enum: [PA28] + - if: + properties: + function: + const: timer3 + then: + properties: + pins: + items: + enum: [PB0, PB1] + - if: + properties: + function: + const: timer4 + then: + properties: + pins: + items: + enum: [PB2, PB3] + - if: + properties: + function: + const: timer6 + then: + properties: + pins: + items: + enum: [PB4, PB5, PB6, PB7] + - if: + properties: + function: + const: uart2 + then: + properties: + pins: + items: + enum: [PB8, PB9] + - if: + properties: + function: + const: can2 + then: + properties: + pins: + items: + enum: [PB10, PB11] + - if: + properties: + function: + const: spi2 + then: + properties: + pins: + items: + enum: [PB12, PB13, PB14, PB15, PB16] + - if: + properties: + function: + const: spi3 + then: + properties: + pins: + items: + enum: [PB17, PB18, PB19, PB20, PB21] + - if: + properties: + function: + const: mclk0 + then: + properties: + pins: + items: + enum: [PB22] + +required: + - compatible + - reg + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index 00ff22e2ee54..f397dd1b32d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14790,6 +14790,7 @@ L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml F: Documentation/devicetree/bindings/mips/mobileye.yaml +F: Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml F: Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig From patchwork Mon Feb 12 13:44:37 2024 Content-Type: text/plain; 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745479; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5Gf1u42EHHfffvDbyP9y58zXZhDYkOBkG79TmsvC6H0=; b=RXfCyjeRydY2wMt+zGRmTJixZVTHUe2RA7JSfkhPFMw0swyoAD7d9A5JoHmO1zjjO3tBTZ +2yrAlQowuTrQMGsShOP3wESoqSZjZLsJlFGpcsKGCoJJch+khXooKo5SVD6H7G5HiDrFB fMk7sqBGZ86aHoZ525d47IMOj1rO8g7SSYgYG3Uin8wQC9PjU5paO/Drc1XA/cDrpGzdO/ JNuWY348uJo/cbRqNKkOEvnQL4HRWs7XjxBaXcwQlY22KvaoIpbLNJMIj36mmunOyLyFZ4 cF45C+uLBUn9Vf+bDF496eRLrWrrqCTE7D0prffpz7gOZ0v1ubKZZhP1dK0sFw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:37 +0100 Subject: [PATCH v6 06/13] dt-bindings: soc: mobileye: add EyeQ5 OLB system controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-6-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790701428202817033 X-GMAIL-MSGID: 1790701428202817033 Add documentation to describe the "Other Logic Block" syscon. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Théo Lebrun --- .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml | 94 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 95 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml new file mode 100644 index 000000000000..bcded7fb86dc --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 SoC system controller + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +description: + OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks, + resets, pinctrl are being handled from here. + +properties: + compatible: + items: + - const: mobileye,eyeq5-olb + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + '^clock-controller@[0-9a-f]+$': + $ref: /schemas/clock/mobileye,eyeq5-clk.yaml# + + '^reset-controller@[0-9a-f]+$': + $ref: /schemas/reset/mobileye,eyeq5-reset.yaml# + + '^pinctrl@[0-9a-f]+$': + $ref: /schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml# + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-controller@e00000 { + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; + reg = <0x0 0xe00000 0x0 0x400>; + ranges = <0x0 0x0 0xe00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + reset: reset-controller@0 { + compatible = "mobileye,eyeq5-reset"; + reg = <0x000 0x0c>, <0x200 0x34>, <0x120 0x04>; + reg-names = "d0", "d1", "d2"; + #reset-cells = <2>; + }; + + clocks: clock-controller@2c { + compatible = "mobileye,eyeq5-clk"; + reg = <0x02c 0x50>, <0x11c 0x04>; + reg-names = "plls", "ospi"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + + pinctrl: pinctrl@b0 { + compatible = "mobileye,eyeq5-pinctrl"; + reg = <0x0b0 0x30>; + + uart2_pins: uart2-pins { + function = "uart2"; + pins = "PB8", "PB9"; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index f397dd1b32d8..51445b919ebf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14792,6 +14792,7 @@ F: Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml F: Documentation/devicetree/bindings/mips/mobileye.yaml F: Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml F: Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml +F: Documentation/devicetree/bindings/soc/mobileye/ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S From patchwork Mon Feb 12 13:44:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199849 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2461088dyd; Mon, 12 Feb 2024 06:27:27 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUvnwEsg5xkahBN6yFqFNDXcTOhKd4EmrR18EiD+STVRmSHo9cjiBNTfHuDvq0dqJwCk+C6NGBjjEpgNf4RnidvOhFusg== X-Google-Smtp-Source: AGHT+IF+mrmB+QrgQSw61mR3X30CRuwHymxxSgoQQYyF47MFParYXBJ3IXhqQpSrT0n2mZA2wXDh X-Received: by 2002:aa7:86d4:0:b0:6dd:c3fd:45fb with SMTP id h20-20020aa786d4000000b006ddc3fd45fbmr6408592pfo.24.1707748046887; Mon, 12 Feb 2024 06:27:26 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707748046; cv=pass; d=google.com; s=arc-20160816; b=rZyjL61Ka0XUEZp/cJVOcI1slXfW95BmVnMwJc9YtW1DOdIronujXGmexmoiqkHSzw 2LJfz5p+d3yGwdyDbqiG66NGL1OYBuxtpgUJQYa+Ihl72ptKj3DooMDJlCeqbEVALqj+ pWXiy/lM5yggQPHhPU3Ej04M9gqTet6CXHs/XvTYDj6dKODyVtiFuJeQc0Z0lCyHKOXJ 5DocAwyk259SxS1uCLXMUZUT29acevUBBmOw4AWJie/HwNIggAo1ruKc5Maa9apJVN6D z3Ui+dZoTSQiTRmLu30Opp0YS6YYf0eOO2WnIghJoHByGlBgyXka6mCLulitJQbGRAwT aIag== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=VZyV9IslD7MrdL6YpL4GuDtYnHORrna6RtrNu8CCW3g=; fh=MNXVbv4q5G1X9FalviJ/W1kMliEukyLFIPAoWTs+zEQ=; b=PxR7eEHDLnpcN0JKgo0zLleYX/zF/gmsyICvhXuD4Jra3GtMw79RKCvjg+K7YWJBHz 3FRV4djcKHxhXuzzQJKsj9C7gAFg0g/ae3GTpav1R1zlBurFz1S2M3M44nX8FNSe9cbu ISDD3kxl6TY+uPCfqM/+jQuSxpbLj6aH6JZArj/X3UszVC6UEF0kR7zPYNhK94MN8ol+ TOhusGemIAmKgmKmCKDeVvZyAwYIJsacAbh6tJipGpZYtzd5NAepyrQ1XeiDs7nZcPUU kUDKsdv05wANyq8/5LjpEk/V1em6Ot7+Z0OFruGRECvN1GPUGEZIt384rTksIgdlPXGW cJ3g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=nAw5m1cl; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-61736-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61736-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=2; AJvYcCVVVjNKZvRv2ToluC2tLF1hmpuxtuSo5aKEHH38hkss8Y1zIWBwHNefcXuEB+GCk30mWarZQyMmrfuZaDVT4KbF4pj4sQ== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745480; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VZyV9IslD7MrdL6YpL4GuDtYnHORrna6RtrNu8CCW3g=; b=nAw5m1cl6601b3adKCO1cq92AnruRJX93E687Oq4GCI9XodbnaVrryqE51sitMdTR1+d77 3o7M8zLUGD9NC1KTsk46rullJoAotjzT4AS0xR9j6ujJRw+phFeVGezGBoRZncAAJk90BC UtOB8jxd+nv/0EoggBn5DSckOZ61a9RSwo90qbY8HXaPvHNAz1hMcnHWRABwion8HAK0tZ hDNUcJ/1bCOvbbAjDwxH7U8jXGb30vjPAhTYFSyqXcqMqThiPOL9TifOsXJEAFBQLtcrxv Pke/HUbCJ6Cn0m2bVG16j5+Qe72h5VitGKqzZleGOFikG05HJPQw566+y9odgw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:38 +0100 Subject: [PATCH v6 07/13] clk: eyeq5: add platform driver, and init routine at of_clk_init() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-7-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790703616369440810 X-GMAIL-MSGID: 1790703616369440810 Add the Mobileye EyeQ5 clock controller driver. It might grow to add support for other platforms from Mobileye. It handles 10 read-only PLLs derived from the main crystal on board. It exposes a table-based divider clock used for OSPI. Other platform clocks are not configurable and therefore kept as fixed-factor devicetree nodes. Two PLLs are required early on and are therefore registered at of_clk_init(). Those are pll-cpu for the GIC timer and pll-per for the UARTs. Signed-off-by: Théo Lebrun --- MAINTAINERS | 1 + drivers/clk/Kconfig | 11 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-eyeq5.c | 289 ++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 302 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 51445b919ebf..743e7d40c853 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14796,6 +14796,7 @@ F: Documentation/devicetree/bindings/soc/mobileye/ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S +F: drivers/clk/clk-eyeq5.c F: include/dt-bindings/clock/mobileye,eyeq5-clk.h F: include/dt-bindings/soc/mobileye,eyeq5.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 50af5fc7f570..d5043ce2a75c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -218,6 +218,17 @@ config COMMON_CLK_EN7523 This driver provides the fixed clocks and gates present on Airoha ARM silicon. +config COMMON_CLK_EYEQ5 + bool "Clock driver for the Mobileye EyeQ5 platform" + depends on OF + depends on MACH_EYEQ5 || COMPILE_TEST + default MACH_EYEQ5 + help + This driver provides the clocks found on the Mobileye EyeQ5 SoC. Its + registers live in a shared register region called OLB. It provides 10 + read-only PLLs derived from the main crystal clock which must be constant + and one divider clock based on one PLL. + config COMMON_CLK_FSL_FLEXSPI tristate "Clock driver for FlexSPI on Layerscape SoCs" depends on ARCH_LAYERSCAPE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 14fa8d4ecc1f..81c4d11ca437 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o +obj-$(CONFIG_COMMON_CLK_EYEQ5) += clk-eyeq5.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o diff --git a/drivers/clk/clk-eyeq5.c b/drivers/clk/clk-eyeq5.c new file mode 100644 index 000000000000..9598139e0383 --- /dev/null +++ b/drivers/clk/clk-eyeq5.c @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PLL clock driver for the Mobileye EyeQ5 platform. + * + * This controller handles 10 read-only PLLs, all derived from the same main + * crystal clock. It also exposes one divider clock, a child of one of the + * PLLs. The parent clock is expected to be constant. This driver's registers + * live in a shared region called OLB. Two PLLs must be initialized by + * of_clk_init(). + * + * We use eq5c_ as prefix, as-in "EyeQ5 Clock", but way shorter. + * + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#define pr_fmt(fmt) "clk-eyeq5: " fmt + +#include +#include +#include +#include +#include +#include + +#include + +/* In frac mode, it enables fractional noise canceling DAC. Else, no function. */ +#define PCSR0_DAC_EN BIT(0) +/* Fractional or integer mode */ +#define PCSR0_DSM_EN BIT(1) +#define PCSR0_PLL_EN BIT(2) +/* All clocks output held at 0 */ +#define PCSR0_FOUTPOSTDIV_EN BIT(3) +#define PCSR0_POST_DIV1 GENMASK(6, 4) +#define PCSR0_POST_DIV2 GENMASK(9, 7) +#define PCSR0_REF_DIV GENMASK(15, 10) +#define PCSR0_INTIN GENMASK(27, 16) +#define PCSR0_BYPASS BIT(28) +/* Bits 30..29 are reserved */ +#define PCSR0_PLL_LOCKED BIT(31) + +#define PCSR1_RESET BIT(0) +#define PCSR1_SSGC_DIV GENMASK(4, 1) +/* Spread amplitude (% = 0.1 * SPREAD[4:0]) */ +#define PCSR1_SPREAD GENMASK(9, 5) +#define PCSR1_DIS_SSCG BIT(10) +/* Down-spread or center-spread */ +#define PCSR1_DOWN_SPREAD BIT(11) +#define PCSR1_FRAC_IN GENMASK(31, 12) + +static struct clk_hw_onecell_data *eq5c_clk_data; + +struct eq5c_pll { + int index; + const char *name; + u32 reg; /* next 8 bytes are r0 and r1 */ +}; + +/* Required early for the GIC timer (pll-cpu) and UARTs (pll-per). */ +static const struct eq5c_pll eq5c_early_plls[] = { + { .index = EQ5C_PLL_CPU, .name = "pll-cpu", .reg = 0x00, }, + { .index = EQ5C_PLL_PER, .name = "pll-per", .reg = 0x30, }, +}; + +static const struct eq5c_pll eq5c_plls[] = { + { .index = EQ5C_PLL_VMP, .name = "pll-vmp", .reg = 0x08, }, + { .index = EQ5C_PLL_PMA, .name = "pll-pma", .reg = 0x10, }, + { .index = EQ5C_PLL_VDI, .name = "pll-vdi", .reg = 0x18, }, + { .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg = 0x20, }, + { .index = EQ5C_PLL_PCI, .name = "pll-pci", .reg = 0x28, }, + { .index = EQ5C_PLL_PMAC, .name = "pll-pmac", .reg = 0x38, }, + { .index = EQ5C_PLL_MPC, .name = "pll-mpc", .reg = 0x40, }, + { .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg = 0x48, }, +}; + +#define EQ5C_OSPI_DIV_CLK_NAME "div-ospi" +#define EQ5C_OSPI_DIV_WIDTH 4 + +#define EQ5C_NB_CLKS (ARRAY_SIZE(eq5c_early_plls) + ARRAY_SIZE(eq5c_plls) + 1) + +static const struct clk_div_table eq5c_ospi_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 4 }, + { .val = 2, .div = 6 }, + { .val = 3, .div = 8 }, + { .val = 4, .div = 10 }, + { .val = 5, .div = 12 }, + { .val = 6, .div = 14 }, + { .val = 7, .div = 16 }, + {} /* sentinel */ +}; + +static int eq5c_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult, + unsigned long *div, unsigned long *acc) +{ + if (r0 & PCSR0_BYPASS) { + *mult = 1; + *div = 1; + *acc = 0; + return 0; + } + + if (!(r0 & PCSR0_PLL_LOCKED)) + return -EINVAL; + + *mult = FIELD_GET(PCSR0_INTIN, r0); + *div = FIELD_GET(PCSR0_REF_DIV, r0); + if (r0 & PCSR0_FOUTPOSTDIV_EN) + *div *= FIELD_GET(PCSR0_POST_DIV1, r0) * + FIELD_GET(PCSR0_POST_DIV2, r0); + + /* Fractional mode, in 2^20 (0x100000) parts. */ + if (r0 & PCSR0_DSM_EN) { + *div *= 0x100000; + *mult = *mult * 0x100000 + FIELD_GET(PCSR1_FRAC_IN, r1); + } + + if (!*mult || !*div) + return -EINVAL; + + /* Spread spectrum. */ + if (!(r1 & (PCSR1_RESET | PCSR1_DIS_SSCG))) { + /* + * Spread is 1/1000 parts of frequency, accuracy is half of + * that. To get accuracy, convert to ppb (parts per billion). + */ + u32 spread = FIELD_GET(PCSR1_SPREAD, r1); + *acc = spread * 500000; + if (r1 & PCSR1_DOWN_SPREAD) { + /* + * Downspreading: the central frequency is half a + * spread lower. + */ + *mult *= 2000 - spread; + *div *= 2000; + } + } else { + *acc = 0; + } + + return 0; +} + +static int eq5c_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *base_plls, *base_ospi; + struct clk_hw *hw; + int i; + + if (IS_ERR(eq5c_clk_data)) + return PTR_ERR(eq5c_clk_data); + else if (!eq5c_clk_data) + return -EINVAL; + + base_plls = devm_platform_ioremap_resource_byname(pdev, "plls"); + base_ospi = devm_platform_ioremap_resource_byname(pdev, "ospi"); + if (!base_plls || !base_ospi) + return -ENODEV; + + for (i = 0; i < ARRAY_SIZE(eq5c_plls); i++) { + const struct eq5c_pll *pll = &eq5c_plls[i]; + unsigned long mult, div, acc; + u32 r0, r1; + int ret; + + r0 = readl(base_plls + pll->reg); + r1 = readl(base_plls + pll->reg + sizeof(r0)); + + ret = eq5c_pll_parse_registers(r0, r1, &mult, &div, &acc); + if (ret) { + dev_warn(dev, "failed parsing state of %s\n", pll->name); + continue; + } + + hw = clk_hw_register_fixed_factor_with_accuracy_fwname(dev, np, + pll->name, "ref", 0, mult, div, acc); + eq5c_clk_data->hws[pll->index] = hw; + if (IS_ERR(hw)) { + dev_err(dev, "failed registering %s: %ld\n", + pll->name, PTR_ERR(hw)); + } + } + + hw = clk_hw_register_divider_table_parent_hw(dev, EQ5C_OSPI_DIV_CLK_NAME, + eq5c_clk_data->hws[EQ5C_PLL_PER], 0, + base_ospi, 0, EQ5C_OSPI_DIV_WIDTH, 0, + eq5c_ospi_div_table, NULL); + eq5c_clk_data->hws[EQ5C_DIV_OSPI] = hw; + if (IS_ERR(hw)) { + dev_err(dev, "failed registering %s: %ld\n", + EQ5C_OSPI_DIV_CLK_NAME, PTR_ERR(hw)); + } + + return 0; +} + +static const struct of_device_id eq5c_match_table[] = { + { .compatible = "mobileye,eyeq5-clk" }, + {} +}; +MODULE_DEVICE_TABLE(of, eq5c_match_table); + +static struct platform_driver eq5c_driver = { + .probe = eq5c_probe, + .driver = { + .name = "clk-eyeq5", + .of_match_table = eq5c_match_table, + }, +}; + +builtin_platform_driver(eq5c_driver); + +static void __init eq5c_init(struct device_node *np) +{ + void __iomem *base_plls, *base_ospi; + int index_plls, index_ospi; + int i, ret; + + eq5c_clk_data = kzalloc(struct_size(eq5c_clk_data, hws, EQ5C_NB_CLKS), + GFP_KERNEL); + if (!eq5c_clk_data) { + ret = -ENOMEM; + goto err; + } + + eq5c_clk_data->num = EQ5C_NB_CLKS; + + /* + * Mark all clocks as deferred. We register some now and others at + * platform device probe. + */ + for (i = 0; i < EQ5C_NB_CLKS; i++) + eq5c_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); + + index_plls = of_property_match_string(np, "reg-names", "plls"); + index_ospi = of_property_match_string(np, "reg-names", "ospi"); + if (index_plls < 0 || index_ospi < 0) { + ret = -ENODEV; + goto err; + } + + base_plls = of_iomap(np, index_plls); + base_ospi = of_iomap(np, index_ospi); + if (!base_plls || !base_ospi) { + ret = -ENODEV; + goto err; + } + + for (i = 0; i < ARRAY_SIZE(eq5c_early_plls); i++) { + const struct eq5c_pll *pll = &eq5c_early_plls[i]; + unsigned long mult, div, acc; + struct clk_hw *hw; + u32 r0, r1; + + r0 = readl(base_plls + pll->reg); + r1 = readl(base_plls + pll->reg + sizeof(r0)); + + ret = eq5c_pll_parse_registers(r0, r1, &mult, &div, &acc); + if (ret) { + pr_warn("failed parsing state of %s\n", pll->name); + continue; + } + + hw = clk_hw_register_fixed_factor_with_accuracy_fwname(NULL, + np, pll->name, "ref", 0, mult, div, acc); + eq5c_clk_data->hws[pll->index] = hw; + if (IS_ERR(hw)) { + pr_err("failed registering %s: %ld\n", + pll->name, PTR_ERR(hw)); + } + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, eq5c_clk_data); + if (ret) { + pr_err("failed registering clk provider: %d\n", ret); + goto err; + } + + return; + +err: + kfree(eq5c_clk_data); + /* Signal to platform driver probe that we failed init. */ + eq5c_clk_data = ERR_PTR(ret); +} + +CLK_OF_DECLARE_DRIVER(eq5c, "mobileye,eyeq5-clk", eq5c_init); From patchwork Mon Feb 12 13:44:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199808 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2439224dyd; Mon, 12 Feb 2024 05:54:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IG6hMHfedojmD6ZTCphhZ7NYELkPLDogutDpoZbuwhgzm/bW6q7Ouy3UdYgaS6CsQSJJqMS X-Received: by 2002:a9d:7c8e:0:b0:6e2:eb6c:db44 with SMTP id q14-20020a9d7c8e000000b006e2eb6cdb44mr1637146otn.36.1707746046768; Mon, 12 Feb 2024 05:54:06 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707746046; cv=pass; d=google.com; s=arc-20160816; b=wtWM+YNP4mmG6XY9hWnQQ9qVv4tYRHIBscD9dnFlPKS7jXIbRn9PmKSZsiO4qagsrD B1ZgbVMTigoRUQViSWRXK18Wnk+G6NFG7bdaWSmEG/gDc3lt0LDGe5Bgp6tv/SRzknk5 izR/Gl3WGK5f/xlkcxYKWQ2jNTg2yRr25ZtepGI8363bAxQkpQBvBdrxktEhhLC/0gxn SRqi51P2obKCUMRcr0uhwGsqm8L9B+h/7ptRnH0FkMX5UUmI6uVAV1QD1mJXvAXejHaJ gGcf1pX6Gz5vJ86XsKTu9Z7GdBxCPFGFNhplh1VMCRL5Y6xwf3xFfEwzjguUBrJKkaJh qZVg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=wne3b7P+/pTIFB3LivavHhUStRiltDCfAet4fiUKTA8=; fh=PBtKAHcAOGZmUzAPfbBFc4gxnVQ9feMZrPxMx32xIcM=; b=yCZFizTDUKLTsJPFf8Bo+5Q1YdL+4QBZFTjdjf/xJAUHsgVtrLy1YfPcbB//UY984t xjxqwZDr+nzI3IgluCG72+6tI5Pv99c6sMIL0vsubMspYJpWdK9GoB1EpezwWjzgqCJ8 YT4EhXyVKGoScnGpekIPHgLyCDA6DAskoMupOmmV/PMcw9176rmhap8kkb4LsFfwj8aT /xc2DHVamwxC6+Nxq0wth47aJawrRmMOK9J6H2RBq5eRdx/o1rnNRrOtq9M4gb5tQfTB pMti4Vim1ujiYPdHp/tZunnKnVCaU2fa7fXCAH/lQGXnmaPfdHhVBbdgRBsLPFIyFikd ByoA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=jS9kvCo8; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-61737-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61737-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=2; AJvYcCXkafE/YmIHmg/x/R32cetM/SbquwXa092rqlTQjkpB3aG6DSuFURcVUqCv8ebgP+FYiQIwW7AB6oBRJdETKJcPOU87lA== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id y25-20020ac87099000000b0042c1ca83f25si393724qto.89.2024.02.12.05.54.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 05:54:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-61737-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=jS9kvCo8; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-61737-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61737-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 67E2C1C22F14 for ; Mon, 12 Feb 2024 13:54:06 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 868C74DA0C; Mon, 12 Feb 2024 13:44:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="jS9kvCo8" Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 485543EA90; Mon, 12 Feb 2024 13:44:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.199 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707745486; cv=none; b=BjZzDNHN1CWxzZFYD2AOVVHtsCHWnsIGRcJz6SOfSLiDuO0y1B/Uv6qDsREiW60q6EXdTruJBX5VvchwdgcE23wC5OXmaIgIWauJzCP6UTrdntDie+pCWKnVWKp6am1FEBDj0f1kZGxP3qcZumjHggvzwMpDlQBHYNUxXs3YDhQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707745486; c=relaxed/simple; bh=HZUIIdShjyvYXgT4qT64mYvRZI92u+IlaKO2F6+Pwx8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hAnCfnINdpVeF4EOsNqFKUEp0VS9gkM+8uMJfPOWDTE0qMITvT/2JiSBA9dill+daOPVB1TNLr5KUq8/QclEbctcyfq8se4OTMyBEFInVsTS7CvSwLBxDHZQS6OmD7MRYVJgcYkQH2Sgr1DRSXtR5pBnhWjMAuAQMIHkzVpSMFU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=jS9kvCo8; arc=none smtp.client-ip=217.70.183.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 8951DFF802; Mon, 12 Feb 2024 13:44:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745481; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wne3b7P+/pTIFB3LivavHhUStRiltDCfAet4fiUKTA8=; b=jS9kvCo8rRBQzillKS5LfsE2ek0X7GXjWH6PvkrzvMbYVyzN2myUp508JwJL0FBLh5DmcH M4SwzQ6NDdn1QeLjECSY3po+bYLK3CpuyPrAzRLS9GLNFLNx+0TIev5wALn27RTrldmgPV SgFTbfN4MoIrG0q+qD5ajyRECRfCIQSnWsAegMZAcatFHdagSTv28ovcfxEu69CbukZxCQ /BJiBsk4Qt2sC1zrDCx5RVg1i3AqhNcWCEr4BHqN0+h1kJC0/92LO2zC8kDcbWEkgxXQv3 DnbGBiXvfZ9rspcx03TjHtcxHveyU732DURGC7epFrsjCJDKqXw9NjrhkdG1Zw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:39 +0100 Subject: [PATCH v6 08/13] reset: eyeq5: add platform driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-8-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790701518651159302 X-GMAIL-MSGID: 1790701518651159302 Add the Mobileye EyeQ5 reset controller driver. It belongs to a syscon region called OLB. It might grow to add later support of other platforms from Mobileye. Signed-off-by: Théo Lebrun --- MAINTAINERS | 1 + drivers/reset/Kconfig | 12 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-eyeq5.c | 342 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 356 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 743e7d40c853..e39580805c53 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14797,6 +14797,7 @@ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S F: drivers/clk/clk-eyeq5.c +F: drivers/reset/reset-eyeq5.c F: include/dt-bindings/clock/mobileye,eyeq5-clk.h F: include/dt-bindings/soc/mobileye,eyeq5.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index ccd59ddd7610..80bfde54c076 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -66,6 +66,18 @@ config RESET_BRCMSTB_RESCAL This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on BCM7216. +config RESET_EYEQ5 + bool "Mobileye EyeQ5 reset controller" + depends on MFD_SYSCON + depends on MACH_EYEQ5 || COMPILE_TEST + default MACH_EYEQ5 + help + This enables the Mobileye EyeQ5 reset controller. + + It has three domains, with a varying number of resets in each of them. + Registers are located in a shared register region called OLB accessed + through a syscon & regmap. + config RESET_HSDK bool "Synopsys HSDK Reset Driver" depends on HAS_IOMEM diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 8270da8a4baa..4fabe0070390 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o +obj-$(CONFIG_RESET_EYEQ5) += reset-eyeq5.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o diff --git a/drivers/reset/reset-eyeq5.c b/drivers/reset/reset-eyeq5.c new file mode 100644 index 000000000000..f9d3935dd420 --- /dev/null +++ b/drivers/reset/reset-eyeq5.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Reset driver for the Mobileye EyeQ5 platform. + * + * The registers are located in a syscon region called OLB. We handle three + * reset domains. Domains 0 and 2 look similar in that they both use one bit + * per reset line. Domain 1 has a register per reset. + * + * We busy-wait after updating a reset in domains 0 or 1. The reason is hardware + * logic built-in self-test (LBIST) that might be enabled. + * + * We use eq5r_ as prefix, as-in "EyeQ5 Reset", but way shorter. + * + * Known resets in domain 0: + * 3. CAN0 + * 4. CAN1 + * 5. CAN2 + * 6. SPI0 + * 7. SPI1 + * 8. SPI2 + * 9. SPI3 + * 10. UART0 + * 11. UART1 + * 12. UART2 + * 13. I2C0 + * 14. I2C1 + * 15. I2C2 + * 16. I2C3 + * 17. I2C4 + * 18. TIMER0 + * 19. TIMER1 + * 20. TIMER2 + * 21. TIMER3 + * 22. TIMER4 + * 23. WD0 + * 24. EXT0 + * 25. EXT1 + * 26. GPIO + * 27. WD1 + * + * Known resets in domain 1: + * 0. VMP0 (Vector Microcode Processors) + * 1. VMP1 + * 2. VMP2 + * 3. VMP3 + * 4. PMA0 (Programmable Macro Array) + * 5. PMA1 + * 6. PMAC0 + * 7. PMAC1 + * 8. MPC0 (Multi-threaded Processing Clusters) + * 9. MPC1 + * + * Known resets in domain 2: + * 0. PCIE0_CORE + * 1. PCIE0_APB + * 2. PCIE0_LINK_AXI + * 3. PCIE0_LINK_MGMT + * 4. PCIE0_LINK_HOT + * 5. PCIE0_LINK_PIPE + * 6. PCIE1_CORE + * 7. PCIE1_APB + * 8. PCIE1_LINK_AXI + * 9. PCIE1_LINK_MGMT + * 10. PCIE1_LINK_HOT + * 11. PCIE1_LINK_PIPE + * 12. MULTIPHY + * 13. MULTIPHY_APB + * 15. PCIE0_LINK_MGMT + * 16. PCIE1_LINK_MGMT + * 17. PCIE0_LINK_PM + * 18. PCIE1_LINK_PM + * + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Domain 0 register offsets */ +#define D0_SARCR0 (0x004) +#define D0_SARCR1 (0x008) + +/* Domain 1 masks */ +#define D1_ACRP_PD_REQ BIT(0) +#define D1_ACRP_ST_POWER_DOWN BIT(27) +#define D1_ACRP_ST_ACTIVE BIT(29) + +/* Vendor-provided timeout values. D1 has a long timeout because of LBIST. */ +#define D0_TIMEOUT_POLL 10 +#define D1_TIMEOUT_POLL 40000 + +/* + * Masks for valid reset lines in each domain. This array is also used to get + * the domain and reset counts. + */ +static const u32 eq5r_valid_masks[] = { 0x0FFFFFF8, 0x00001FFF, 0x0007BFFF }; + +#define EQ5R_DOMAIN_COUNT ARRAY_SIZE(eq5r_valid_masks) + +struct eq5r_private { + struct mutex mutexes[EQ5R_DOMAIN_COUNT]; + void __iomem *base_d0; + void __iomem *base_d1; + void __iomem *base_d2; + struct reset_controller_dev rcdev; +}; + +#define rcdev_to_priv(rcdev) container_of(rcdev, struct eq5r_private, rcdev) + +static int eq5r_busy_wait_withlock(struct eq5r_private *priv, + struct device *dev, u32 domain, u32 offset, + bool assert) +{ + unsigned int val, mask; + int i; + + lockdep_assert_held(&priv->mutexes[domain]); + + switch (domain) { + case 0: + for (i = 0; i < D0_TIMEOUT_POLL; i++) { + val = readl(priv->base_d0 + D0_SARCR1); + val = !(val & BIT(offset)); + if (val == assert) + return 0; + udelay(1); + } + break; + case 1: + mask = assert ? D1_ACRP_ST_POWER_DOWN : D1_ACRP_ST_ACTIVE; + for (i = 0; i < D1_TIMEOUT_POLL; i++) { + val = readl(priv->base_d1 + 4 * offset); + if (val & mask) + return 0; + udelay(1); + } + break; + case 2: + return 0; /* No busy waiting for domain 2. */ + default: + WARN_ON(1); + return -EINVAL; + } + + dev_dbg(dev, "%u-%u: timeout\n", domain, offset); + return -ETIMEDOUT; +} + +static void eq5r_assert_withlock(struct eq5r_private *priv, u32 domain, + u32 offset) +{ + void __iomem *reg; + + lockdep_assert_held(&priv->mutexes[domain]); + + switch (domain) { + case 0: + reg = priv->base_d0 + D0_SARCR0; + writel(readl(reg) & ~BIT(offset), reg); + break; + case 1: + reg = priv->base_d1 + 4 * offset; + writel(readl(reg) | D1_ACRP_PD_REQ, reg); + break; + case 2: + reg = priv->base_d2; + writel(readl(reg) & ~BIT(offset), reg); + break; + default: + WARN_ON(1); + } +} + +static int eq5r_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct eq5r_private *priv = rcdev_to_priv(rcdev); + u32 offset = id & GENMASK(7, 0); + u32 domain = id >> 8; + + dev_dbg(rcdev->dev, "%u-%u: assert request\n", domain, offset); + + guard(mutex)(&priv->mutexes[domain]); + eq5r_assert_withlock(priv, domain, offset); + return eq5r_busy_wait_withlock(priv, rcdev->dev, domain, offset, true); +} + +static void eq5r_deassert_withlock(struct eq5r_private *priv, u32 domain, + u32 offset) +{ + void __iomem *reg; + + lockdep_assert_held(&priv->mutexes[domain]); + + switch (domain) { + case 0: + reg = priv->base_d0 + D0_SARCR0; + writel(readl(reg) | BIT(offset), reg); + break; + case 1: + reg = priv->base_d1 + 4 * offset; + writel(readl(reg) & ~D1_ACRP_PD_REQ, reg); + break; + case 2: + reg = priv->base_d2; + writel(readl(reg) | BIT(offset), reg); + break; + default: + WARN_ON(1); + } +} + +static int eq5r_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct eq5r_private *priv = rcdev_to_priv(rcdev); + u32 offset = id & GENMASK(7, 0); + u32 domain = id >> 8; + + dev_dbg(rcdev->dev, "%u-%u: deassert request\n", domain, offset); + + guard(mutex)(&priv->mutexes[domain]); + eq5r_deassert_withlock(priv, domain, offset); + return eq5r_busy_wait_withlock(priv, rcdev->dev, domain, offset, false); +} + +static int eq5r_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct eq5r_private *priv = rcdev_to_priv(rcdev); + u32 offset = id & GENMASK(7, 0); + u32 domain = id >> 8; + u32 val; + + dev_dbg(rcdev->dev, "%u-%u: status request\n", domain, offset); + + guard(mutex)(&priv->mutexes[domain]); + + switch (domain) { + case 0: + val = readl(priv->base_d0 + D0_SARCR1); + return !(val & BIT(offset)); + case 1: + val = readl(priv->base_d1 + 4 * offset); + return !(val & D1_ACRP_ST_ACTIVE); + case 2: + val = readl(priv->base_d2); + return !(val & BIT(offset)); + default: + return -EINVAL; + } +} + +static const struct reset_control_ops eq5r_ops = { + .assert = eq5r_assert, + .deassert = eq5r_deassert, + .status = eq5r_status, +}; + +static int eq5r_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + u32 domain, offset; + + if (WARN_ON(reset_spec->args_count != 2)) + return -EINVAL; + + domain = reset_spec->args[0]; + offset = reset_spec->args[1]; + + if (domain >= EQ5R_DOMAIN_COUNT || offset > 31 || + !(eq5r_valid_masks[domain] & BIT(offset))) { + dev_err(rcdev->dev, "%u-%u: invalid reset\n", domain, offset); + return -EINVAL; + } + + return (domain << 8) | offset; +} + +static int eq5r_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct eq5r_private *priv; + int ret, i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base_d0 = devm_platform_ioremap_resource_byname(pdev, "d0"); + if (IS_ERR(priv->base_d0)) + return PTR_ERR(priv->base_d0); + + priv->base_d1 = devm_platform_ioremap_resource_byname(pdev, "d1"); + if (IS_ERR(priv->base_d1)) + return PTR_ERR(priv->base_d1); + + priv->base_d2 = devm_platform_ioremap_resource_byname(pdev, "d2"); + if (IS_ERR(priv->base_d2)) + return PTR_ERR(priv->base_d2); + + for (i = 0; i < EQ5R_DOMAIN_COUNT; i++) + mutex_init(&priv->mutexes[i]); + + priv->rcdev.ops = &eq5r_ops; + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.dev = dev; + priv->rcdev.of_node = np; + priv->rcdev.of_reset_n_cells = 2; + priv->rcdev.of_xlate = eq5r_of_xlate; + + priv->rcdev.nr_resets = 0; + for (i = 0; i < EQ5R_DOMAIN_COUNT; i++) + priv->rcdev.nr_resets += __builtin_popcount(eq5r_valid_masks[i]); + + ret = devm_reset_controller_register(dev, &priv->rcdev); + if (ret) { + dev_err(dev, "Failed registering reset controller: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id eq5r_match_table[] = { + { .compatible = "mobileye,eyeq5-reset" }, + {} +}; + +static struct platform_driver eq5r_driver = { + .probe = eq5r_probe, + .driver = { + .name = "eyeq5-reset", + .of_match_table = eq5r_match_table, + }, +}; + +builtin_platform_driver(eq5r_driver); From patchwork Mon Feb 12 13:44:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199851 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2461507dyd; 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It might grow to add later support of other platforms from Mobileye. It belongs to a syscon region called OLB. Existing pins and their function live statically in the driver code rather than in the devicetree, see compatible match data. Signed-off-by: Théo Lebrun Reviewed-by: Linus Walleij --- MAINTAINERS | 1 + drivers/pinctrl/Kconfig | 15 ++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-eyeq5.c | 581 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 598 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e39580805c53..9134384171fe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14797,6 +14797,7 @@ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S F: drivers/clk/clk-eyeq5.c +F: drivers/pinctrl/pinctrl-eyeq5.c F: drivers/reset/reset-eyeq5.c F: include/dt-bindings/clock/mobileye,eyeq5-clk.h F: include/dt-bindings/soc/mobileye,eyeq5.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 8163a5983166..abe94de85b3d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -195,6 +195,21 @@ config PINCTRL_EQUILIBRIUM desired pin functions, configure GPIO attributes for LGM SoC pins. Pin muxing and pin config settings are retrieved from device tree. +config PINCTRL_EYEQ5 + bool "Mobileye EyeQ5 pinctrl driver" + depends on OF + depends on MACH_EYEQ5 || COMPILE_TEST + select PINMUX + select GENERIC_PINCONF + select MFD_SYSCON + default MACH_EYEQ5 + help + Pin controller driver for the Mobileye EyeQ5 platform. It does both + pin config & pin muxing. It does not handle GPIO. + + Pin muxing supports two functions for each pin: first is GPIO, second + is pin-dependent. Pin config is about bias & drive strength. + config PINCTRL_GEMINI bool depends on ARCH_GEMINI diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 1071f301cc70..0033940914d9 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o +obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq5.c new file mode 100644 index 000000000000..49ad15bdd70b --- /dev/null +++ b/drivers/pinctrl/pinctrl-eyeq5.c @@ -0,0 +1,581 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pinctrl driver for the Mobileye EyeQ5 platform. + * + * The registers are located in a syscon region called OLB. There are two pin + * banks, each being controlled by 5 registers (see enum eq5p_regs) for + * pull-down, pull-up, drive strength and muxing. + * + * For each pin, muxing is between two functions: (0) GPIO or (1) another one + * that is pin-dependent. Functions are declared statically in this driver. + * + * We create pinctrl groups that are 1:1 equivalent to pins: each group has a + * single pin, and its index/selector is the pin number. + * + * We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter. + * + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" + +struct eq5p_pinctrl { + struct pinctrl_desc desc; + void __iomem *base; +}; + +struct eq5p_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +enum eq5p_bank { + EQ5P_BANK_A, + EQ5P_BANK_B, + + EQ5P_BANK_COUNT, +}; + +enum eq5p_regs { + EQ5P_PD, + EQ5P_PU, + EQ5P_DS_LOW, + EQ5P_DS_HIGH, + EQ5P_IOCR, + + EQ5P_REG_COUNT, +}; + +static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = { + [EQ5P_BANK_A] = {0x010, 0x014, 0x020, 0x024, 0x000}, + [EQ5P_BANK_B] = {0x018, 0x01C, 0x028, 0x02C, 0x004}, +}; + +/* + * Comments to the right of each pin are the "signal name" in the datasheet. + */ +static const struct pinctrl_pin_desc eq5p_pins[] = { + /* Bank A */ + PINCTRL_PIN(0, "PA0"), /* A0_TIMER0_CK */ + PINCTRL_PIN(1, "PA1"), /* A1_TIMER0_EOC */ + PINCTRL_PIN(2, "PA2"), /* A2_TIMER1_CK */ + PINCTRL_PIN(3, "PA3"), /* A3_TIMER1_EOC */ + PINCTRL_PIN(4, "PA4"), /* A4_TIMER2_CK */ + PINCTRL_PIN(5, "PA5"), /* A5_TIMER2_EOC */ + PINCTRL_PIN(6, "PA6"), /* A6_TIMER5_EXT_INCAP1 */ + PINCTRL_PIN(7, "PA7"), /* A7_TIMER5_EXT_INCAP2 */ + PINCTRL_PIN(8, "PA8"), /* A8_TIMER5_EXT_OUTCMP1 */ + PINCTRL_PIN(9, "PA9"), /* A9_TIMER5_EXT_OUTCMP2 */ + PINCTRL_PIN(10, "PA10"), /* A10_UART_0_TX */ + PINCTRL_PIN(11, "PA11"), /* A11_UART_0_RX */ + PINCTRL_PIN(12, "PA12"), /* A12_UART_1_TX */ + PINCTRL_PIN(13, "PA13"), /* A13_UART_1_RX */ + PINCTRL_PIN(14, "PA14"), /* A14_CAN_0_TX */ + PINCTRL_PIN(15, "PA15"), /* A15_CAN_0_RX */ + PINCTRL_PIN(16, "PA16"), /* A16_CAN_1_TX */ + PINCTRL_PIN(17, "PA17"), /* A17_CAN_1_RX */ + PINCTRL_PIN(18, "PA18"), /* A18_SPI_0_DO */ + PINCTRL_PIN(19, "PA19"), /* A19_SPI_0_DI */ + PINCTRL_PIN(20, "PA20"), /* A20_SPI_0_CK */ + PINCTRL_PIN(21, "PA21"), /* A21_SPI_0_CS0 */ + PINCTRL_PIN(22, "PA22"), /* A22_SPI_0_CS1 */ + PINCTRL_PIN(23, "PA23"), /* A23_SPI_1_DO */ + PINCTRL_PIN(24, "PA24"), /* A24_SPI_1_DI */ + PINCTRL_PIN(25, "PA25"), /* A25_SPI_1_CK */ + PINCTRL_PIN(26, "PA26"), /* A26_SPI_1_CS0 */ + PINCTRL_PIN(27, "PA27"), /* A27_SPI_1_CS1 */ + PINCTRL_PIN(28, "PA28"), /* A28_REF_CLK0 */ + +#define EQ5P_PIN_OFFSET_BANK_B 29 + + /* Bank B */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 0, "PB0"), /* B0_TIMER3_CK */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 1, "PB1"), /* B1_TIMER3_EOC */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 2, "PB2"), /* B2_TIMER4_CK */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 3, "PB3"), /* B3_TIMER4_EOC */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 4, "PB4"), /* B4_TIMER6_EXT_INCAP1 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 5, "PB5"), /* B5_TIMER6_EXT_INCAP2 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 6, "PB6"), /* B6_TIMER6_EXT_OUTCMP1 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 7, "PB7"), /* B7_TIMER6_EXT_OUTCMP2 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 8, "PB8"), /* B8_UART_2_TX */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 9, "PB9"), /* B9_UART_2_RX */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */ +}; + +static const char * const gpio_groups[] = { + /* Bank A */ + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", + "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", "PA16", "PA17", "PA18", + "PA19", "PA20", "PA21", "PA22", "PA23", "PA24", "PA25", "PA26", "PA27", + "PA28", + + /* Bank B */ + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", "PB8", "PB9", + "PB10", "PB11", "PB12", "PB13", "PB14", "PB15", "PB16", "PB17", "PB18", + "PB19", "PB20", "PB21", "PB22", +}; + +/* Groups of functions on bank A */ +static const char * const timer0_groups[] = { "PA0", "PA1" }; +static const char * const timer1_groups[] = { "PA2", "PA3" }; +static const char * const timer2_groups[] = { "PA4", "PA5" }; +static const char * const timer5_groups[] = { "PA6", "PA7", "PA8", "PA9" }; +static const char * const uart0_groups[] = { "PA10", "PA11" }; +static const char * const uart1_groups[] = { "PA12", "PA13" }; +static const char * const can0_groups[] = { "PA14", "PA15" }; +static const char * const can1_groups[] = { "PA16", "PA17" }; +static const char * const spi0_groups[] = { "PA18", "PA19", "PA20", "PA21", "PA22" }; +static const char * const spi1_groups[] = { "PA23", "PA24", "PA25", "PA26", "PA27" }; +static const char * const refclk0_groups[] = { "PA28" }; + +/* Groups of functions on bank B */ +static const char * const timer3_groups[] = { "PB0", "PB1" }; +static const char * const timer4_groups[] = { "PB2", "PB3" }; +static const char * const timer6_groups[] = { "PB4", "PB5", "PB6", "PB7" }; +static const char * const uart2_groups[] = { "PB8", "PB9" }; +static const char * const can2_groups[] = { "PB10", "PB11" }; +static const char * const spi2_groups[] = { "PB12", "PB13", "PB14", "PB15", "PB16" }; +static const char * const spi3_groups[] = { "PB17", "PB18", "PB19", "PB20", "PB21" }; +static const char * const mclk0_groups[] = { "PB22" }; + +#define FUNCTION(a, b) { .name = a, .groups = b, .ngroups = ARRAY_SIZE(b) } + +static const struct eq5p_function eq5p_functions[] = { + /* GPIO having a fixed index is depended upon, see GPIO_FUNC_SELECTOR. */ + FUNCTION("gpio", gpio_groups), +#define GPIO_FUNC_SELECTOR 0 + + /* Bank A functions */ + FUNCTION("timer0", timer0_groups), + FUNCTION("timer1", timer1_groups), + FUNCTION("timer2", timer2_groups), + FUNCTION("timer5", timer5_groups), + FUNCTION("uart0", uart0_groups), + FUNCTION("uart1", uart1_groups), + FUNCTION("can0", can0_groups), + FUNCTION("can1", can1_groups), + FUNCTION("spi0", spi0_groups), + FUNCTION("spi1", spi1_groups), + FUNCTION("refclk0", refclk0_groups), + + /* Bank B functions */ + FUNCTION("timer3", timer3_groups), + FUNCTION("timer4", timer4_groups), + FUNCTION("timer6", timer6_groups), + FUNCTION("uart2", uart2_groups), + FUNCTION("can2", can2_groups), + FUNCTION("spi2", spi2_groups), + FUNCTION("spi3", spi3_groups), + FUNCTION("mclk0", mclk0_groups), +}; + +static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl, + enum eq5p_bank bank, enum eq5p_regs reg, + u32 mask, u32 val) +{ + void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg]; + + writel((readl(ptr) & ~mask) | (val & mask), ptr); +} + +static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl, + enum eq5p_bank bank, enum eq5p_regs reg, int offset) +{ + u32 val = readl(pctrl->base + eq5p_regs[bank][reg]); + + if (WARN_ON(offset > 31)) + return false; + + return (val & BIT(offset)) != 0; +} + +static enum eq5p_bank eq5p_pin_to_bank(unsigned int pin) +{ + if (pin < EQ5P_PIN_OFFSET_BANK_B) + return EQ5P_BANK_A; + else + return EQ5P_BANK_B; +} + +static unsigned int eq5p_pin_to_offset(unsigned int pin) +{ + if (pin < EQ5P_PIN_OFFSET_BANK_B) + return pin; + else + return pin - EQ5P_PIN_OFFSET_BANK_B; +} + +static int eq5p_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(eq5p_pins); +} + +static const char *eq5p_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return pctldev->desc->pins[selector].name; +} + +static int eq5p_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + *pins = &pctldev->desc->pins[selector].number; + *num_pins = 1; + return 0; +} + +static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config); + +static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int pin) +{ + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const char *pin_name = pctrl->desc.pins[pin].name; + unsigned int offset = eq5p_pin_to_offset(pin); + enum eq5p_bank bank = eq5p_pin_to_bank(pin); + const char *func_name, *bias; + unsigned long ds_config; + u32 drive_strength; + bool pd, pu; + int i, j; + + /* + * First, let's get the function name. All pins have only two functions: + * GPIO (IOCR == 0) and something else (IOCR == 1). + */ + if (!eq5p_test_bit(pctrl, bank, EQ5P_IOCR, offset)) { + func_name = eq5p_functions[GPIO_FUNC_SELECTOR].name; + } else { + func_name = NULL; + for (i = 0; i < ARRAY_SIZE(eq5p_functions); i++) { + if (i == GPIO_FUNC_SELECTOR) + continue; + + for (j = 0; j < eq5p_functions[i].ngroups; j++) { + /* Groups and pins are the same thing for us. */ + const char *x = eq5p_functions[i].groups[j]; + + if (strcmp(x, pin_name) == 0) { + func_name = eq5p_functions[i].name; + break; + } + } + + if (func_name) + break; + } + + /* + * We have not found the function attached to this pin, this + * should never occur as all pins have exactly two functions. + */ + if (!func_name) + func_name = "unknown"; + } + + /* Second, we retrieve the bias. */ + pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset); + pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset); + if (pd && pu) + bias = "both"; + else if (pd && !pu) + bias = "pulldown"; + else if (!pd && pu) + bias = "pullup"; + else + bias = "none"; + + /* Third, we get the drive strength. */ + ds_config = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 0); + eq5p_pinconf_get(pctldev, pin, &ds_config); + drive_strength = pinconf_to_config_argument(ds_config); + + seq_printf(s, "function=%s bias=%s drive_strength=%d", + func_name, bias, drive_strength); +} + +static const struct pinctrl_ops eq5p_pinctrl_ops = { + .get_groups_count = eq5p_pinctrl_get_groups_count, + .get_group_name = eq5p_pinctrl_get_group_name, + .get_group_pins = eq5p_pinctrl_get_group_pins, + .pin_dbg_show = eq5p_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int eq5p_pinmux_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(eq5p_functions); +} + +static const char *eq5p_pinmux_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return eq5p_functions[selector].name; +} + +static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int *num_groups) +{ + *groups = eq5p_functions[selector].groups; + *num_groups = eq5p_functions[selector].ngroups; + return 0; +} + +static int eq5p_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int func_selector, unsigned int pin) +{ + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const char *func_name = eq5p_functions[func_selector].name; + const char *group_name = pctldev->desc->pins[pin].name; + bool is_gpio = func_selector == GPIO_FUNC_SELECTOR; + unsigned int offset = eq5p_pin_to_offset(pin); + enum eq5p_bank bank = eq5p_pin_to_bank(pin); + u32 mask, val; + + dev_dbg(pctldev->dev, "%s: func=%s group=%s\n", __func__, func_name, + group_name); + + mask = BIT(offset); + val = is_gpio ? 0 : U32_MAX; + eq5p_update_bits(pctrl, bank, EQ5P_IOCR, mask, val); + return 0; +} + +static int eq5p_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + /* Pin numbers and group selectors are the same thing in our case. */ + return eq5p_pinmux_set_mux(pctldev, GPIO_FUNC_SELECTOR, pin); +} + +static const struct pinmux_ops eq5p_pinmux_ops = { + .get_functions_count = eq5p_pinmux_get_functions_count, + .get_function_name = eq5p_pinmux_get_function_name, + .get_function_groups = eq5p_pinmux_get_function_groups, + .set_mux = eq5p_pinmux_set_mux, + .gpio_request_enable = eq5p_pinmux_gpio_request_enable, + .strict = true, +}; + +static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + enum pin_config_param param = pinconf_to_config_param(*config); + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned int offset = eq5p_pin_to_offset(pin); + enum eq5p_bank bank = eq5p_pin_to_bank(pin); + u32 val_ds, arg = 0; + bool pd, pu; + + pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset); + pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = !(pd || pu); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = pd; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg = pu; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + offset *= 2; /* two bits per pin */ + if (offset >= 32) { + val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]); + offset -= 32; + } else { + val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]); + } + arg = (val_ds >> offset) & 0b11; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int eq5p_pinconf_set_drive_strength(struct pinctrl_dev *pctldev, + unsigned int pin, u32 arg) +{ + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned int offset = eq5p_pin_to_offset(pin); + enum eq5p_bank bank = eq5p_pin_to_bank(pin); + unsigned int reg; + u32 mask, val; + + if (arg > 3) { + dev_err(pctldev->dev, "Unsupported drive strength: %u\n", arg); + return -EINVAL; + } + + offset *= 2; /* two bits per pin */ + + if (offset >= 32) { + reg = EQ5P_DS_HIGH; + offset -= 32; + } else { + reg = EQ5P_DS_LOW; + } + + mask = 0b11 << offset; + val = arg << offset; + eq5p_update_bits(pctrl, bank, reg, mask, val); + return 0; +} + +static int eq5p_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const char *pin_name = pctldev->desc->pins[pin].name; + unsigned int offset = eq5p_pin_to_offset(pin); + enum eq5p_bank bank = eq5p_pin_to_bank(pin); + struct device *dev = pctldev->dev; + u32 val = BIT(offset); + unsigned int i; + + for (i = 0; i < num_configs; i++) { + enum pin_config_param param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + dev_dbg(dev, "pin=%s bias_disable\n", pin_name); + + eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0); + eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + dev_dbg(dev, "pin=%s bias_pull_down arg=%u\n", + pin_name, arg); + + if (arg == 0) /* cannot connect to GND */ + return -ENOTSUPP; + + eq5p_update_bits(pctrl, bank, EQ5P_PD, val, val); + eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + dev_dbg(dev, "pin=%s bias_pull_up arg=%u\n", + pin_name, arg); + + if (arg == 0) /* cannot connect to VDD */ + return -ENOTSUPP; + + eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0); + eq5p_update_bits(pctrl, bank, EQ5P_PU, val, val); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + dev_dbg(dev, "pin=%s drive_strength arg=%u\n", + pin_name, arg); + + eq5p_pinconf_set_drive_strength(pctldev, pin, arg); + break; + + default: + dev_err(dev, "Unsupported pinconf %u\n", param); + return -ENOTSUPP; + } + } + + return 0; +} + +static const struct pinconf_ops eq5p_pinconf_ops = { + .is_generic = true, + .pin_config_get = eq5p_pinconf_get, + .pin_config_set = eq5p_pinconf_set, + /* Pins and groups are equivalent in this driver. */ + .pin_config_group_get = eq5p_pinconf_get, + .pin_config_group_set = eq5p_pinconf_set, +}; + +static int eq5p_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pinctrl_dev *pctldev; + struct eq5p_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->base)) + return PTR_ERR(pctrl->base); + + pctrl->desc.name = dev_name(dev); + pctrl->desc.pins = eq5p_pins; + pctrl->desc.npins = ARRAY_SIZE(eq5p_pins); + pctrl->desc.pctlops = &eq5p_pinctrl_ops; + pctrl->desc.pmxops = &eq5p_pinmux_ops; + pctrl->desc.confops = &eq5p_pinconf_ops; + pctrl->desc.owner = THIS_MODULE; + + ret = devm_pinctrl_register_and_init(dev, &pctrl->desc, pctrl, &pctldev); + if (ret) { + dev_err(dev, "Failed registering pinctrl device: %d\n", ret); + return ret; + } + + ret = pinctrl_enable(pctldev); + if (ret) { + dev_err(dev, "Failed enabling pinctrl device: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id eq5p_match[] = { + { .compatible = "mobileye,eyeq5-pinctrl" }, + {}, +}; + +static struct platform_driver eq5p_driver = { + .driver = { + .name = "eyeq5-pinctrl", + .of_match_table = eq5p_match, + }, + .probe = eq5p_probe, +}; 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745483; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YjzH8us36qfzbp3mhYrknBNc6xeLQlFhaU/yX/UTwvc=; b=Q4f4eUDZVfiGYGj1EG83eH4M3hyZfU8R6jntvSoDeeycvBzsEcymx1t/FZAdEXaMxL1qUO 8eQjFJNQafi+NQk3G9nBTl1cx5pC5D1BQPUSTU79hsc4idcLORi5wGvJT72UsfW91M7y5O cm2XzWaIUxOCxsYEeDLqSg5cm9MFdjj00s/mI9e12YOaDhFqLgeyxvVb+xOK8EyrdP15d4 4mD0RqrspkYtE85Il1Pc0EoRC0a7yahoAkNFl92QH4rKgx+fC2HvTfYbhFrGXp/MEbWO72 1OTeRqWxfhJRHFguUgc+KbOfmAK8aBmUaM9Wlh5VoTdStg21abm3QVK4z1A8Fg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:41 +0100 Subject: [PATCH v6 10/13] MIPS: mobileye: eyeq5: add OLB syscon node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-10-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790701500938071932 X-GMAIL-MSGID: 1790701500938071932 The OLB ("Other Logic Block") is a syscon region hosting the clock, reset and pin controllers. It contains registers such as I2C speed mode that need to be accessible by other nodes. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 6cc5980e2fa1..e82d2a57f6da 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -100,6 +100,14 @@ uart2: serial@a00000 { clock-names = "uartclk", "apb_pclk"; }; + olb: system-controller@e00000 { + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; + reg = <0 0xe00000 0x0 0x400>; + ranges = <0x0 0x0 0xe00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + gic: interrupt-controller@140000 { compatible = "mti,gic"; reg = <0x0 0x140000 0x0 0x20000>; From patchwork Mon Feb 12 13:44:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199810 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2439413dyd; Mon, 12 Feb 2024 05:54:30 -0800 (PST) X-Google-Smtp-Source: AGHT+IHyxg31ocRCOzmlJATzmc+4fuM4gaHyBzEBw+S8SXJSV2N1dppJmwq3Ls9F45cyEkKaQ4i3 X-Received: by 2002:a17:906:395:b0:a3b:b334:2f26 with SMTP id b21-20020a170906039500b00a3bb3342f26mr4778867eja.61.1707746070411; Mon, 12 Feb 2024 05:54:30 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707746070; cv=pass; d=google.com; s=arc-20160816; b=Y8mgZ0vY6sfL41f1DSTxdRpOmzCVeDfO44FFpju/XsqLBbHDSAQKZ4zux+Uen4x19Q AjcOCTBKjhvu08Rdc8awPhdGZUvpsA2F3sqmBe8Q47hD8gMKqOOFZsmSpPx/ybS5Z/rb mFxVSuKHkDHa9BgX/TS2F/VRZDInyy4L1nFsb9GTZHpgZgDF/XYRoSK47EoV0q9e4Lq7 zldVTLOS5OdW2e8ierheYTypbPj4VeqV+BNJbkYXO621DAsBdsT9J3M5dtgmHTK+jbqy PYd3vpLwyMcS5HT+i2HZmCprvhqv54bvMM43/Qa9aQIA+SszYb8RoL6coj8y7txNzjRj 04Gw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=wi8jwip8WrhGTKLzAJSMQEzhaSDon8uDm4Ah20T+FYE=; fh=1SLtHWyVW1/Bx1wCwpJbatO0e0um/eo9KeodRLFuOkY=; b=wey13yKEXOl3TFfKGUwN2/hZ1n/m4a98qa+GOLJ/I9dBK/vClWu3cbid0karF1Tete p0McM6rlzKhtUs9CzU6Y1aYNrXwePLLUp7taspYh3e8Jcptfu6lwz2mVqG9ZWqB0OB0/ vHDaPNagbIq/m0I4uhJrvWTrtrRY3FkYKb7FAuIqO6LP5tE3qtG0yrqOXPhNXFIseYz0 4+tF0VBqfWjxLKgf9jymy+7KXkLUWIBPhxDC8TwUcXckYARTbUBgPxtO93kUq2oPVje4 reFg/vfPcoxAMZpUwZYimL0g5nKj/0NGnRcaRjnouvM22CqUbvLhlZO0Ik1JtZBIXrLh iADA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=I7hfupym; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-61740-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61740-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=2; AJvYcCX+hELajTU1xBOb9Qj9pBDhi80iBjihWS4306zj+Mo+djDU2t1sAyp41EiyCyUapQ1K99r33yz7By9z2d4EGgrGtCLstg== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745484; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wi8jwip8WrhGTKLzAJSMQEzhaSDon8uDm4Ah20T+FYE=; b=I7hfupymM/IlNjvC78CBmtDt9lxmNUGxedWs5b78wThPouo1GA0ClmkmMi5fpUyG5XOnYa hvDtpTwlS6XI3nCTxLu0lXs174M3K5bLECkFRWw/uZy6M462h565Nnue1ZOrsmZNsvhUqz yZaaZqk9zbaJNP/TRLnVGJlzXB4zVWkipbvONV+0X1d0hpdkyY2aq/RLQIE6YJrS4Nz2HM Hzy0eWhhBpVP8afFJP6qbVPkPgukmcIxkLLG3zVQuRosmA3h9xGm4TIkCydK1OmJLWrWzg 0TN/OSW22KkNlvWTsjwoehkL4vPTPzYD3zMi1PPQKyr85zrTRoaRBlasH8YDFg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:42 +0100 Subject: [PATCH v6 11/13] MIPS: mobileye: eyeq5: use OLB clocks controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-11-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790701543359728097 X-GMAIL-MSGID: 1790701543359728097 We add the clock controller inside the OLB syscon region and remove previous fixed devicetree nodes representing PLLs exposed by the clock controller. Signed-off-by: Théo Lebrun --- .../{eyeq5-fixed-clocks.dtsi => eyeq5-clocks.dtsi} | 54 +++++++--------------- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 11 ++++- 2 files changed, 26 insertions(+), 39 deletions(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi similarity index 88% rename from arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi rename to arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi index 78f5533a95c6..aa6db704a786 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi @@ -3,42 +3,20 @@ * Copyright 2023 Mobileye Vision Technologies Ltd. */ +#include + / { /* Fixed clock */ - pll_cpu: pll-cpu { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1500000000>; - }; - - pll_vdi: pll-vdi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1280000000>; - }; - - pll_per: pll-per { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - - pll_ddr0: pll-ddr0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1857210000>; - }; - - pll_ddr1: pll-ddr1 { + xtal: xtal { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <1857210000>; + clock-frequency = <30000000>; }; /* PLL_CPU derivatives */ occ_cpu: occ-cpu { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <1>; clock-mult = <1>; @@ -101,7 +79,7 @@ mem_clk: mem-clk { }; occ_isram: occ-isram { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -115,7 +93,7 @@ isram_clk: isram-clk { /* gate ClkRstGen_isram */ }; occ_dbu: occ-dbu { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <10>; clock-mult = <1>; @@ -130,7 +108,7 @@ si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ /* PLL_VDI derivatives */ occ_vdi: occ-vdi { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -144,7 +122,7 @@ vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ }; occ_can_ser: occ-can-ser { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; @@ -158,7 +136,7 @@ can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ }; i2c_ser_clk: i2c-ser-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <20>; clock-mult = <1>; @@ -166,7 +144,7 @@ i2c_ser_clk: i2c-ser-clk { /* PLL_PER derivatives */ occ_periph: occ-periph { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; @@ -225,7 +203,7 @@ gpio_clk: gpio-clk { }; emmc_sys_clk: emmc-sys-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <10>; clock-mult = <1>; @@ -233,7 +211,7 @@ emmc_sys_clk: emmc-sys-clk { }; ccf_ctrl_clk: ccf-ctrl-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; @@ -241,7 +219,7 @@ ccf_ctrl_clk: ccf-ctrl-clk { }; occ_mjpeg_core: occ-mjpeg-core { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -265,7 +243,7 @@ mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ }; fcmu_a_clk: fcmu-a-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <20>; clock-mult = <1>; @@ -273,7 +251,7 @@ fcmu_a_clk: fcmu-a-clk { }; occ_pci_sys: occ-pci-sys { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index e82d2a57f6da..1a65b43e13b1 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -5,7 +5,7 @@ #include -#include "eyeq5-fixed-clocks.dtsi" +#include "eyeq5-clocks.dtsi" / { #address-cells = <2>; @@ -106,6 +106,15 @@ olb: system-controller@e00000 { ranges = <0x0 0x0 0xe00000 0x400>; #address-cells = <1>; #size-cells = <1>; + + clocks: clock-controller@e0002c { + compatible = "mobileye,eyeq5-clk"; + reg = <0x02c 0x50>, <0x11c 0x04>; + reg-names = "plls", "ospi"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; }; gic: interrupt-controller@140000 { From patchwork Mon Feb 12 13:44:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199809 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2439337dyd; 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745484; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BaAH/txD0ZSJCug0F9IruK7CsdNif1nz4F+71F4j3Ts=; b=Vy96bdXJeXnd6fVN3a30bH/PBBI8xN/2tianri1oWSW0Q1EllkegwlV+lwXoF4E1ougfY6 ZgoriIaddapZwgOSOBZF9rRNFBoVbBlDEJfK2ZD0PUa3bGQSepwKHV2RkHTnM7hz6WmlbR 8iWvNMuFJg2S/vRRWRP7MPmNZT8/HyVHlpz1eviGZukcOS3qOv7iF3KgWcrOdDOqnLfVFK 8jctAXsFQP553X1KfJi9DoBV6TCic+HyX1fT8ksTv7WlLY7awq/0ZHAKIoDqPet+8nbHJl BlMmAR7m9E2TAZ+txAO8/gWFK35bY89bykhGG/Lh2NVyPpDEPVcyP8PQSM6AsQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:43 +0100 Subject: [PATCH v6 12/13] MIPS: mobileye: eyeq5: add OLB reset controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-12-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790701534729828191 X-GMAIL-MSGID: 1790701534729828191 Add the devicetree node for the reset controller on the Mobileye EyeQ5 platform. It appears as a subnode to the OLB syscon as its registers are located in this shared register region. Add reset phandles to UART nodes. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 1a65b43e13b1..76935f237ab5 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -78,6 +78,7 @@ uart0: serial@800000 { interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 10>; }; uart1: serial@900000 { @@ -88,6 +89,7 @@ uart1: serial@900000 { interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 11>; }; uart2: serial@a00000 { @@ -98,6 +100,7 @@ uart2: serial@a00000 { interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 12>; }; olb: system-controller@e00000 { @@ -107,6 +110,13 @@ olb: system-controller@e00000 { #address-cells = <1>; #size-cells = <1>; + reset: reset-controller@e00000 { + compatible = "mobileye,eyeq5-reset"; + reg = <0x000 0x0c>, <0x200 0x34>, <0x120 0x04>; + reg-names = "d0", "d1", "d2"; + #reset-cells = <2>; + }; + clocks: clock-controller@e0002c { compatible = "mobileye,eyeq5-clk"; reg = <0x02c 0x50>, <0x11c 0x04>; From patchwork Mon Feb 12 13:44:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199811 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2440247dyd; Mon, 12 Feb 2024 05:56:15 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUdjaFdSs3b4Xjr/MBm4iRCLnzzLqD+t/zEphvsJSAd2Ril5n/gFV34+nqy3Po3GVrk+VWdDNDZcbL41kSU1yZsxfW4OA== X-Google-Smtp-Source: AGHT+IExYX43bLuFhKpUwHs3enodsFMFUsK8zmUIil/WpkAIUUgQXFGieMocpla8bMSU3kTQDs2t X-Received: by 2002:a17:902:f545:b0:1d9:9e4f:c0b3 with SMTP id h5-20020a170902f54500b001d99e4fc0b3mr5602260plf.64.1707746175201; Mon, 12 Feb 2024 05:56:15 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707746175; cv=pass; d=google.com; s=arc-20160816; b=ndFO8lUiomTsCYV8bYgfa4CVAmp7LURGnJJKVguFpovJ14srk4UGX+QoONkwKtDPE9 wSDR+9C50gE4IktEXqYDJ+hZJik7CjBFN9bLKPa3fSWxG54ZDxk0mW2z8UIlu4Yw3DLI sxbcR0yUPxqu7y8BQ6naEKyOsWm27TDrAGnLC5aLTbTvOrFUa6gh2PY+a1Sg06yVi3sq xebwJx4UnxceDSfKW02A6qBwpeDs/jH4tOCX7lDf1niQGJiFabo7axvuK6wS6ZkbyGrL V4iNvTTItvltMRHHk9SPOWLzFsYZd3W8ZhGmUdCjkEUtSAUvvWcPBJGDA8fTu0sVpOlM kd+Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=ntwnUlVjSIXSSPhME4Hzl2L0UVU1UFUtEinrPzePqbc=; fh=IMUhj/+ND1TqjvPxw3AKPEkDOd2F45raMwsbVQJhBSM=; b=FYRo0ph6Pc6hTXKk/dacjlzdBGgriZR37G89GGgl0rOu6hrfr69XKkxyG5hAk/9f6h b7NKTOLpFlquE15qvvLzkhLH8Py7BMU6VA/aUNvrWVupgW/yQw+ZYfXnBbCQ9IXtpFPy X3qS4ptOYguJW4OeJ0RRF5zwARCe3e27fVbh0kngP9O7QXA5wHlh8+Q4MfOTZy+HSVx4 xkqYkl8ADjeLLQcVHmOkO2ePLmGS9IAcKW+e9WQOLD5m1o9tBzPoov99T0O9DYi+p1Kj m3GlXyOKywKksvPUyL/bb37OVrM+jKjspbJ3zh7El3Rcc7CRNntzFpsUcQY0YvAFLVCr jzQg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=FEuE7F60; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-61742-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61742-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=2; AJvYcCXBPOTwS6ZezZDqMuEZQj7jPH71zUe0fkQ6wcH11858LxansmiEGhGW6C2Iv08W8J3nSOj1s/Qk9G0bipsS3bQlXgWImA== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745485; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ntwnUlVjSIXSSPhME4Hzl2L0UVU1UFUtEinrPzePqbc=; b=FEuE7F60GbzlKRHPPJBWauRvqMcuSgV8RV3aIUMUmQyFbdDZBR6GhUc1Icb5cwl4iLA6Wa sG+z4mYAo0SPRU5zatybX2y2De23/gGgNld179CWO46ltbv4YBcOiNVkD07Kjs/i1vCi64 mCzPyQZ3KTYcb4UHvLPAsjb7t9GEemSpU7ctBusSKKeC80/u86AdcQ/QbhmdQD/uANZGn3 5vlQswfP609J3hRyVVzBonv0Mz9u/WM6jZr6LOm2mKuwN60aCMbe6qXIMqiNgAxJiC1Lup gWZjBn5LqwmE0Fvw9Y3GwX/eNkVvvvk1uuQHaTO++nmygxsej7TK4RnFOQn2KA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:44 +0100 Subject: [PATCH v6 13/13] MIPS: mobileye: eyeq5: add pinctrl node & pinmux function nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-13-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790701653236719237 X-GMAIL-MSGID: 1790701653236719237 Pins on this platform have two functions: GPIO or something-else. We create function nodes for each something-else based on functions. UART nodes are present in the platform devicetree. Add pinctrl to them now that the pin controller is supported. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi | 125 ++++++++++++++++++++++++++++ arch/mips/boot/dts/mobileye/eyeq5.dtsi | 13 +++ 2 files changed, 138 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi new file mode 100644 index 000000000000..42acda13e57a --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +/* + * Default pin configuration for Mobileye EyeQ5 boards. We mostly create one + * pin configuration node per function. + */ + +&pinctrl { + timer0_pins: timer0-pins { + function = "timer0"; + pins = "PA0", "PA1"; + }; + timer1_pins: timer1-pins { + function = "timer1"; + pins = "PA2", "PA3"; + }; + timer2_pins: timer2-pins { + function = "timer2"; + pins = "PA4", "PA5"; + }; + pps0_pins: pps0-pin { + function = "timer2"; + pins = "PA4"; + }; + pps1_pins: pps1-pin { + function = "timer2"; + pins = "PA5"; + }; + timer5_ext_pins: timer5-ext-pins { + function = "timer5"; + pins = "PA6", "PA7", "PA8", "PA9"; + }; + timer5_ext_input_pins: timer5-ext-input-pins { + function = "timer5"; + pins = "PA6", "PA7"; + }; + timer5_ext_incap_a_pins: timer5-ext-incap-a-pin { + function = "timer5"; + pins = "PA6"; + }; + timer5_ext_incap_b_pins: timer5-ext-incap-b-pin { + function = "timer5"; + pins = "PA7"; + }; + can0_pins: can0-pins { + function = "can0"; + pins = "PA14", "PA15"; + }; + can1_pins: can1-pins { + function = "can1"; + pins = "PA16", "PA17"; + }; + uart0_pins: uart0-pins { + function = "uart0"; + pins = "PA10", "PA11"; + }; + uart1_pins: uart1-pins { + function = "uart1"; + pins = "PA12", "PA13"; + }; + spi0_pins: spi0-pins { + function = "spi0"; + pins = "PA18", "PA19", "PA20", "PA21", "PA22"; + }; + spi1_pins: spi1-pins { + function = "spi1"; + pins = "PA23", "PA24", "PA25", "PA26", "PA27"; + }; + spi1_slave_pins: spi1-slave-pins { + function = "spi1"; + pins = "PA24", "PA25", "PA26"; + }; + refclk0_pins: refclk0-pin { + function = "refclk0"; + pins = "PA28"; + }; + timer3_pins: timer3-pins { + function = "timer3"; + pins = "PB0", "PB1"; + }; + timer4_pins: timer4-pins { + function = "timer4"; + pins = "PB2", "PB3"; + }; + timer6_ext_pins: timer6-ext-pins { + function = "timer6"; + pins = "PB4", "PB5", "PB6", "PB7"; + }; + timer6_ext_input_pins: timer6-ext-input-pins { + function = "timer6"; + pins = "PB4", "PB5"; + }; + timer6_ext_incap_a_pins: timer6-ext-incap-a-pin { + function = "timer6"; + pins = "PB4"; + }; + timer6_ext_incap_b_pins: timer6-ext-incap-b-pin { + function = "timer6"; + pins = "PB5"; + }; + can2_pins: can2-pins { + function = "can2"; + pins = "PB10", "PB11"; + }; + uart2_pins: uart2-pins { + function = "uart2"; + pins = "PB8", "PB9"; + }; + spi2_pins: spi2-pins { + function = "spi2"; + pins = "PB12", "PB13", "PB14", "PB15", "PB16"; + }; + spi3_pins: spi3-pins { + function = "spi3"; + pins = "PB17", "PB18", "PB19", "PB20", "PB21"; + }; + spi3_slave_pins: spi3-slave-pins { + function = "spi3"; + pins = "PB18", "PB19", "PB20"; + }; + mclk0_pins: mclk0-pin { + function = "mclk0"; + pins = "PB22"; + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 76935f237ab5..8d4f65ec912d 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -79,6 +79,8 @@ uart0: serial@800000 { clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; resets = <&reset 0 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; }; uart1: serial@900000 { @@ -90,6 +92,8 @@ uart1: serial@900000 { clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; resets = <&reset 0 11>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; }; uart2: serial@a00000 { @@ -101,6 +105,8 @@ uart2: serial@a00000 { clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; resets = <&reset 0 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; }; olb: system-controller@e00000 { @@ -125,6 +131,11 @@ clocks: clock-controller@e0002c { clocks = <&xtal>; clock-names = "ref"; }; + + pinctrl: pinctrl@e000b0 { + compatible = "mobileye,eyeq5-pinctrl"; + reg = <0x0b0 0x30>; + }; }; gic: interrupt-controller@140000 { @@ -149,3 +160,5 @@ timer { }; }; }; + +#include "eyeq5-pins.dtsi"