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Mon, 12 Feb 2024 02:37:35 -0800 (PST) From: Neil Armstrong Date: Mon, 12 Feb 2024 11:37:30 +0100 Subject: [PATCH 1/5] dt-bindings: display/msm/gmu: Document Adreno 750 GMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-topic-sm8650-gpu-v1-1-708a40b747b5@linaro.org> References: <20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org> In-Reply-To: <20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790689256953764343 X-GMAIL-MSGID: 1790689256953764343 Document the Adreno 750 GMU found on the SM8650 platform. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 4e1c25b42908..b3837368a260 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -224,6 +224,7 @@ allOf: enum: - qcom,adreno-gmu-730.1 - qcom,adreno-gmu-740.1 + - qcom,adreno-gmu-750.1 then: properties: reg: From patchwork Mon Feb 12 10:37:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 199640 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2346578dyd; Mon, 12 Feb 2024 02:38:39 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUo7tFKEwYjdcCdk+gLRRadUfClEQ9whcBN5gYD8knlrUliQXfQ6KYiFeBOAEbCIrAj3Tw2PeRd+sW+PsuVF1m+Z5lDwg== X-Google-Smtp-Source: AGHT+IGYeACHarp6YL3ccu47Z4ZVt012I1IMDIN1I9FgSGRTBWsbScfUhJ/R/u8thGdwVEmvJNKp X-Received: by 2002:a05:620a:4085:b0:785:9704:148b with SMTP id f5-20020a05620a408500b007859704148bmr8320471qko.58.1707734319377; Mon, 12 Feb 2024 02:38:39 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707734319; cv=pass; d=google.com; s=arc-20160816; b=d0NLUNn+vGM1sultYJVwL5CKa2BJwgirI+/QcEwP3Cd04nUCuuuK4q/zVheF+BZbTP DddjnFxaWFOgwiuGmLR17XYiHxUJVQ/deL7hCwWjhkC3sclJNX4TbGWIoWEpTOAYjaRv 6Dwn5/vHmYwgIDsY7Y6TINQHQc6D++0Cbun5/b7AwZaw3hWPXOhqUaXmDaV39PDSFRvn g59I0mWSTd0eVutpaFMbALwukai2xpTc7dV0nulvrWsnzWco8Lr7cRkDhqyoztmonY4N e23yWJBmc+AnYHN3CgvRnZPVxXsQ37DRfq1rJuH2BzQXuGdqtCNDwfw/aEQHha/DJW2L 232Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=rJagULZ78/2FNiklIv2V0yaJYekfWzVBl7+5o+wg9ug=; fh=KOwl0fmVEY7P0VKoSVLD5Sf4wr5ApmJYqE18DboBBiY=; b=tHf3SbCbjkDjcNPFXInakZKYkS1JHXrtESukZTSCbU8jKnFaPYYVw5ZbKmhtLLac99 XgX/ToTcS3xrqtKVOWNJQ1ZCsrCGqProBYWmrpvVdmKKiwbfVzXAhjlNBS1HPQ/14TQe i5MEEhBrFCD20aKjB8Y2oIOxAqxy91MGXCGKb6YGNyIsd+DFBvDnBr9q3A984zt9D1UA ADhZiqVwBaVLfDPxDzKSdhYF6lBfhHKJjkFIMBqeJOvHIf8KZZGbcTfLi2IfdvUM0e1K xTZ2C4Hgn+vIkAv4IObvKhdjxMhYI3dP9c0yolhbl1C7hyjXpOTufvle/8fpPkA99hXB 0h9A==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HFlZe2Wn; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61329-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61329-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCU/FcjUm2tRUXjN+rXowL0O7SSc9C8nVYOxTVxb0CsZGLHQ4ucXA1lINip2OTmQTk3ouZx4yj18p9dnC1Yy0psqJezXzg== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Mon, 12 Feb 2024 02:37:36 -0800 (PST) From: Neil Armstrong Date: Mon, 12 Feb 2024 11:37:31 +0100 Subject: [PATCH 2/5] dt-bindings: arm-smmu: Document SM8650 GPU SMMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-topic-sm8650-gpu-v1-2-708a40b747b5@linaro.org> References: <20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org> In-Reply-To: <20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790689221553351433 X-GMAIL-MSGID: 1790689221553351433 Document the GPU SMMU found on the SM8650 platform. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index a4042ae24770..3ad5c850f3bf 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -93,6 +93,7 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -508,7 +509,10 @@ allOf: - if: properties: compatible: - const: qcom,sm8550-smmu-500 + contains: + enum: + - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 then: properties: clock-names: @@ -544,7 +548,6 @@ allOf: - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 then: properties: From patchwork Mon Feb 12 10:37:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 199641 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2346740dyd; Mon, 12 Feb 2024 02:39:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IFcC6gXAgWVtz71MtIYEfO3TyTnJraUzw+nQwJcaX7tmjeTfPLSr86sylDqMy2vLbIK39+a X-Received: by 2002:a17:902:cec3:b0:1d9:39b4:2039 with SMTP id d3-20020a170902cec300b001d939b42039mr11559639plg.30.1707734348787; Mon, 12 Feb 2024 02:39:08 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707734348; cv=pass; d=google.com; s=arc-20160816; b=u8J1SAqG5G89ysGunf6Vl4yQ8g+8yzckpguWHcdkA3Oen/ZCo3xObY6bv9/dNWQKUE HRctUEw/+wde8WQB/87tYLRhvNVVpCLZxDi86hFBW8pDyhrDg/4IW/CU3oQ7jsTkbMok 08sRl+KVSdlfbnjIL6gz5/LdyObq6tLuwyuARaE3Pnc8TdsLEMgUP/VkFJusMKLx69Tb WHIAake2MCowBkzYTkql1qPF1WWUQeM5r9jJwaJsVQwrxN2HePrgLU1kAxM+7aZtxB7X 6ziCf4K58/y1YF+7/tGYmrEwzv46vrp70UnkR94koP/vVoI/5F/T4yIYTyFkpZr+5KjJ nx3w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=qwfVS+Td8YMY3ebZOXzlWppW1EsDh7tKAqBML4ltt8s=; fh=RVslxJIRahMtF4S3EYXJDF1aCU8w9sY/EGOYyyGdpdU=; b=sJuVk+CNTtTzDs8yEQ87wUb1Ys9H0e2E/Ff86sWnoVZRD+Bo7LQquMcZvGDlEQjqES RZhWyFoAT8bWMjvEfQamGj/0dH65VmDQl89DQ5K54ZTuoLHWAWwMvVLxg0PHbRBJebS4 W4T5mIKzOekaUq6h7mSczEpzbXIW7GmNdMW+hDmfQDTxMUhukXrYEiamzJzgOjwahdoa OirPrn+b5Dgz9YK7XIDMZ/MNZu1njLauJ4aqYB1EvImMEtbXXaShCHhU6ipgqqj0RqoZ akhBGP3P2qDDd9XnvJvtg1a19uZ2cptMtBnVlj0ytO5vxDrVSHLjlqE8eTZAHAcCXsHf siXg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x1FCjYT2; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-61330-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61330-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCVn5c1ZH4HgJFDucS5ovc7fd/GquwrB/7F3gkovYWQHW6joaeM3j3fT5bnMThqJbBIt803yNa1I0IAEqRtLDK7BH0wkFQ== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Mon, 12 Feb 2024 02:37:37 -0800 (PST) From: Neil Armstrong Date: Mon, 12 Feb 2024 11:37:32 +0100 Subject: [PATCH 3/5] drm: msm: add support for A750 GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-topic-sm8650-gpu-v1-3-708a40b747b5@linaro.org> References: <20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org> In-Reply-To: <20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790689252094382066 X-GMAIL-MSGID: 1790689252094382066 Add support for the A750 GPU found on the SM8650 platform Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The missing registers are added in the a6xx.xml.h file that would require a subsequent sync and the non-existent hwcfg is handled in a6xx_set_hwcg(). The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 ++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 29 ++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 9 ++++++++- 5 files changed, 58 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 863b5e3b0e67..c4db4e0c0819 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1725,6 +1725,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 +#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad + #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 @@ -1939,12 +1941,18 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d +#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e + +#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f + #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122 + #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 8c4900444b2c..325881d8ff08 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -842,6 +842,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) */ if (adreno_is_a740(adreno_gpu)) chipid_min = 2; + else if (adreno_is_a750(adreno_gpu)) + chipid_min = 9; else return -EINVAL; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c0bc924cd302..472991584053 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -958,10 +958,11 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; const struct adreno_reglist *reg; + bool skip_programming = !(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu)); unsigned int i; u32 val, clock_cntl_on, cgc_mode; - if (!adreno_gpu->info->hwcg) + if (skip_programming) return; if (adreno_is_a630(adreno_gpu)) @@ -982,6 +983,25 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) state ? 0x5555 : 0); } + if (!adreno_gpu->info->hwcg) { + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); + gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); + + if (state) { + gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); + + if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, + val & BIT(0), 1, 10)) { + dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); + return; + } + + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); + } + + return; + } + val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); /* Don't re-program the registers if they are already correct */ @@ -1239,7 +1259,9 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) count = ARRAY_SIZE(a660_protect); count_max = 48; BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); - } else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) { + } else if (adreno_is_a730(adreno_gpu) || + adreno_is_a740(adreno_gpu) || + adreno_is_a750(adreno_gpu)) { regs = a730_protect; count = ARRAY_SIZE(a730_protect); count_max = 48; @@ -2880,7 +2902,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || - config->info->family == ADRENO_7XX_GEN2; + config->info->family == ADRENO_7XX_GEN2 || + config->info->family == ADRENO_7XX_GEN3; a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2ce7d7b1690d..e2582c91d7e7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -522,6 +522,20 @@ static const struct adreno_info gpulist[] = { .zapfw = "a740_zap.mdt", .hwcg = a740_hwcg, .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ + .family = ADRENO_7XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "gen70900_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70900.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "gen70900_zap.mbn", + .address_space_size = SZ_16G, }, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index bc14df96feb0..744fa18067f8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -48,6 +48,7 @@ enum adreno_family { ADRENO_6XX_GEN4, /* a660 family */ ADRENO_7XX_GEN1, /* a730 family */ ADRENO_7XX_GEN2, /* a740 family */ + ADRENO_7XX_GEN3, /* a750 family */ }; #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) @@ -423,12 +424,18 @@ static inline int adreno_is_a740(struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x43050a01; } +static inline int adreno_is_a750(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x43051401; +} + /* Placeholder to make future diffs smaller */ static inline int adreno_is_a740_family(struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return gpu->info->family == ADRENO_7XX_GEN2; + return gpu->info->family == ADRENO_7XX_GEN2 || + gpu->info->family == ADRENO_7XX_GEN3; } static inline int adreno_is_a7xx(struct adreno_gpu *gpu) From patchwork Mon Feb 12 10:37:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 199643 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2346794dyd; Mon, 12 Feb 2024 02:39:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IHS/D8HVPYQsmAn2FIODcTwQFOwJ1VpV/QIMjEz19aGsjcLBnu8fHoF5jb8M2mRCMahw9VR X-Received: by 2002:a17:906:fc06:b0:a3c:3299:9a9f with SMTP id ov6-20020a170906fc0600b00a3c32999a9fmr4668752ejb.13.1707734359143; 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Mon, 12 Feb 2024 02:37:39 -0800 (PST) From: Neil Armstrong Date: Mon, 12 Feb 2024 11:37:33 +0100 Subject: [PATCH 4/5] arm64: dts: qcom: sm8650: add GPU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-topic-sm8650-gpu-v1-4-708a40b747b5@linaro.org> References: <20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org> In-Reply-To: <20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790689263519553753 X-GMAIL-MSGID: 1790689263519553753 Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 169 +++++++++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index c455ca4e6475..f6f9e603fb2f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2582,6 +2582,131 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43051401", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-629000000 { + opp-hz = /bits/ 64 <629000000>; + opp-level = ; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = ; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-level = ; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + }; + + opp-231000000 { + opp-hz = /bits/ 64 <231000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = ; + }; + + opp-260000000 { + opp-hz = /bits/ 64 <260000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8650-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -2595,6 +2720,50 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; From patchwork Mon Feb 12 10:37:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 199644 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2346819dyd; Mon, 12 Feb 2024 02:39:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IGFJxv5RbY3SximmUjgm9rmFbsYFyzZpoNqM/g37y3L8xUTtENYWy5fKRl/y4PM+R6SWYjH X-Received: by 2002:a05:6808:1813:b0:3bd:d8a6:a4c0 with SMTP id bh19-20020a056808181300b003bdd8a6a4c0mr7521279oib.46.1707734363794; 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Mon, 12 Feb 2024 02:37:40 -0800 (PST) From: Neil Armstrong Date: Mon, 12 Feb 2024 11:37:34 +0100 Subject: [PATCH 5/5] arm64: dts: qcom: sm8650-qrd: enable GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-topic-sm8650-gpu-v1-5-708a40b747b5@linaro.org> References: <20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org> In-Reply-To: <20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790689268357863860 X-GMAIL-MSGID: 1790689268357863860 Add path of the GPU firmware for the SM8650-QRD board Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 8515498553bf..7151f3dc67c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -525,6 +525,14 @@ &ipa { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + &mdss { status = "okay"; };