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Cc: stable@kernel.org Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Signed-off-by: Samuel Holland Reviewed-by: Andrew Jones --- arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..2468c55933cd 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -424,6 +424,7 @@ # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE # define CSR_TVEC CSR_MTVEC +# define CSR_ENVCFG CSR_MENVCFG # define CSR_SCRATCH CSR_MSCRATCH # define CSR_EPC CSR_MEPC # define CSR_CAUSE CSR_MCAUSE @@ -448,6 +449,7 @@ # define CSR_STATUS CSR_SSTATUS # define CSR_IE CSR_SIE # define CSR_TVEC CSR_STVEC +# define CSR_ENVCFG CSR_SENVCFG # define CSR_SCRATCH CSR_SSCRATCH # define CSR_EPC CSR_SEPC # define CSR_CAUSE CSR_SCAUSE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..c5b13f7dd482 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -950,7 +950,7 @@ arch_initcall(check_unaligned_access_all_cpus); void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) - csr_set(CSR_SENVCFG, ENVCFG_CBZE); + csr_set(CSR_ENVCFG, ENVCFG_CBZE); } #ifdef CONFIG_RISCV_ALTERNATIVE From patchwork Mon Feb 12 02:26:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 199564 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2196535dyd; Sun, 11 Feb 2024 18:27:18 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUaaprDZrLZJczvhsozB0StuUGra2wLf/H2nrbqMlJU2XN3jOF6LRl9St9BjmJtLRpJRO1vi1IoILj83VpZ5OEI7lV8gg== X-Google-Smtp-Source: AGHT+IFRC9hDqSxUrwq2zqwti1Vohrf+McyeOMiY5NXv0vait4TieSM8l1khTLg5b1jYfZcioXlt X-Received: by 2002:a05:6512:5c3:b0:511:86a2:7ea with SMTP id o3-20020a05651205c300b0051186a207eamr2299316lfo.33.1707704837721; Sun, 11 Feb 2024 18:27:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707704837; cv=pass; d=google.com; s=arc-20160816; b=OLkhEC33JGak8bJEtnZ/lnullD4G+hV1mxv0eAIay03KPywH4+MoZIWKy5e8F3gDs2 2X3sX6MlKNNTdbFzN1V2isWlwCbnC1BzDhXADkmVHk3e+z5nuP+plsUY1ha9l9Dj2G/N mpmaTBp+VnJrNc/2Ma4CVuLIDyIfQsJm+9Sxhh51aPmm5RLeANu0+qklWnrR55r5y3Hs ERXftG66Wi1Fqkr4a1oezjolxGslCpjKxxnEdi1hI330llJRFUWXZVPJnzQi8e86BeaI ct1lAGdGmC5csjB2PoYibXs4fa5k2yRKKVSQ1JebWoZT/j+lqjtb/ZaNlCZmf8PhUsci hJDg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=wExfnkW+ofqoMhPp98EXVpYHYdKKuq8sVv8wNwYyPSY=; fh=iVf3XZmN/EGd3TclSb7GtKpMNdj5Aj9pWzoGjvUlrvI=; b=QRNUd55yPlV4XD9KpDmY8QraI7NXQyiRsyYh0Szr1F5D5WreorM1xQKXY+LMad14u6 MmhRxsH5wzq9DnqRJjwpZCjb8xWgIlVGK+4VBtRJCGU3KpCEbxt9kPE5N3z32vbt26ED ruEklEypMkg9azzhmsuZtvsxqBuTPQd5cHJNBzckpCU6IfttChKQ1jUNohBr3wGGhpdo VgNgPEoYRZAPAtWvmXFeLw1tvRGloNLJSu9wnVsueByxz/RE13aDAvsssmNdqxh+5etG ysgkxpXgUtrRN00c/eRTqtEAh3+YxhDLRf2dX+s1HrxD3VXe4QRSAL8DCYEYJb7em0nd 5P2g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=AgLGh7Xp; arc=pass (i=1 spf=pass spfdomain=sifive.com dkim=pass dkdomain=sifive.com dmarc=pass fromdomain=sifive.com); spf=pass (google.com: domain of linux-kernel+bounces-61068-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61068-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=sifive.com X-Forwarded-Encrypted: i=2; AJvYcCVTvmlzIs3kvnCt2BOkx30RwwgTqYnpRACLEHLQDYzDf5mOQ9rzIP7OnGsYc+BedKSrltjm1GGnJbWyk8UzgyAafx607Q== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Because the [ms]envcfg CSR is part of the base RISC-V privileged ISA specification, it cannot be detected from the ISA string. However, most existing hardware is too old to implement this CSR. As a result, it must be probed at runtime. Extend the logic for the Zicsr ISA extension to probe for the presence of specific CSRs. Since the CSR number is encoded as an immediate value within the csrr instruction, a switch case is necessary for any CSR that must be probed this way. Use the exception table to handle the illegal instruction exception raised when the CSR is not implemented. Cc: stable@kernel.org Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Signed-off-by: Samuel Holland Reviewed-by: Andrew Jones --- arch/riscv/include/asm/csr.h | 23 +++++++++++++++++++++++ arch/riscv/include/asm/suspend.h | 1 + arch/riscv/kernel/cpufeature.c | 23 +++++++++++++++++++++++ arch/riscv/kernel/suspend.c | 2 ++ 4 files changed, 49 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..daff95feb817 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -542,6 +542,29 @@ : "memory"); \ }) +#define ALT_CSR_READ(csr) \ +({ \ + unsigned long __v; \ + __asm__ __volatile__ ( \ + ALTERNATIVE("li %[v], 0", "csrr %[v], %[r]", 0, \ + csr << 16 | RISCV_ISA_EXT_ZICSR, 1) \ + : [v] "=r" (__v) \ + : [r] "i" (csr) \ + : "memory"); \ + __v; \ +}) + +#define ALT_CSR_WRITE(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ( \ + ALTERNATIVE("nop", "csrw %[r], %[v]", 0, \ + csr << 16 | RISCV_ISA_EXT_ZICSR, 1) \ + : : [r] "i" (csr), [v] "rK" (__v) \ + : "memory"); \ + __v; \ +}) + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_CSR_H */ diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h index 02f87867389a..491296a335d0 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -14,6 +14,7 @@ struct suspend_context { struct pt_regs regs; /* Saved and restored by high-level functions */ unsigned long scratch; + unsigned long envcfg; unsigned long tvec; unsigned long ie; #ifdef CONFIG_MMU diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c5b13f7dd482..934090270ae5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -954,6 +954,27 @@ void riscv_user_isa_enable(void) } #ifdef CONFIG_RISCV_ALTERNATIVE +static bool riscv_cpufeature_probe_csr(u16 csr) +{ + bool ret = false; + + switch (csr) { +#define PROBE_CSR_CASE(_csr) \ + case _csr: \ + asm("1: csrr zero, %[csr]\n" \ + " li %[r], 1\n" \ + "2:\n" \ + _ASM_EXTABLE(1b, 2b) \ + : [r] "+r" (ret) \ + : [csr] "i" (_csr)); \ + break + PROBE_CSR_CASE(CSR_ENVCFG); +#undef PROBE_CSR_CASE + } + + return ret; +} + /* * Alternative patch sites consider 48 bits when determining when to patch * the old instruction sequence with the new. These bits are broken into a @@ -974,6 +995,8 @@ static bool riscv_cpufeature_patch_check(u16 id, u16 value) return true; switch (id) { + case RISCV_ISA_EXT_ZICSR: + return riscv_cpufeature_probe_csr(value); case RISCV_ISA_EXT_ZICBOZ: /* * Zicboz alternative applications provide the maximum diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 239509367e42..fe544f12a5c5 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -15,6 +15,7 @@ void suspend_save_csrs(struct suspend_context *context) { context->scratch = csr_read(CSR_SCRATCH); + context->envcfg = ALT_CSR_READ(CSR_ENVCFG); context->tvec = csr_read(CSR_TVEC); context->ie = csr_read(CSR_IE); @@ -36,6 +37,7 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { csr_write(CSR_SCRATCH, context->scratch); + ALT_CSR_WRITE(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); csr_write(CSR_IE, context->ie);