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Sun, 11 Feb 2024 22:16:11 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41BMGA3a025148 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 11 Feb 2024 22:16:10 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 11 Feb 2024 14:16:09 -0800 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH] aarch64: Improve PERM<{0}, a, ...> (64bit) by adding whole vector shift right [PR113872] Date: Sun, 11 Feb 2024 14:15:56 -0800 Message-ID: <20240211221556.3121555-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: U44PvzSrKTvR1c5tLj_Km258PvL7m_6a X-Proofpoint-ORIG-GUID: U44PvzSrKTvR1c5tLj_Km258PvL7m_6a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-11_20,2024-02-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 spamscore=0 phishscore=0 mlxscore=0 mlxlogscore=421 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402110177 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790642554466616447 X-GMAIL-MSGID: 1790642554466616447 The backend currently defines a whole vector shift left for 64bit vectors, adding the shift right can also improve code for some PERMs too. So this adds that pattern. I added a testcase for the shift left also. I also fixed the instruction template there which was using a space instead of a tab after the instruction. Built and tested on aarch64-linux-gnu. PR target/113872 gcc/ChangeLog: * config/aarch64/aarch64-simd.md (vec_shr_): Use tab instead of space after the instruction in the template. (vec_shl_): New pattern * config/aarch64/iterators.md (unspec): Add UNSPEC_VEC_SHL gcc/testsuite/ChangeLog: * gcc.target/aarch64/perm_zero-1.c: New test. * gcc.target/aarch64/perm_zero-2.c: New test. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64-simd.md | 18 ++++++++++++++++-- gcc/config/aarch64/iterators.md | 1 + gcc/testsuite/gcc.target/aarch64/perm_zero-1.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/aarch64/perm_zero-2.c | 15 +++++++++++++++ 4 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/perm_zero-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/perm_zero-2.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f8bb973a278..0d2f1ea3902 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1592,9 +1592,23 @@ (define_insn "vec_shr_" "TARGET_SIMD" { if (BYTES_BIG_ENDIAN) - return "shl %d0, %d1, %2"; + return "shl\t%d0, %d1, %2"; else - return "ushr %d0, %d1, %2"; + return "ushr\t%d0, %d1, %2"; + } + [(set_attr "type" "neon_shift_imm")] +) +(define_insn "vec_shl_" + [(set (match_operand:VD 0 "register_operand" "=w") + (unspec:VD [(match_operand:VD 1 "register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VEC_SHL))] + "TARGET_SIMD" + { + if (BYTES_BIG_ENDIAN) + return "ushr\t%d0, %d1, %2"; + else + return "shl\t%d0, %d1, %2"; } [(set_attr "type" "neon_shift_imm")] ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 99cde46f1ba..3aebe9cf18a 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -758,6 +758,7 @@ (define_c_enum "unspec" UNSPEC_PMULL ; Used in aarch64-simd.md. UNSPEC_PMULL2 ; Used in aarch64-simd.md. UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. + UNSPEC_VEC_SHL ; Used in aarch64-simd.md. UNSPEC_VEC_SHR ; Used in aarch64-simd.md. UNSPEC_SQRDMLAH ; Used in aarch64-simd.md. UNSPEC_SQRDMLSH ; Used in aarch64-simd.md. diff --git a/gcc/testsuite/gcc.target/aarch64/perm_zero-1.c b/gcc/testsuite/gcc.target/aarch64/perm_zero-1.c new file mode 100644 index 00000000000..3c8f0591a2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/perm_zero-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* PR target/113872 */ +/* For 64bit vectors, PERM with a constant 0 should produce a shift instead of the ext instruction. */ + +#define vect64 __attribute__((vector_size(8))) + +void f(vect64 unsigned short *a) +{ + *a = __builtin_shufflevector((vect64 unsigned short){0},*a, 3,4,5,6); +} + +/* { dg-final { scan-assembler-times "ushr\t" 1 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times "shl\t" 1 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-not "ext\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/perm_zero-2.c b/gcc/testsuite/gcc.target/aarch64/perm_zero-2.c new file mode 100644 index 00000000000..970e428f832 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/perm_zero-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* PR target/113872 */ +/* For 64bit vectors, PERM with a constant 0 should produce a shift instead of the ext instruction. */ + +#define vect64 __attribute__((vector_size(8))) + +void f(vect64 unsigned short *a) +{ + *a = __builtin_shufflevector(*a, (vect64 unsigned short){0},3,4,5,6); +} + +/* { dg-final { scan-assembler-times "shl\t" 1 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times "ushr\t" 1 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-not "ext\t" } } */