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Fri, 9 Feb 2024 08:08:25 -0700 Received: from che-lt-i70843lx.amer.actel.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 9 Feb 2024 08:08:12 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Rob Herring Subject: [PATCH v4 1/4] dt-bindings: display: bridge: add sam9x75-lvds binding Date: Fri, 9 Feb 2024 20:37:54 +0530 Message-ID: <20240209150757.66914-2-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240209150757.66914-1-dharma.b@microchip.com> References: <20240209150757.66914-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790434483113454154 X-GMAIL-MSGID: 1790434483113454154 Add the 'sam9x75-lvds' compatible binding, which describes the Low Voltage Differential Signaling (LVDS) Controller found on some Microchip's sam9x7 series System-on-Chip (SoC) devices. This binding will be used to define the properties and configuration for the LVDS Controller in DT. Signed-off-by: Dharma Balasubiramani Reviewed-by: Rob Herring --- Changelog v3 -> v4 - Rephrase the commit subject. v2 -> v3 - No changes. v1 -> v2 - Remove '|' in description, as there is no formatting to preserve. - Remove 'gclk' from clock-names as there is only one clock(pclk). - Remove the unused headers and include only used ones. - Change the compatible name specific to SoC (sam9x75) instead of entire series. - Change file name to match the compatible name. --- .../bridge/microchip,sam9x75-lvds.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml new file mode 100644 index 000000000000..862ef441ac9f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/microchip,sam9x75-lvds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip SAM9X75 LVDS Controller + +maintainers: + - Dharma Balasubiramani + +description: + The Low Voltage Differential Signaling Controller (LVDSC) manages data + format conversion from the LCD Controller internal DPI bus to OpenLDI + LVDS output signals. LVDSC functions include bit mapping, balanced mode + management, and serializer. + +properties: + compatible: + const: microchip,sam9x75-lvds + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Peripheral Bus Clock + + clock-names: + items: + - const: pclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + lvds-controller@f8060000 { + compatible = "microchip,sam9x75-lvds"; + reg = <0xf8060000 0x100>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "pclk"; + }; From patchwork Fri Feb 9 15:07:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dharma Balasubiramani X-Patchwork-Id: 198944 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp918590dyd; Fri, 9 Feb 2024 07:10:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IGm8cx0Kz1c8dlcPV0vyWz98NQs9ZbkiJgO4DIBXpUhOXjcrGKR4qijc1S9BLML+MRKxl8R X-Received: by 2002:a05:6a21:3983:b0:19c:9a4a:6606 with SMTP id ad3-20020a056a21398300b0019c9a4a6606mr2256457pzc.13.1707491438968; Fri, 09 Feb 2024 07:10:38 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707491438; cv=pass; d=google.com; s=arc-20160816; b=sllgYu4QD/KUAjmXZVbkfN/0mPQyPyJfb4HwBmSVR5uCDgTNY1KMp2Mrhh5VwmRB3A 24hgHR8h49ysQ4iwjuMXMZRwsno7XoDhdRO/hIQI3CDfwyqwSmu41OdZhxY9eoCi5AsZ A3FNEtZ0VX82hbIkQwJwMJCJFTyTYLhAEMgSG3kwOEKcCKSzB9mzO5B0srRGKZhNBch8 hrbITtEPqvpxc1+N2sm6PRr6VkFYif76czVlWkPvYveudZAnt3mf3lSZBRCEmyobJ8iZ W2f87AxsOYS+OhE1DoVyMSupS56c36evgH8BdMNZpq3SyOFefGSytxFm6+5IBjWlvPYH Glkg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:to:from:dkim-signature; bh=LRb4qxm/GDJzDbhKIkNgVTnks+gzZSXnllucDuWAH4k=; fh=5s2szDlMF9W/xFqPKsWWo7aJe48t5MmbKr9Y9FfoUxU=; b=AbmvPSPNTQOEcukqEE4UyuY6v4GAJ8HAp+lpqz7dWUa3UqNDz2KLkrdwu1sSkXCMeT uRj0UvrGOJdnWyDAo/xIA2W0ZbHvRIuFwGMS9a5dPG4ueSyiBZlqqgkgonOUxYPvHW6j jj+s0UwbXkBGvOmWiHz4GZHeflFMRLi92OX+GqQ5RULNI7qcsS2HwppMxDQRmRbwuWOV cg7/A4oKzvFOzcqYQ/WAnI0FnDVe4jhz8uWy+tPgBEngrv0ekDwDr03uwMj8wz2aLFXC J69Mhn3/i8SHRgr6R6fHxwU3htR6K5PCusl+Ld7dqZTNpTzxtBbi8uXthgiAttUASaFd EWLg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=ku2iSXtK; arc=pass (i=1 spf=pass spfdomain=microchip.com dkim=pass dkdomain=microchip.com dmarc=pass fromdomain=microchip.com); spf=pass (google.com: domain of linux-kernel+bounces-59509-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-59509-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=microchip.com X-Forwarded-Encrypted: i=2; AJvYcCVWeojRfCvJLoedYXpzSy2RGNIpQIkSo6T2dwdbHTkbnKU4RUDT0jjqGtEWukaGLeT2n7W2IHuT7vWVgZ2Z8bZl7X+A0A== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Fri, 9 Feb 2024 08:08:37 -0700 Received: from che-lt-i70843lx.amer.actel.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 9 Feb 2024 08:08:25 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 2/4] drm/bridge: add lvds controller support for sam9x7 Date: Fri, 9 Feb 2024 20:37:55 +0530 Message-ID: <20240209150757.66914-3-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240209150757.66914-1-dharma.b@microchip.com> References: <20240209150757.66914-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790434542907437167 X-GMAIL-MSGID: 1790434542907437167 Add a new LVDS controller driver for sam9x7 which does the following: - Prepares and enables the LVDS Peripheral clock - Defines its connector type as DRM_MODE_CONNECTOR_LVDS and adds itself to the global bridge list. - Identifies its output endpoint as panel and adds it to the encoder display pipeline - Enables the LVDS serializer Signed-off-by: Manikandan Muralidharan Signed-off-by: Dharma Balasubiramani --- Changelog v3 -> v4 - No changes. v2 ->v3 - Correct Typo error "serializer". - Consolidate get() and prepare() functions and use devm_clk_get_prepared(). - Remove unused variable 'ret' in probe(). - Use devm_pm_runtime_enable() and drop the mchp_lvds_remove(). v1 -> v2 - Drop 'res' variable and combine two lines into one. - Handle deferred probe properly, use dev_err_probe(). - Don't print anything on deferred probe. Dropped print. - Remove the MODULE_ALIAS and add MODULE_DEVICE_TABLE(). - symbol 'mchp_lvds_driver' was not declared. It should be static. --- drivers/gpu/drm/bridge/Kconfig | 7 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/microchip-lvds.c | 228 ++++++++++++++++++++++++ 3 files changed, 236 insertions(+) create mode 100644 drivers/gpu/drm/bridge/microchip-lvds.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 3e6a4e2044c0..74ca0edb4e0d 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -173,6 +173,13 @@ config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW to DP++. This is used with the i.MX6 imx-ldb driver. You are likely to say N here. +config DRM_MICROCHIP_LVDS_SERIALIZER + tristate "Microchip LVDS serializer support" + depends on OF + depends on DRM_ATMEL_HLCDC + help + Support for Microchip's LVDS serializer. + config DRM_NWL_MIPI_DSI tristate "Northwest Logic MIPI DSI Host controller" depends on DRM diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 2b892b7ed59e..e3804e93d324 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o +obj-$(CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER) += microchip-lvds.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/bridge/microchip-lvds.c new file mode 100644 index 000000000000..d3fd9d722e36 --- /dev/null +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan + * Author: Dharma Balasubiramani + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define LVDS_POLL_TIMEOUT_MS 1000 + +/* LVDSC register offsets */ +#define LVDSC_CR 0x00 +#define LVDSC_CFGR 0x04 +#define LVDSC_SR 0x0C +#define LVDSC_WPMR 0xE4 + +/* Bitfields in LVDSC_CR (Control Register) */ +#define LVDSC_CR_SER_EN BIT(0) + +/* Bitfields in LVDSC_CFGR (Configuration Register) */ +#define LVDSC_CFGR_PIXSIZE_24BITS 0 +#define LVDSC_CFGR_DEN_POL_HIGH 0 +#define LVDSC_CFGR_DC_UNBALANCED 0 +#define LVDSC_CFGR_MAPPING_JEIDA BIT(6) + +/*Bitfields in LVDSC_SR */ +#define LVDSC_SR_CS BIT(0) + +/* Bitfields in LVDSC_WPMR (Write Protection Mode Register) */ +#define LVDSC_WPMR_WPKEY_MASK GENMASK(31, 8) +#define LVDSC_WPMR_WPKEY_PSSWD 0x4C5644 + +struct mchp_lvds { + struct device *dev; + void __iomem *regs; + struct clk *pclk; + int format; /* vesa or jeida format */ + struct drm_panel *panel; + struct drm_bridge bridge; + struct drm_bridge *panel_bridge; +}; + +static inline struct mchp_lvds *bridge_to_lvds(struct drm_bridge *bridge) +{ + return container_of(bridge, struct mchp_lvds, bridge); +} + +static inline u32 lvds_readl(struct mchp_lvds *lvds, u32 offset) +{ + return readl_relaxed(lvds->regs + offset); +} + +static inline void lvds_writel(struct mchp_lvds *lvds, u32 offset, u32 val) +{ + writel_relaxed(val, lvds->regs + offset); +} + +static void lvds_serialiser_on(struct mchp_lvds *lvds) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(LVDS_POLL_TIMEOUT_MS); + + /* The LVDSC registers can only be written if WPEN is cleared */ + lvds_writel(lvds, LVDSC_WPMR, (LVDSC_WPMR_WPKEY_PSSWD & + LVDSC_WPMR_WPKEY_MASK)); + + /* Wait for the status of configuration registers to be changed */ + while (lvds_readl(lvds, LVDSC_SR) & LVDSC_SR_CS) { + if (time_after(jiffies, timeout)) { + dev_err(lvds->dev, "%s: timeout error\n", __func__); + return; + } + usleep_range(1000, 2000); + } + + /* Configure the LVDSC */ + lvds_writel(lvds, LVDSC_CFGR, (LVDSC_CFGR_MAPPING_JEIDA | + LVDSC_CFGR_DC_UNBALANCED | + LVDSC_CFGR_DEN_POL_HIGH | + LVDSC_CFGR_PIXSIZE_24BITS)); + + /* Enable the LVDS serializer */ + lvds_writel(lvds, LVDSC_CR, LVDSC_CR_SER_EN); +} + +static int mchp_lvds_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct mchp_lvds *lvds = bridge_to_lvds(bridge); + + bridge->encoder->encoder_type = DRM_MODE_ENCODER_LVDS; + + return drm_bridge_attach(bridge->encoder, lvds->panel_bridge, + bridge, flags); +} + +static void mchp_lvds_enable(struct drm_bridge *bridge) +{ + struct mchp_lvds *lvds = bridge_to_lvds(bridge); + int ret; + + ret = clk_enable(lvds->pclk); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); + return; + } + + ret = pm_runtime_get_sync(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + clk_disable(lvds->pclk); + return; + } + + lvds_serialiser_on(lvds); +} + +static void mchp_lvds_disable(struct drm_bridge *bridge) +{ + struct mchp_lvds *lvds = bridge_to_lvds(bridge); + + pm_runtime_put(lvds->dev); + clk_disable(lvds->pclk); +} + +static const struct drm_bridge_funcs mchp_lvds_bridge_funcs = { + .attach = mchp_lvds_attach, + .enable = mchp_lvds_enable, + .disable = mchp_lvds_disable, +}; + +static int mchp_lvds_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mchp_lvds *lvds; + struct device_node *port; + + if (!dev->of_node) + return -ENODEV; + + lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL); + if (!lvds) + return -ENOMEM; + + lvds->dev = dev; + + lvds->regs = devm_ioremap_resource(lvds->dev, + platform_get_resource(pdev, IORESOURCE_MEM, 0)); + if (IS_ERR(lvds->regs)) + return PTR_ERR(lvds->regs); + + lvds->pclk = devm_clk_get_prepared(lvds->dev, "pclk"); + if (IS_ERR(lvds->pclk)) + return dev_err_probe(lvds->dev, PTR_ERR(lvds->pclk), + "could not get pclk_lvds prepared\n"); + + port = of_graph_get_remote_node(dev->of_node, 1, 0); + if (!port) { + DRM_DEV_ERROR(dev, + "can't find port point, please init lvds panel port!\n"); + return -EINVAL; + } + + lvds->panel = of_drm_find_panel(port); + of_node_put(port); + + if (IS_ERR(lvds->panel)) + return -EPROBE_DEFER; + + lvds->panel_bridge = devm_drm_panel_bridge_add(dev, lvds->panel); + + if (IS_ERR(lvds->panel_bridge)) + return PTR_ERR(lvds->panel_bridge); + + lvds->bridge.of_node = dev->of_node; + lvds->bridge.type = DRM_MODE_CONNECTOR_LVDS; + lvds->bridge.funcs = &mchp_lvds_bridge_funcs; + + dev_set_drvdata(dev, lvds); + devm_pm_runtime_enable(dev); + + drm_bridge_add(&lvds->bridge); + + return 0; +} + +static const struct of_device_id mchp_lvds_dt_ids[] = { + { + .compatible = "microchip,sam9x75-lvds", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mchp_lvds_dt_ids); + +static struct platform_driver mchp_lvds_driver = { + .probe = mchp_lvds_probe, + .driver = { + .name = "microchip-lvds", + .of_match_table = mchp_lvds_dt_ids, + }, +}; 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Fri, 9 Feb 2024 08:08:49 -0700 Received: from che-lt-i70843lx.amer.actel.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 9 Feb 2024 08:08:37 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 3/4] MAINTAINERS: add SAM9X7 SoC's LVDS controller Date: Fri, 9 Feb 2024 20:37:56 +0530 Message-ID: <20240209150757.66914-4-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240209150757.66914-1-dharma.b@microchip.com> References: <20240209150757.66914-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790434965144860603 X-GMAIL-MSGID: 1790434965144860603 Add the newly added LVDS controller for the SAM9X7 SoC to the existing MAINTAINERS entry. Signed-off-by: Dharma Balasubiramani Reviewed-by: Neil Armstrong Acked-by: Nicolas Ferre --- Changelog v3 ->v4 - No changes. v2 -> v3 - Move the entry before "MICROCHIP SAMA5D2-COMPATIBLE ADC DRIVER". v1 -> v2 - No Changes. --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a7c4cf8201e0..ce592b6cf375 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14216,6 +14216,14 @@ S: Supported F: Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml F: drivers/pwm/pwm-atmel.c +MICROCHIP SAM9x7-COMPATIBLE LVDS CONTROLLER +M: Manikandan Muralidharan +M: Dharma Balasubiramani +L: dri-devel@lists.freedesktop.org +S: Supported +F: Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvds.yaml +F: drivers/gpu/drm/bridge/microchip-lvds.c + MICROCHIP SAMA5D2-COMPATIBLE ADC DRIVER M: Eugen Hristev L: linux-iio@vger.kernel.org From patchwork Fri Feb 9 15:07:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dharma Balasubiramani X-Patchwork-Id: 198948 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp923887dyd; Fri, 9 Feb 2024 07:17:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IEfcsnIVX2sOLRKdYjRsqQTaux1aD8Nk4xJoWK/N9E7bh+MFnf9ntc8AD2IADQQDyNt6VqR X-Received: by 2002:a05:6402:5172:b0:560:1c4:cb31 with SMTP id d18-20020a056402517200b0056001c4cb31mr1778850ede.17.1707491872828; Fri, 09 Feb 2024 07:17:52 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707491872; cv=pass; d=google.com; s=arc-20160816; b=LdnUNTaGPS32EqtSXcMCvw+drOAOYTp3hANQyKBu5o+KOhaJIQL4/cLFcRkP3EXLqC 3CVJKXSjROic+P6gRteF7zvSo2BR1cREFZ4Qh3DTtiPKtbI/FG2dpwu2KonMkUs4zIFh mhHZZtYj63sRhaI+ARVZZG4iUlPbOV2RwHl7Xlb4tbmqEyBq9GaFocuJPZycdFZZLExn Xrl1tch1gzvbCvnzZ5D9clAW8L/TZJ6+eRWK2Z9CkButnxJ1G26c6otk14h/w0IwDsIN sBBt9iOCK6ANh90F48NeFipl3qPq7DQyRHIoygFHkzNceWHbhKIqhTAJSWx5iKMgdAdt auLw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:to:from:dkim-signature; bh=L1snpPAjd/lRqAyyncvZEAbBcT/xPZMLZxq8+x/buWw=; fh=SMf9KabK89bprkgt7y1jwmCAYqmE7CqxzzuxRHfNkBE=; b=LDnEJ46KfOiF+C9wBNXL5JfjsIlSFJQCs/cv+YAK4zRowIvnvQLGsdW28svapL0XX3 bNyBmZ49VvjH5gfgxaQXLTXvOgd43ijO7aU7tK9+T9RAeZARlsiZUzdVjzFhKCMUkTsB 6GeBBCi+85g18QECIUyaroj00/+OYOywJJ6wD38UL/uLg0tAYbxVlP1wEop/6nW6/wup YSlkd6pZPJ9IhUw8BOnmgljd8P+Yi/i1ynn+bMi9PRzDuBpwsTCH/dBnh83Hi09D6N3m LmPDcME62wEwJT2LP7OWpdIQNNRNiRx6gNbPsybmT/YJXK+msySNB86UVqDXSMnmrXOt AVOA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=W00OKl0h; arc=pass (i=1 spf=pass spfdomain=microchip.com dkim=pass dkdomain=microchip.com dmarc=pass fromdomain=microchip.com); spf=pass (google.com: domain of linux-kernel+bounces-59512-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-59512-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=microchip.com X-Forwarded-Encrypted: i=2; AJvYcCWqjxVjGL+pllAeUD67GyK7aEjqDCNGZqYNyhjoxYGrQyW4CQ0dXxiLg3rzsiSZVOHusYtC2VyqEKsMRqxa5K2VN92axQ== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Fri, 9 Feb 2024 08:09:01 -0700 Received: from che-lt-i70843lx.amer.actel.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 9 Feb 2024 08:08:49 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 4/4] ARM: configs: at91: Enable LVDS serializer support Date: Fri, 9 Feb 2024 20:37:57 +0530 Message-ID: <20240209150757.66914-5-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240209150757.66914-1-dharma.b@microchip.com> References: <20240209150757.66914-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790434998355370916 X-GMAIL-MSGID: 1790434998355370916 Enable LVDS serializer support for display pipeline. Signed-off-by: Dharma Balasubiramani Acked-by: Hari Prasath Gujulan Elango Acked-by: Nicolas Ferre --- Changelog v3 -> v4 - No Changes. v2 -> v3 - No Changes. --- arch/arm/configs/at91_dt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 71b5acc78187..6a7714beb099 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -143,6 +143,7 @@ CONFIG_VIDEO_OV2640=m CONFIG_VIDEO_OV7740=m CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=y +CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_FB_ATMEL=y