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a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790340213171205156 X-GMAIL-MSGID: 1790340213171205156 Add the overlay dtbo file to a Makefile target so it can be picked by the dtbs_install command. Fixes: b8690ed3d1d1 ("arm64: dts: ti: am65x: Add Rocktech OLDI panel DT overlay") Signed-off-by: Roger Quadros Reviewed-by: Aradhya Bhatia --- Changelog: v2: no change v1: https://lore.kernel.org/all/20240126114530.40913-2-rogerq@kernel.org/ --- arch/arm64/boot/dts/ti/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 4a570dffb638..bfcc86ff8e24 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board-rocktech-rk101-panel.dtbo # Boards with J7200 SoC k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo From patchwork Thu Feb 8 13:51:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 198430 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp188874dyd; Thu, 8 Feb 2024 06:06:38 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCV17JMDmOs8GuUChRPTBUII8ZAiRmB0/Fhgkz9oHn2typIJAI/7ARQpfzG23URh9lZYkMlUwKsIAKltoD8rrxYvqS3oHQ== X-Google-Smtp-Source: AGHT+IG0eWfHtxX4b8RNJvdf+lP9OmIxtLPDJ8G4lvCn/Mys/eCWzAa213S8bBfGgz6uE6mgDQ/4 X-Received: by 2002:a05:6820:2290:b0:59c:f0eb:be1f with SMTP id ck16-20020a056820229000b0059cf0ebbe1fmr8916013oob.6.1707401198175; Thu, 08 Feb 2024 06:06:38 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707401198; cv=pass; d=google.com; s=arc-20160816; b=eqjS3LcoTAPO8yLnD01cnlu0P4jlFngTF/0MqreLqYX6AYUHpHjgT72pmDaUekVmRK Lk8QmxYPldhgP6LhWV9OzZ6KkIQxd2jIEYjoN1FG6gFCwWU207y4h8FlIJa29G2FYLde bEQKnFTgIC03oOjPuAKu0tRIKDGiRxewlelKJTYnOIbGdk8m+dYwVq9ZrkzDkW+mIpE6 v2rlE1+GQz4mlvsWmxJ2Ib6hmhl1SmsEm9+gZaa0AXBCUrwCWJVYGizPQtfnmDPn0lEJ goXN8bddJVXmxPQRqDIAVivDcEcFduSSIED1B81TeDLGPfsCWP5xf7v5LMjnFEnFnb6m xKtg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=ZLMRRIl2fzZVqDbpB84UAWIhM0JNtUUxByvfpfPvby0=; fh=Tfsgx7LZ2pIoLFRaqPZAed6Vm10ytyzsVkZQONdTLBQ=; b=ZpCZl9eiiUtcOi4QxpyFF9Rb3CX+iZjDs7WIeg/6ehag590zLS18hSYBpi9zZpknUz rMHc3w+r19DvLTp2koMkcoRBdI67BlbeS5CdHZUC5r/8xKLAKwkHzXkRNzlblIshzJuu yB9SrKRgJeZUch4QtTMTq2CbeJZhG7yKuH7B6G0zlWTWtwuoXbSyFBWXmyFjXwCqpqC3 fuhYlqJBNx0DlmnhGl4v1GndKN185jCYG/QOx3KgVcNXMCLYAGz7urzPtHtoPk0JpN05 R3zz8iNTuen5dXP71d57Z7DdzndrybWTHcMakpgvFtjeRQMLizFT91YuXvyAXMgEuXxA 6r4g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=iQBGrYby; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-58190-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58190-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org X-Forwarded-Encrypted: i=2; AJvYcCV38eKCrEy99LS3YEOppJ+yUwzaDiv9itheznYZmtna6l4qyXTwbV5wA9L7kHoeTJJDwb1r3H3/bUfHWristy202+MHyA== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339918848708366 X-GMAIL-MSGID: 1790339918848708366 From: Roger Quadros Enable both SERDES and PCIe DT nodes in order to get PCIe working on the SERDES PCIe x2 personality card. The daughter card also has a USB 2.0 dual-role port. As the base board already supports a 2.0 dual-role port, enable the port on the SERDES card to be a host only port. This will prevent user confusion as having 2 ports in device mode often leads to confusion as to which port is bound to the gadget function driver. The PCIe x2 card is provided with the AM65x IDK configuration [1] so apply the overlay to k3-am654-idk.dtb [1] https://www.ti.com/lit/ug/spruim6a/spruim6a.pdf Co-developed-by: Kishon Vijay Abraham I Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Roger Quadros --- Changelog: v2: - Drop PCIe endpoint settings as it no longer exists in base tree. v1: https://lore.kernel.org/all/20240126114530.40913-3-rogerq@kernel.org/ --- arch/arm64/boot/dts/ti/Makefile | 3 +- arch/arm64/boot/dts/ti/k3-am654-pcie-usb2.dtso | 59 ++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index bfcc86ff8e24..f534c373c958 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -47,7 +47,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo # Boards with AM65x SoC k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo k3-am654-evm-dtbs := k3-am654-base-board.dtb k3-am654-icssg2.dtbo -k3-am654-idk-dtbs := k3-am654-evm.dtb k3-am654-idk.dtbo +k3-am654-idk-dtbs := k3-am654-evm.dtb k3-am654-idk.dtbo k3-am654-pcie-usb2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb @@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board-rocktech-rk101-panel.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am654-pcie-usb2.dtbo # Boards with J7200 SoC k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am654-pcie-usb2.dtso b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb2.dtso new file mode 100644 index 000000000000..dd701e0c1750 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb2.dtso @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include +#include +#include "k3-pinctrl.h" + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, + <&serdes0 AM654_SERDES_CMU_REFCLK>, + <&serdes0 AM654_SERDES_RO_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, + <&k3_clks 153 4>, + <&k3_clks 153 4>; + status = "okay"; +}; + +&serdes1 { + assigned-clocks = <&serdes1 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&serdes0 AM654_SERDES_RO_REFCLK>; + status = "okay"; +}; + +&pcie0_rc { + num-lanes = <2>; + phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0", "pcie-phy1"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_pmx0 { + usb0_pins_default: usb0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&dwc3_0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; +}; From patchwork Thu Feb 8 13:51:45 2024 Content-Type: text/plain; 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a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339269680129307 X-GMAIL-MSGID: 1790339269680129307 From: Kishon Vijay Abraham I Add overlay for PCIe (uses the second instance of PCIe in AM654x) and USB3.0 SERDES personality card The PCI3/USB3 card is provided with the AM65x GP EVM configurtion [1] so apply the overlay to k3-am654-gp-evm.dtb [1] https://www.ti.com/lit/ug/spruim7/spruim7.pdf Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Roger Quadros --- Changelog: v2: - drop PCIe endpoint settings as it no longer exists in base tree. v1: https://lore.kernel.org/all/20240126114530.40913-4-rogerq@kernel.org/ --- arch/arm64/boot/dts/ti/Makefile | 5 ++- arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso | 61 ++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index f534c373c958..75033b6e8693 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -45,7 +45,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo # Boards with AM65x SoC -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo +k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \ + k3-am654-base-board-rocktech-rk101-panel.dtbo \ + k3-am654-pcie-usb3.dtbo k3-am654-evm-dtbs := k3-am654-base-board.dtb k3-am654-icssg2.dtbo k3-am654-idk-dtbs := k3-am654-evm.dtb k3-am654-idk.dtbo k3-am654-pcie-usb2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb @@ -59,6 +61,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board-rocktech-rk101-panel.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am654-pcie-usb2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am654-pcie-usb3.dtbo # Boards with J7200 SoC k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso new file mode 100644 index 000000000000..e463163f2b7b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include +#include + +#include "k3-pinctrl.h" + +&serdes1 { + status = "okay"; +}; + +&pcie1_rc { + num-lanes = <1>; + phys = <&serdes1 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_pmx0 { + usb0_pins_default: usb0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&serdes0 { + status = "okay"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + status = "okay"; + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; + +&usb0_phy { + status = "okay"; +};